JP2854166B2 - Ferroelectric memory - Google Patents
Ferroelectric memoryInfo
- Publication number
- JP2854166B2 JP2854166B2 JP3186196A JP18619691A JP2854166B2 JP 2854166 B2 JP2854166 B2 JP 2854166B2 JP 3186196 A JP3186196 A JP 3186196A JP 18619691 A JP18619691 A JP 18619691A JP 2854166 B2 JP2854166 B2 JP 2854166B2
- Authority
- JP
- Japan
- Prior art keywords
- ferroelectric
- electrodes
- electrode
- memory
- ferroelectric memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5657—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、強誘電コンデンサを用
いた強誘電体メモリに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory using a ferroelectric capacitor.
【0002】[0002]
【従来の技術】近時、強誘電コンデンサをメモリに用い
て2値の電荷量を保持させるものが用いられてきた。2. Description of the Related Art In recent years, a ferroelectric capacitor used as a memory to hold a binary charge has been used.
【0003】[0003]
【発明が解決しようとする課題】しかし乍ら、この種従
来の強誘電体メモリは、1個の強誘電コンデンサに2値
の電荷量を保持できるもので、複数値の電荷量を保持さ
せるためにはその数に応じた複数個の強誘電コンデンサ
を必要とするものであった。However, in this type of conventional ferroelectric memory, a single ferroelectric capacitor can hold a binary charge amount. Requires a plurality of ferroelectric capacitors corresponding to the number.
【0004】[0004]
【課題を解決するための手段】本発明は、見かけ上1個
の強誘電体の表面と裏面に夫々多数の電極を設け、該電
極の中から表面と裏面で夫々1つづつの電極を選択的に
選んで強誘電体メモリとして用いることにより、選択的
に選んだ数だけの電荷量を保持することができるように
したものである。According to the present invention, apparently, a large number of electrodes are provided on the front surface and the back surface of one ferroelectric, respectively, and one electrode is selectively selected from the electrodes on the front surface and the back surface, respectively. And using it as a ferroelectric memory, it is possible to hold a selectively selected number of charges.
【0005】たとえば、本発明の強誘電体メモリとし
て、1個の強誘電体の表面と裏面に夫々2個の電極A,
BとC,Dを互いに隣接して設け、前記電極の中から表
面と裏面に夫々1個づつの電極を選択して、AC,A
D,BC,BDの中から一つづつを特定できるようにす
ると、電極の位置AC,AD,BC,BDに応じて3つ
以上の異なる分極状態を得ることができるようにしたも
のである。For example, as a ferroelectric memory of the present invention, two electrodes A,
B, C, and D are provided adjacent to each other, and one electrode is selected on each of the front surface and the back surface from among the electrodes.
If each of D, BC, and BD can be specified one by one, three or more different polarization states can be obtained according to the electrode positions AC, AD, BC, and BD.
【0006】[0006]
【作用】したがって、前記の如き構成よりなる本発明の
強誘電体メモリによって、1個の強誘電コンデンサで複
数個の電荷量を保持させることができるために、簡単な
構造で複数値をメモリできる強誘電体メモリをメモリ素
子として提供できるものである。According to the ferroelectric memory of the present invention having the above-described structure, a single ferroelectric capacitor can hold a plurality of charges, so that a plurality of values can be stored with a simple structure. A ferroelectric memory can be provided as a memory element.
【0007】したがって、単位セル当りの情報量を3値
以上に増加させることができるものである。たとえば、
単位セル当りの情報量が2値から4値以上になり、セル
面積を変えることなく、単位面積当りの情報量を飛躍的
に増大することが可能となるものである。Therefore, the amount of information per unit cell can be increased to three values or more. For example,
The information amount per unit cell increases from two values to four or more values, and the information amount per unit area can be dramatically increased without changing the cell area.
【0008】[0008]
【実施例】以下、本発明を図面に示す一実施例について
説明する。図1は、本発明の強誘電体メモリの一実施例
を示す回路図、図2は図1の回路図の電界一分極の特性
図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the ferroelectric memory of the present invention, and FIG. 2 is a characteristic diagram of electric field versus polarization in the circuit diagram of FIG.
【0009】図1に示す強誘電コンデンサ50は、1個
の強誘電体の表面と裏面に夫々隣接する複数の電極6
1,62,63,64を有しており、裏面の電極62,
64を基準電位ライン30,31に接合する一方、表面
の電極61,63に夫々FET40,41を接続する。
基準電位ライン30,31は通常の基準電位であり、好
ましくは接地されているが、ライン30,31はそれに
印加されるゼロでない電圧パルスを保有することができ
る。コンデンサ50の表面の電極61,63は電界効果
トランジスタ(FET)40,41のソース、ドレイン
を経てビットライン20,21に結合させる。A ferroelectric capacitor 50 shown in FIG. 1 has a plurality of electrodes 6 adjacent to the front and back surfaces of one ferroelectric material, respectively.
1, 62, 63, 64, and the electrodes 62,
64 is connected to the reference potential lines 30 and 31, while the FETs 40 and 41 are connected to the electrodes 61 and 63 on the surface, respectively.
The reference potential lines 30, 31 are at a normal reference potential and are preferably grounded, but the lines 30, 31 can carry non-zero voltage pulses applied thereto. The electrodes 61 and 63 on the surface of the capacitor 50 are coupled to the bit lines 20 and 21 via the sources and drains of the field effect transistors (FETs) 40 and 41.
【0010】図1のFET40,41はNチャンネルデ
バイスであり、従ってこのFET40,41のドレイン
電極Dをビットライン20,21に結合させるのに対
し、FET26のソース電極Sはコンデンサ50の表面
電極61,63に結合させる。ゲート電極Gは別個に制
御されるワードライン10に結合させる。なお本発明に
は必ずしもNチャンネルFETを用いる必要はなく、他
のスイッチングデバイスを用いることもできる。The FETs 40 and 41 of FIG. 1 are N-channel devices, so that the drain electrodes D of the FETs 40 and 41 are coupled to the bit lines 20 and 21, whereas the source electrode S of the FET 26 is the surface electrode 61 of the capacitor 50. , 63. The gate electrode G is coupled to a separately controlled word line 10. In the present invention, it is not always necessary to use an N-channel FET, and other switching devices can be used.
【0011】図1の強誘電体メモリ50で、電極61,
62を用いた場合の電界一分極特性は、図2ではBDで
C=P(0)を通る曲線となり、電極63,64を用い
た場合は、図2のDBでE=P(1)を通る曲線とな
り、電極61,64を用いた場合は、図2のFHでG=
P(2)を通る曲線となり、電極63,62を用いた場
合は、図2のHFでI=P(3)を通る曲線となる。In the ferroelectric memory 50 shown in FIG.
In FIG. 2, the electric field-polarization characteristic when using the electrode 62 is a curve passing C = P (0) in the case of BD, and when using the electrodes 63 and 64, E = P (1) in the DB of FIG. When electrodes 61 and 64 are used, G = FH in FIG.
When the electrodes 63 and 62 are used, the curve passes through I = P (3) when the electrodes 63 and 62 are used.
【0012】したがって、FET40,41をON,O
FFして電極の組61,62;63,64;61,6
4;63,62;のいづれか1つを選択的に特定するよ
うにすると、P(0),P(2),P(3),P(1)
の4値の電荷量を得ることができる。Therefore, the FETs 40 and 41 are turned ON, O
FF and set of electrodes 61, 62; 63, 64; 61, 6
4, 63, 62; P (0), P (2), P (3), P (1)
Can be obtained.
【0013】上記実施例に詳記した如く、本発明の強誘
電体メモリにおいては、隣接する複数個の電極を設けた
1個の強誘電体の各電極に対し、適切なるパルス電界を
与えることにより、1つの強誘電体に対して2値以上の
分極反転状態を生じせしめ、これにより、1セル当りの
記憶容量を増加せしめる事ができるようになる。As described in detail in the above embodiment, in the ferroelectric memory of the present invention, an appropriate pulse electric field is applied to each electrode of one ferroelectric material provided with a plurality of adjacent electrodes. As a result, two or more polarization inversion states are generated for one ferroelectric substance, and thereby, the storage capacity per cell can be increased.
【0014】[0014]
【発明の効果】一つの強誘電体を用いることにより、電
極により挟まれた各部分の特性をほぼ同一とすることが
できるため、例えば同一の電圧を印加すれば各部分に同
じような分極状態が生じ、メモリの書き込み動作及び読
み取り動作等の制御を容易に行うことができる。又、複
数の強誘電体を製造する必要がないため、製造工程を簡
略化することも可能になる。更に1個の強誘電体の各部
分の分極状態で、全体として3つ以上の異なる分極状態
が可能となることにより、コンパクトなセル面積でメモ
リを構成することができ、さらに多値によるメモリ制御
も可能になる。By using one ferroelectric substance, the characteristics of each portion sandwiched between the electrodes can be made substantially the same. For example, when the same voltage is applied, the same polarization state is applied to each portion. And the control of the write operation and the read operation of the memory can be easily performed. Further, since there is no need to manufacture a plurality of ferroelectrics, the manufacturing process can be simplified. Further, three or more different polarization states are possible as a whole in the polarization state of each part of one ferroelectric substance, so that a memory can be configured with a compact cell area, and furthermore, memory control by multi-valued memory. Also becomes possible.
【図1】 本発明の強誘電体メモリの一実施例を示す電
気回路図である。FIG. 1 is an electric circuit diagram showing one embodiment of a ferroelectric memory of the present invention.
【図2】 図1の電気回路図の電界・分極の特性図であ
る。FIG. 2 is a characteristic diagram of electric field and polarization in the electric circuit diagram of FIG.
10 WL 20 BL 21 BL 30 DL 基準電位ライン 31 DL 基準電位ライン 40 FET 41 FET 50 強誘電体 61 表頂部電極 62 裏面部電極 63 表面部電極 64 裏面部電極 10 WL 20 BL 21 BL 30 DL Reference potential line 31 DL Reference potential line 40 FET 41 FET 50 Ferroelectric 61 Top electrode 62 Back electrode 63 Front electrode 64 Back electrode
Claims (1)
の面側に設けられた少なくとも2つの電極からなる第1
電極群と、前記強誘電体の他方の面側に前記第1電極群
と対向するように設けられた少なくとも2つの電極から
なる第2電極群と、前記第1電極群から選択された電極
及び前記第2電極群から選択された電極に電圧を印加す
ることで、前記強誘電体に3つ以上の異なる分極状態を
生じさせる手段とを備えたことを特徴とする強誘電体メ
モリ。1. A first ferroelectric material comprising: one ferroelectric; and at least two electrodes provided on one surface of the ferroelectric.
An electrode group, a second electrode group including at least two electrodes provided on the other surface side of the ferroelectric so as to face the first electrode group, and an electrode selected from the first electrode group. Means for applying a voltage to an electrode selected from the second electrode group to cause the ferroelectric to generate three or more different polarization states.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3186196A JP2854166B2 (en) | 1991-07-25 | 1991-07-25 | Ferroelectric memory |
| US07/876,186 US5291436A (en) | 1991-07-25 | 1992-04-30 | Ferroelectric memory with multiple-value storage states |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3186196A JP2854166B2 (en) | 1991-07-25 | 1991-07-25 | Ferroelectric memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0528774A JPH0528774A (en) | 1993-02-05 |
| JP2854166B2 true JP2854166B2 (en) | 1999-02-03 |
Family
ID=16184067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3186196A Expired - Fee Related JP2854166B2 (en) | 1991-07-25 | 1991-07-25 | Ferroelectric memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2854166B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10017368B4 (en) * | 2000-04-07 | 2005-12-15 | Infineon Technologies Ag | Method for operating an integrated memory |
-
1991
- 1991-07-25 JP JP3186196A patent/JP2854166B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0528774A (en) | 1993-02-05 |
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