JP2854433B2 - Line memory control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for performing image processing such as a spatial filter operation while enlarging or reducing an image at an arbitrary magnification.

[0002] Image processing technology has been used in various fields, and the market is expected to expand further in the future.
Above all, in the printing and publishing-related fields, the introduction of this technology is being rapidly promoted for the purpose of streamlining and simplifying work.
One of the most frequently used processes in this field is image scaling. For example, when a newspaper is created, when an operator freely edits a sheet of paper, an appropriate sheet of paper is created while enlarging or reducing an image or the like. In recent years, speeding up of the enlargement / reduction processing has been required. For this reason, there is a need to increase the efficiency of processing accompanying enlargement / reduction.

[0003]

2. Description of the Related Art FIG. 3 is a diagram for explaining a conventional technique. Conventionally, as shown in FIG.
Is enlarged by coordinate transformation, and this transformed image 35 is created on the work memory. After that, an output image 36 is created by performing processes such as a spatial filter and halftoning. In the coordinate conversion, as shown in FIG. 3B, each coordinate of the input image 34 is calculated based on a conversion formula to obtain output coordinates.

[0004]

In such a conventional method, after a coordinate conversion process is performed on an input image to create a converted image, a process such as a spatial filter is performed on the converted image. Requires a large memory area to temporarily store the data. Also, since the process of coordinate transformation and the process of spatial filter etc. are performed in two stages,
It took a lot of time for the whole image processing. Further, there is a problem that coordinate conversion, which is a method of enlargement, requires a lot of time by itself.

The present invention has been made in view of the above problems, and has as its object to provide an image processing apparatus capable of performing image processing at high speed using a small-capacity memory.

[0006]

According to the invention, the above-mentioned object is achieved by the means described in the claims.

More specifically, a first aspect of the present invention is a control circuit for performing enlargement or reduction processing on image data transferred to a line memory on a line basis in the image processing apparatus, wherein the screen is represented by a fraction. When an arbitrary magnification in the horizontal direction is specified, an X-direction numerator register for storing the number of the numerator, an X-direction denominator register for storing the number of the denominator, the X-direction numerator register and the X-direction First to select and output one of the contents of the denominator register
, A first register for storing a surplus value for arithmetic processing for enlarging or reducing the screen in the horizontal direction, a surplus value of the first register, and an output from the first multiplexer A first pulse that outputs a pulse according to the sign of the remaining value of the first register at the same time as storing the result in the first register.
The first DDA involved in the process of enlarging or reducing the screen in the horizontal direction and the number of the numerator when an arbitrary magnification in the vertical direction of the screen expressed by a fraction is designated , A Y-direction denominator register for storing the number of denominators, and a second multiplexer for selecting and outputting any one of the Y-direction denominator register and the Y-direction denominator register A second register for storing a surplus value for an operation for enlarging or reducing the screen in the vertical direction, a surplus value of the second register, and a value output from the second multiplexer And a second adder that outputs a pulse in accordance with the sign of the remainder of the second register at the same time as storing the result in the second register. The constituting the second DDA involved in the process of enlargement or reduction of the direction, the first DDA 1
A read address counter that counts up by a pulse output from the adder of one row and instructs what digit data is to be read and processed for one row of image data to be subjected to enlargement or reduction processing, and a fixed cycle. A write address counter that counts up and writes the data to be written from the buffer to the line memory, in which digit of the line memory the address on the line memory is to be written, and the read timing and write of data related to enlargement or reduction processing Switching timing 3
And a second DDA constituting the second DDA.
And a third register for holding a pulse output from the adder and instructing whether or not to write data from the buffer to the line memory.

According to a second aspect of the present invention, there is provided a line memory control circuit according to the first aspect, wherein at least one line memory is controlled, and the line memory is controlled to perform enlargement or reduction processing on image data. The image processing apparatus includes an arithmetic unit that performs post-processing such as a spatial filter and halftone processing by pipeline control on output data from a line memory.

[0009]

FIG. 1 is a diagram illustrating the principle of the present invention. In the present invention, processing of coordinate transformation such as enlargement / reduction and processing of a spatial filter or the like are performed at one time. In FIG. 1, one line of image data of the input image 1 is sent to the line memory 4 one after another. The image data sent to the line memory 4 is expanded or reduced at an arbitrary magnification by the line memory control circuit 5 and developed on the line memory 4. The enlarged or reduced image data is immediately sent to a computing unit 3 that performs pipeline control, where a process such as a spatial filter is performed. Image-processed data is sequentially sent to the output image 2.

As described above, the enlargement / reduction processing and the processing such as the spatial filter are not regarded as separate processing but as a series of one processing. Can be realized. That is, without waiting for all image data to be enlarged or reduced, processing such as a spatial filter is performed one after another in the order in which the enlargement or reduction processing is completed. By doing so, the required memory only needs to have a capacity for one row instead of one screen, so that it is small.

[0011]

FIG. 2 is a diagram showing a configuration example of a line memory control circuit according to the present invention. In FIG. 2, input image data is sent to a buffer 7 via an image bus. This image data is enlarged or reduced by the line memory 6 and sent to the arithmetic unit 8. The arithmetic unit 8 performs a process such as a spatial filter and writes the result to an image memory. The data written in the image memory 9 is displayed as an output image.

The line memory control circuit 10 for controlling the line memory 6 includes a digital differential analyzer (Digital Differe).
The image data is enlarged or reduced using an arithmetic mechanism of an ntial analyzer (hereinafter referred to as DDA). Hereinafter, the expansion will be described as an example.

The DDA 11 is for enlarging an image in a horizontal direction (hereinafter referred to as an x direction). Line memory 6
Receives one line of image data, the DDA 11 calculates how many repetitions in the x direction of each digit of the one line will produce a predetermined enlargement ratio. For example, if it is desired to double the value in the x direction, the image data for one line sent is read one digit at a time from the beginning, and after reading one digit, this is output to the arithmetic unit 8 twice. At this time, the read address counter 1 indicates the digit address of the original data to be read.
5 The multiplexer 13 switches between the timing of reading data and the timing of writing data.

The DDA 12 is for enlarging an image in a vertical direction (hereinafter, referred to as a y direction). When the last digit of the image data for one line to be enlarged is enlarged, the image data is enlarged in the y direction in synchronization with the enlargement. Here, if the enlargement processing in the x direction is repeatedly performed without rewriting the data written in the line memory 6, the enlargement in the y direction can be performed. For example, if you want to double in the y direction,
The data written in the line memory 6 is repeated twice to enlarge and output. Note that the register 16 stores the DDA1
2 is held.

The two DDAs 11 and 12 have the same configuration, and the outputs of the multiplexers 19 and 24 and the register 2
Adders 20 and 25 add the contents of 1 and 26 and store the results in registers 21 and 26. At the same time, adder 20,
25 outputs an overflow pulse in accordance with the sign of the value stored in the registers 21 and 26. The pulse is D
The outputs of DAs 11 and 12 contribute to enlargement processing in the x and y directions. The enlargement ratio in the x direction is stored in the X direction numerator register 17 and the X direction denominator register 18. The enlargement ratio in the y direction is stored in the Y direction numerator register 22 and the Y direction numerator register.
It is stored in the direction denominator register 23. By expressing the enlargement ratio as a fraction, the image can be enlarged at an arbitrary magnification.

FIG. 3 is a flowchart showing the operation of the line memory control circuit. First, in S1, an enlargement ratio in the x direction and the y direction is set. As mentioned above,
Magnification represents a fraction, each register corresponding integer value is stored (hereinafter, N _X, using the M _X, N _Y, M Y shown in FIG. 3). At this time, two's complements of all the original numerical values are stored in N _X and N _Y. For example, in the case where the enlargement ratio in the x direction is 3/2 times and N _X and M _X are 4-bit registers, “1101B” which is the two's complement of “0011B” is stored in N _X. On the other hand, the M _X "0
010B "is stored. Adding the two's complement value subtracts the original number.

At S2, "0" is set in the remaining registers of the DDA (hereinafter, A _X and A _Y shown in FIG. 3 are used). If the comparison result in S3 is negative, the value of the read address counter remains unchanged, and if the result is not negative, the read address counter is incremented in S4,
The next image data is read by one digit. Then, S5 or S
6 is performed, and the process is repeated in S7. The exit from S7 is synchronized when the read address counter goes to the last address of the line memory and is cleared. The processing from S3 to S7 indicated by the letter A is an expansion processing in the x direction, and is processing related to the DDA 11 in FIG.

When the enlarging process for one line is completed, the alphabet B
The enlarging process in the y direction indicated by is performed. This corresponds to D in FIG.
This is processing related to DA12. The read address counter is cleared in S8, and the comparison is performed in S9. If the result of the comparison is negative, the contents of the line memory are not rewritten. If the result is not negative, one line of the next image data is read in S10.
Subsequently, the calculation in S11 or S12 is performed, and the process returns to S3 in S13. The process exits from S13 after the last line of the image data to be enlarged is processed.

FIG. 4 is a diagram for explaining a case where the enlargement ratio is 4/3. As shown in FIG. 4A, the read address is not necessarily increased because it is added by the output pulse from the DDA contributing to the expansion in the x direction. That is, the read address remains unchanged at times “0” and “4”. FIG. 4B illustrates the registers A _X ,
The calculation of N _X and M _X is shown. Here, since two complements are stored in N _X , each is given a negative sign. At times "0" and "4", the read address is not added because the calculation result is a negative value.

FIG. 5 is a diagram for explaining an image processing apparatus according to the present invention. The arithmetic unit 33 performs processing such as a spatial filter by pipeline control. The process of the spatial filter is a process for removing noise and sharpening the image for each unit area of the image. To remove noise in a 3 × 3 area,

(Equation 1) There is also something that sharpens the image,

(Equation 2) There is something like Data read from a plurality of rows of line memories is sent to the arithmetic unit 33 that performs such arithmetic processing, and this is processed as vector data in a Tokoroten manner by pipeline control. In FIG. 5, three line memories 27 to 29 are provided assuming a spatial filter process for a 3 × 3 area. The line memory control circuits 30 to 32 control the corresponding line memories 27 to 29 to perform enlargement or reduction processing at an arbitrary magnification.

[0021]

As described above, according to the present invention, enlargement or reduction processing is performed by a simple circuit operation, so that enlargement or reduction processing is speeded up. In addition, since the image processing is performed without interruption as one processing up to the processing of the spatial filter, the efficiency is very high. In addition, the use of the line memory enables the effective use of the memory, and the combination of the line memory and its control circuit has the advantage that an image processing apparatus having a high performance which has not been considered before can be configured. is there.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a line memory control circuit according to the present invention;

FIG. 3 is a diagram showing a flowchart relating to the operation of the line memory control circuit.

FIG. 4 is a diagram illustrating a case of an enlargement ratio of 4/3.

FIG. 5 is a diagram illustrating an image processing method according to the present invention.

FIG. 6 is a diagram illustrating a conventional technique.

[Explanation of symbols]

 1,34 input image 2,36 output image 3,8,33 arithmetic unit 4,6,27-29 line memory 5,10,30-32 line memory control circuit 7 buffer 9 image memory 11,12 DDA 13,19, 24 Multiplexer 14 Write address counter 15 Read address counter 16, 21, 26 Register 17 X direction numerator register 18 X direction denominator register 20, 25 Adder 22 Y direction numerator register 23 Y direction denominator register 35 Conversion image

Claims (2)

(57) [Claims] In an image processing apparatus, a control circuit for performing enlargement or reduction processing on image data transferred to a line memory (6) in units of rows, wherein the control circuit performs processing in a horizontal direction of a screen expressed by a fraction. When an arbitrary magnification of is specified,
X-direction numerator register (1
7), an X-direction denominator register (18) for storing the number of denominators, and a multiplexer for selecting and outputting the contents of one of the X-direction numerator register (17) and the X-direction denominator register (18) (19), a register (21) for storing a surplus value for an arithmetic process for enlarging or reducing the screen in the horizontal direction, a surplus value of the register (21), and an output from the multiplexer (19). And an adder (20) for storing the result in the register (21) and simultaneously outputting a pulse in accordance with the sign of the remainder of the register (21). When the DDA (11) involved in the process of enlarging or reducing the image and an arbitrary magnification in the vertical direction of the screen expressed by a fraction are designated, a Y-direction numerator for storing the number of the molecule is used. (22), a Y-direction denominator register (23) for storing the number of denominators, and the contents of one of the Y-direction numerator register (22) and the Y-direction denominator register (23) are selected and output. A multiplexer (24) and a register (26) for storing a surplus value for arithmetic processing for enlarging or reducing the screen in the vertical direction.
And the value of the remainder of the register (26) is added to the value output from the multiplexer (24), and the result is stored in the register (26). An adder (25) for outputting a pulse in accordance with the sign of the value; a DDA (12) involved in the process of enlarging or reducing the screen in the vertical direction; and an adder (20) constituting the DDA (11) ), A read address counter (15) for instructing which digit data is to be read out and processed with respect to one line of image data to be subjected to enlargement or reduction processing, which is counted up by a pulse output from And write data indicating the number of the digit of the line memory (6) to write the data input from the buffer (7) to the line memory (6). And less counter (14), to switch the read timing and write timing of the data according to the enlargement or reduction processing multiplexers (1
3) and an adder (25) constituting the DDA (12)
A line memory control circuit, comprising: a register (16) for holding a pulse output from the memory and instructing output of image data to be written from the buffer (7) to the line memory (6). 2. The line memory control circuit according to claim 1, wherein at least one line memory is controlled, and the line memory is controlled to perform enlargement or reduction processing on the image data. On the other hand, an image processing apparatus comprising: an arithmetic unit that performs post-processing such as a spatial filter and halftoning by pipeline control.