JPH0668760B2 - DMA controller for image editing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to an image editing apparatus for digitally synthesizing, cutting out, rotating, enlarging / reducing images, etc., and speeding up the transfer of memory data with a simple configuration. For image editing equipment
Regarding the A controller.

[Conventional technology]

As a conventional DMA controller for an image editing apparatus, there is, for example, one announced in "Document Image Processing Method in Document Management System" at the 23rd National Convention of Information Processing Society (late 1981). FIG. 9 shows this DMA controller. The control circuit 1 determines the operation of the DMA controller according to a command from a host CPU (not shown) and controls each unit, and the address for setting each address of the transfer source and the transfer destination. A data interval register 33 for setting the counters 31 and 32 and each data interval between the transfer source and the transfer destination (address interval from the address of the last word of one line of the data cutout area to the address of the first word of the next line) 34, an arithmetic unit (ALU) 37 for calculating the address of the transfer source, an ALU 38 for calculating the address of the transfer destination, multiplexers 35, 36 for setting addresses to the address counters 31, 32, and the number of transfer words. Word registers 11 and 13 to be set, and the word register
Word counters 12 and 14 that load the number of words set in 11 and 13 and count down, a memory address register 9 (MAR) that loads the contents of the address counter 31 or the address counter 32, a command from the host CPU, It has a control data bus 15 used for setting an address, a count value and the like to the DMA controller, an address bus 16 for outputting the address of the MAR 9 to an image memory, and an image memory 17.

In the above configuration, the transfer source memory 17a in FIG.
The (N ₁ × M ₁ ) rectangular area (W × H) is cut out and
The operation will be described by taking as an example the case of transferring to the transfer destination memory 17b (N ₂ × M ₂ ) in FIG.

First, the following six parameters are designated as initial values.

a) the source start address _{(S 1: 3N + 2)} b) the source data interval _{(I 1 = N 1 -W)} c) destination start address _{(S 2: 5N + 5)} d) the source data interval _(I 2 = N _2- W) e) Number of horizontal words in rectangular area (W) f) Number of vertical words in rectangular area (H) Parameter is set by the following procedure. The transfer source start address S ₁ (3N + 2) is set in the address counter 31 via the multiplexer 35, and the transfer destination start address S ₂ (5N + 5) is set in the address counter 32 via the multiplexer 36. The transfer source data interval I ₁ is set in the data interval register 33, and the transfer destination data interval I ₂ is set in the data interval register 34. Further, the cutout width W of the image is set in the word register 11, and the number H of lines in the vertical direction of the image is set in the word register 13.

Next, the CPU sends a command code designating the transfer mode to the control circuit 1. Control circuit 1 that received the command code
Starts a DMA transfer. The procedure is as follows. First, the content W (cutout width) of the word register 11 is loaded into the word counter 12, and the content H (vertical line number) of the word register 13 is loaded into the word counter 14. The content (3N + 2) of the address counter 31 is loaded into the MAR 9, and the memory 17a is read, and at the same time, the address counter 31 (3
Add +1 to N + 2).

The read data is temporarily recorded in a data register (not shown). Further, the content W of the word counter 12 is decremented by one. Next, the content (5N + 5) of the address counter 32 is loaded into the MAR 9, the content of the memory register is written to the memory 17a, and at the same time, the address counter 32 (5N + 5) is incremented by one. Further, it is judged whether the output of the word counter 12 is 0 or not. If it is not 0, the content (3N + 3) of the address counter 31 is loaded into the MAR 9 again and the operation is repeated. If the content of the word counter 12 is 0, in other words, if the transfer of one line is completed, the content H of the word counter 14 is decremented by -1. Here, it is determined whether or not the content of the word counter 14 is 0, and whether or not the transfer of all lines is completed. If not 0, the contents of the address counter 31 in the ALU 37 (3 when the transfer of the first line is completed)
The content (I ₁ ) of the data interval register 33 is added to (N + 5) and set in the address counter 31 via the multiplexer 35. At the same time, the contents (I ₂ ) of the data interval register 34 are added to the contents of the address counter 32 (5N + 8 at this point) in the ALU 38, and the contents are set in the address counter 32 via the multiplexer 36.

By this calculation, the start addresses of the lines next to the transfer source and transfer destination rectangular areas are set in the address counter 31 and the address counter 32, respectively. Address counter is set again when the start address of the next line is set
MAR of 31 (4N + 2 at this runner-up)
Load 9 and repeat the same operation. When the word counter 14 becomes 0 by repeating this operation, in other words, when the processing of all lines is completed, the transfer operation is ended.

Since this DMA controller is provided with the data interval register, not only horizontal access but also vertical access or a combination of both access is possible.
The speed of memory access can be increased as compared with the method of performing memory access by the CPU.

[Problems to be solved by the invention]

However, according to the conventional DMA controller for an image editing apparatus, since the address calculation of the transfer source and the transfer destination is performed by a separate circuit, the hardware configuration is complicated, and the data interval is changed every time the size of the cutout area changes. Since it changes, there is the inconvenience that the value must be set. Further, since the horizontal address calculation is performed by the counter, if a count-up counter is used for this counter, access cannot be performed in the direction in which the address decreases, and
The use of the countdown counter has a disadvantage that access cannot be performed in the direction of increasing addresses. Further, since data is transferred line by line, there is a drawback that there is a limit in shortening image editing time such as enlargement / reduction.

[Means for solving problems]

The present invention has been made in view of the above, and is provided next to the first storage unit that stores the number of words in one direction of the transfer source and transfer destination image memories, the transfer source of image data, and the transfer line of the transfer destination. First register for holding the start address of the transfer line, a second register for holding the transfer address of the transfer source and the transfer destination of the image data to be transferred, and the number of words in one direction for the start address of the transfer line. First arithmetic means for obtaining the start address of the next transfer line by addition or subtraction and holding it in the first register, and 1 for the transfer address of the transfer source and transfer destination of the image data being transferred.
Is added or subtracted to obtain a transfer address to be transferred next, and a calculation means for performing a second calculation to hold the transfer address in the second register; and a transfer source of the transfer source based on the transfer address held in the second register The present invention provides a DMA controller for an image editing apparatus, which includes an image memory and a control means for accessing the image memory of the transfer destination.

Further, the present invention provides a DMA controller capable of simultaneously performing high-speed DMA transfer of a plurality of lines in order to shorten the enlargement / reduction time by providing enlargement / reduction circuits in parallel and performing parallel processing.

The DMA controller for the image editing apparatus of the present invention will be described below.

〔Example〕

FIG. 1 shows a first embodiment of the present invention. In this embodiment, the control circuit 1 for controlling the operation of the DMA controller by controlling the operation of the DMA controller by a command from the host CPU (not shown) and the width on the image memory (corresponding to N in FIG. 2A) are set. MAP register to be set (Memory Address Pi
tch register) 2, ALU 10 for calculating source and destination addresses, zero driver 3 for inputting zero to the ALU 10, address registers 5-8 for setting an address described later, and the address A gate 4 for setting address information from the CPU in the registers 5-8, a memory address register (MAR) 9 for loading any of the information in the address registers 5-8 to the address bus 16, and a cutout area. Word register 11 for setting the number of horizontal and vertical transfer words of
13, the word register 11 and the word counters 12 and 14 for loading the values set in the word register 13 to perform subtraction counting and outputting to the control circuit whether or not the count value becomes 0, and from the host CPU It has a control data bus 15 (which may be common with a normal data bus) used when setting a command, an address, a count value, etc. in the DMA controller, and an image memory 17. The above-mentioned operation of the ALU 10 performs operations such as clear, B + A, B-A, etc. by instructions. That is, the lowest order calculation is possible by controlling the A input and the carry input. Clear, -1, -MAP, +0, +
MAP and +1 can be all performed in the same cycle, which enables all access methods necessary for image editing. An address can be input to the B port of the ALU 10 from any of the gate 4 and the address registers 5-8. The output of ALU 10 is loaded into any of address registers 5-8.

With the above configuration, according to the flowchart of FIG.
The operation will be described by taking as an example the case where an image is cut out and transferred to another memory area. The cutout of the rectangular area in FIG. 2A is taken as an example. First, the start address of the transfer source is loaded into the address register 5, and the start address of the transfer destination is loaded into the address counter 7. In this case, the data flow passes from the data bus 15 through the gate 4 and is subjected to +0 operation by the ALU 10 and input to the address registers 5 and 7. In the example of FIG. 2, 2N + 2 is stored in the address register 5 and 10N + 5 (transfer destination start address) is stored in the address register 7. Next, the cut-out width of the image (4 in FIG. 2A) is stored in the word register 11 and the number of lines in the vertical direction of the image (see FIG. 2).
In (a), 5) is set in the word register 13. Next CP
U sends a command code designating the transfer mode to the control circuit 1 of the DMA controller. The control circuit 1 receiving the command code starts the DMA transfer.

First, the content (5) of the word register 13 is loaded into the word counter 14, and the content (4) of the word register 11 is loaded into the word counter 12. Transfer the start address 2N + 2 from the address register 5 to the address register 6,
The address register 5 and MAP are calculated by the ALU 10 (here, 2N + 2 and N), and the head address 3N + of the next line is calculated.
2 is set in the address register 5. The start address 10N + 5 of the transfer destination is transferred from the address register 7 to the address register 8, the address register 7 and MAP (here, 10N + 5 and N) are calculated by the ALU 10, and the start address 11N + 5 of the next line of the transfer destination is set to the address register 7
Set to. Next, the contents of the address register 6 are MAR
9, the memory is read, and the data is temporarily recorded in a data register (not shown). At the same time, the contents of the address register 6 are incremented by 1 by the ALU 10 and set in the address register 6. At this point, the content of address register 6 is 2N
It becomes +3, which means that the next address is set.
Further, the content of the word counter 12 is set to -1. Next, the contents of the address register 8 are loaded into the MAR 9, the contents of the data register are written to the memory, and at the same time, the contents of the address register 8 are incremented by 1 by the ALU 10 and set in the address register 8. At this time, the content of the address register 8 becomes 10N + 6, and the address of the next transfer destination is set. Here, it is determined whether the output of the word counter 12 is 0 or not. If it is 0, it means that the transfer has been performed for the number of horizontal words in the rectangular area (4 in FIG. 2A), so the transfer of one line is completed. On the other hand, if it is not 0, since the transfer of one line is not completed, the content (2N + 3) of the address register 6 is loaded into the MAR 9, the memory is read, the data is temporarily recorded in the data register, and the operation is repeated. When the output of the word counter 12 becomes 0 and the transfer of one line is completed, the content of the word counter 14 is decremented by 1 and the output becomes 0.
Determine whether or not. If it is 0, it means that the number of vertical lines in the rectangular area (5 in FIG. 2A) has been transferred, and the operation ends. On the other hand, if it is not 0, the contents of the word register 11 are loaded into the word counter 12, the contents 3N + 2 of the address register 5 are copied to the address register 6, and the operation is repeated.

As described above, in the present embodiment, all address calculation is AL
I am going to U10. Further, in the present embodiment, the access is used when the address is increased. However, when the address is decreased, the setting of the start address is changed and the ALU 10 can be subtracted by -1. Furthermore, by providing two MAP registers, transfer between image memories having different widths (N) is naturally possible.

FIG. 4 shows a second embodiment of the present invention, which has a RAM 18 for setting the addresses of a plurality of lines to be transferred, a latch circuit 19 for latching the output of the RAM 18, and a counter 20 for generating the address of the RAM 18. The counter 20 can be cleared and counted up. The other configurations are similar to those in FIG. 1 and will not be described.

In the above configuration, the operation of the ALU 10 can be designated as clear, B + A, BA, etc. by an instruction. That is, by controlling A input and carry input,
Clear, -1, -MAP, +0, + MAP,
+1 can be calculated. All of these can be performed in the same cycle, and all the address operations necessary for image editing can be performed. The contents of any of the address register 5, the address register 6 and the RAM 18 can be input to the B port of the ALU 10. The output of the ALU 10 can be output to any of the address register 5, the address register 6 and the RAM 18. Further, the RAM 18 is accessed at the address indicated by the counter 20. The RAM 18 has the number of words equal to or larger than the number of parallel lines to be scaled. Assuming that the enlargement / reduction circuit has a configuration capable of parallel processing of 16 lines, the RAM 18 has a capacity of 16 words, and the counter 20 is a 4-bit counter (countable from 0 to 15).

The latch circuit 19 is normally transparent,
It is assumed that the data is latched only when the data is written in the RAM 18. This is to prevent the original data from changing when the address of the data in the RAM 18 is calculated and the data is written in the RAM 18 again.

In the above configuration, the operation will be described by taking as an example the case where the image data in the rectangular area is thinned out and DMA-transferred to the scaling circuit. First, the counter 20 is cleared and the start address of the original image is loaded from the CPU into the address register 5 of the DMA controller. The data flow is passed from the data bus 15 through the gate 4 to the ALU 10 to be operated by +0 and input to the address register 5. Next, the CPU determines from the reduction ratio whether or not to thin the line, and if it is not thinned, the contents of A5 are copied to the RAM 18. Here, the counter 20 is incremented by +1. Next, the contents of MAP2 are added to the contents of address register 5 and loaded into address register 5 (here, the start address of the next line is stored in address register 5). Then, it is determined whether or not to thin this line (address indicated by the A address register). When thinning out, the contents of the address register 5 are not copied to the RAM 18, but the contents of the MAP 2 are added to the contents of the address register 5 and loaded into the address register 5. This procedure is repeated until the counter 20 reaches 0. FIG. 5 (a) shows 2N + 2, 3 which is the target of reduction processing.
N + 2 ... line is shown, and it is thinned to 16 lines by receiving the processing according to the flowchart of FIG.
It is copied to the RAM 18 in (b). Counter 20 at this point
Is 0. On the other hand, the number of words beside the image to be reduced is stored in the word register 13, and the number of words in the RAM 18 is stored in the word register.
Load to 11. When the setting of each control parameter is completed, the CPU sends a command code designating the transfer mode to the control circuit of the DMA controller. The control circuit 1 receiving the command code starts the DMA transfer. The procedure is as follows (see the flow in FIG. 7).

First, the contents of word register 13 are
14 and loads the contents of the word register 11 into the word counter 12. Next, the counter 20 is cleared. If you are ready to do so, whether DMA transfer is possible, 21
16 parallel scaling circuits 21 of ₀ , 21 ₁ , ... 21 ₁₅ (Fig. 5
Check whether (B)) is ready for input. Wait if not possible. First, R of line 0 indicated by counter 20
At the same time as loading the contents of AM18 into MAR9,
At 10, the contents of RAM 18 are incremented by 1 and set in RAM 18. The contents of the memory at the address indicated by MAR9 are loaded into the parallel scaling circuit, and the word counter 12 is decremented by -1.
To do. Then, the counter 20 is incremented by 1 to determine whether the content of the word counter 12 is 0 or not. RAM if not 0
Since the transfer of 18 words (16 words in this embodiment) has not been completed, the contents of the RAM 18 indicated by the counter 20 are loaded into the MAR 9 again, and the above operation is repeated. 0
In this case, since all 16 head addresses set in the RAM 18 have been transferred, the transfer of one vertical line is completed. Here, the word counter 14 is decremented by 1 and it is determined whether the output of the word counter 14 is 0 or not. If not 0, load the contents of word register 11 to word counter 12,
The counter 20 is cleared and the above operation is repeated. If the word counter 14 is 0, it means that the column transfer has been performed by the number of horizontal words of the rectangular area to be transferred, and thus the DMA transfer of the number of lines that can be processed in parallel is completed. CPU
If the processing of all rectangular areas is not completed at the time when the end of DMA is detected, the head address of the transfer line may be obtained again and the DMA controller may be driven.

In the present embodiment, only the reduction of the image editing has been described, but in the case of other editing, for example, clipping movement, rotation, enlargement, filtering of image processing, interpolation, etc., when several lines of simultaneous data are required at the same time, etc. It can also be used for. Also, depending on the transfer method, the address register,
It can be optimized by increasing or decreasing the number of transfer word registers, counters and the like.

FIG. 8 shows a third embodiment of the present invention, and the common parts are indicated by common reference numerals, and thus duplicated description will be omitted, but the first embodiment and the second embodiment will be omitted. They are merged, and horizontal access, vertical access, and a combination of both are possible.

〔The invention's effect〕

As described above, according to the DMA controller for the image editing apparatus of the present invention, the first register for holding the start address of the line next to the line being transferred and the second register for holding the address being transferred are provided. Therefore, all address calculations can be performed in one ALU in a short time, the hardware configuration can be simplified, and the data setting in the transfer operation can be facilitated.

Further, by providing the scaling circuits in parallel and performing parallel processing, a plurality of lines can be simultaneously subjected to high-speed DMA transfer, and the scaling time can be shortened.

[Brief description of drawings]

1 to 3 show a first embodiment of the present invention.
FIG. 1 is a block diagram, FIGS. 2 (a) and 2 (b) are explanatory views of a memory, FIG. 3 is a control flowchart, and FIGS. 4 to 7 show a second embodiment of the present invention. Figure 4 is a block diagram, 5
FIGS. 6A and 6B are explanatory views of a memory, FIGS. 6 and 7 are control flowcharts, and FIG. 8 is an explanatory view showing a third embodiment of the present invention. 9 and 10 (a) and (b) show a conventional DMA controller for an image editing apparatus, FIG. 9 is a block diagram, and FIGS. 10 (a) and 10 (b) are explanatory views of a memory. Explanation of code 1 ... Control circuit, 2 ... MAP register, 3 ... Zero driver, 4 ... Gate, 5 ... Address register (A5), 6 ... Address register (A6), 7 ... Address register (A7), 8 ... Address register (A8) 9 Memory address register (MAR) 10 ALU 11 Word register (WDREG11) 12 Word counter (WDCNT12) 13 Word register (WDREG13) 14 Word counter (WDCNT14 ) 15 …… control data bus 16 …… address bus 17 …… image memory (IMM) 18 …… RAM, 19 …… latch (LATCH) 20 …… counter 31 …… address counter (A31) 32 …… address counter ( A32) 33 …… Data interval register (I33) 34 …… Data interval register (I34) 35 …… Multiplexer, 36 …… Multiplexer 37 …… ALU, 38 …… A U

Claims (2)

[Claims] 1. A DMA controller that edits or processes image data in a specified area of a transfer source image memory and transfers the image data to a specified area of a transfer destination image memory, wherein the transfer source and transfer destination images A first storage means (2) for storing the number of words in one direction of the memory, and a first register (5) for holding a start address of a transfer line next to a transfer line of a transfer source and a transfer destination of image data. , (7), second registers (6) and (8) for holding the transfer addresses of the transfer source and transfer destination of the image data to be transferred, and the number of words in one direction in the start address of the transfer line. The first address (5) of the first register (5) is obtained by obtaining the start address of the next transfer line by adding or subtracting.
The first operation held in (7) and addition or subtraction of 1 to and from the transfer addresses of the transfer source and transfer destination of the image data being transferred are used to obtain the transfer address to be transferred next and the second operation is performed. Second to be held in registers (6) and (8)
And a control for accessing the transfer source image memory and the transfer destination image memory based on the transfer address held in the second registers (6) and (8). A DMA controller for an image editing apparatus, which is provided with means (1). 2. A DMA controller in an image edit processing apparatus capable of parallel processing of a plurality of data, wherein a first number of words stored in one direction of an image memory of a transfer source is stored.
Storage means (2), a first register (5) for holding the start address of the transfer line next to the transfer line of the transfer source of the image data, and a plurality of sequentially stored in the first register (5) Second storage means (18) for sequentially storing a plurality of addresses for image editing processing obtained by processing the start address of the transfer address, and the start address of the transfer line held in the first register (5). A first operation for obtaining the start address of the next transfer line by adding or subtracting the number of words in one direction stored in the first storage means (2) and holding it in the first register (5) And a plurality of start addresses stored in the second storage means (18) are sequentially added or subtracted by 1 according to the progress of the image editing process to obtain a plurality of operation results for the image editing process. As The arithmetic means (10) for performing the second arithmetic operation to be stored in the second storage means (18), and the transfer based on the image editing processing address stored in the second storage means (18). A DMA controller for an image editing apparatus, comprising: a control unit (1) for accessing an original memory and causing an image editing processing unit to execute an editing process on an image in the memory.