JP2855973B2 - MOS type thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor using polycrystalline silicon.

[0002]

2. Description of the Related Art Since a polycrystalline silicon thin film transistor can be formed on an insulator, a high-speed static
It is used as a load element of a memory integrated circuit, or is arranged for each display unit called a pixel in a liquid crystal display element and used as a liquid crystal drive transistor or the like.

FIG. 4 is a sectional view of a device structure of a general thin film transistor called a bottom gate type . A gate electrode 203 of polycrystalline silicon is arranged on base insulating film 201. After depositing a polycrystalline silicon layer 206 on the top via a gate oxide film 205, a high concentration source / drain region 208 doped with a carrier impurity at a high concentration
Is formed. Further, as a cover film 209, a silicon oxide film is deposited on the upper portion, and an opening is formed in a portion of the source / drain high concentration region 208 to form an aluminum electrode 210.
Is formed. In the structure formed in this way,
The movement of carriers between the source region and the drain region is controlled by an electric field from the gate electrode 203, and the device operates as a MOS transistor.

However, a thin film transistor using polycrystalline silicon has a larger leak current than a MOS type transistor formed using a silicon substrate crystal, and a characteristic structural device is devised.

This is because, as shown in FIG. 4 , an offset region 222 is formed between the source / drain high-concentration region 208 and the end of the gate electrode 203.
Since thin film transistors use polycrystalline silicon, they contain many crystal defects such as crystal grain boundaries, and the effect of the electric field has an effect on the leakage current generation mechanism. It can be inferred from conduction behavior.

Actually, it has been known from experience that providing such an offset region is effective in reducing the leak current.

[0007]

A problem in the manufacturing technique for forming the offset region is that the source / drain high-concentration region is formed in alignment with the underlying gate electrode pattern. Error may be unavoidable.

In a general MOS transistor formed using a silicon substrate crystal, a carrier impurity can be doped by ion implantation using a gate electrode disposed above the substrate as a mass. Therefore, the source / drain regions can be formed in a self-aligned manner with respect to the gate electrode pattern. This is one of the factors that can integrate transistor elements with little variation in characteristics at an extremely high density, and there is a demand for the formation of self-aligned source / drain regions also in thin film transistors.

In addition, with the miniaturization of device dimensions, gate dimensions on the submicron level have been required with high precision.

[0010]

According to the present invention, in order to solve the above-mentioned problems of the prior art, the surface of a base insulating film is
In the bottom gate type thin film transistor provided
A first insulating film and a gate on the surface of the base insulating film;
It has a laminated structure consisting of electrodes and a second insulating film.
Between the upper and side surfaces of the laminated structure and the underlying insulating film.
On the surface has a silicon layer that will be the active area,
A part covering the upper surface and a part of the side surface of the second insulating film;
The silicon layer and a part of the side surface of the first insulating film and
And the silicon that covers a part of the top surface of the base insulating film.
Source and drain regions are provided in the
The gate length is controlled by the thickness of the gate electrode, and the first
The above saw provided below the gate electrode with the thickness of the insulating film
Offset between the drain / drain region and the gate electrode.
The gate width is controlled by controlling the width of the gate region by the thickness of the second insulating film.
The source / drain regions above the electrodes
It is characterized and this <br/> to control the width of the offset region between the gate electrode of.

This is because, in a commonly used semiconductor structure process, misalignment of about several hundred nm is unavoidable in alignment exposure, whereas the film thickness in forming a polycrystalline silicon, an oxide film or the like is increased. Focuses on the fact that control is possible at about a few nanometers, and proposes a new device structure that can utilize this.

[0012]

Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1, which is a cross-sectional view in the order of steps for explaining a method of manufacturing a MOS thin film transistor,
The MOS thin film transistor according to the first embodiment of the present invention
It is formed as follows. First, a 0.3 μm-thick CVD silicon oxide film 102 and a 0.4 μm-thick polycrystalline silicon layer 103 are sequentially deposited on a base insulating film 101. Thereafter, impurity doping is performed on the polycrystalline silicon layer 103 by a phosphorus diffusion method to remove an oxide film on the surface. The thickness of this polycrystalline silicon layer 103 corresponds to the gate length of the normal structure. On this polycrystalline silicon layer 103, a CVD silicon oxide film 104 having a thickness of 0.35 μm is formed.
Is deposited. Next, by applying a lithography technique and a dry etching technique using a photo-resist (not shown), performs shape processing, CVD silicon oxide film 104 on the top, has a CVD silicon oxide film 102 on the lower portion As a result, a laminated structure including the polycrystalline silicon layer 103 is formed in the intermediate layer. A 150 nm-thick CVD silicon oxide film 105 is formed on the periphery including the upper surface and side surfaces of the laminated structure [FIG. 1 (a)].

Next, the entire surface is etched using a highly anisotropic dry etching to form a gate oxide film of the thin film transistor while leaving the CVD silicon oxide film 105 only on the side wall portion of the laminated structure. The polycrystalline silicon layer 106 serving as a layer is formed to a thickness of 150 nm.
It is deposited (FIG. 1B).

Next, the photoresist 107 is patterned to form an opening in a region where a MOS thin film transistor is to be formed. An acceleration voltage of 50 Ke is applied to this opening.
Arsenic is implanted with V to form an n-type ion implantation region 108. The dose is set so that the concentration of arsenic in the implanted portion is about 20 power per cubic centimeter.
If the flow of the implanted ions is kept perpendicular to the substrate surface, the polycrystalline silicon layer 106 formed on the side wall is not doped because the incident angle becomes parallel. If these conditions cannot be satisfied in terms of the apparatus, a CVD silicon oxide film can be disposed in order to supplement the side wall. The method may be performed in the same manner as in the formation of the gate oxide film described above (FIG. 1C).

Next, after the photo resist 107 is removed, annealing is performed at 900 ° C. for about 20 minutes to activate the polycrystalline silicon layer 106 in the ion-implanted region to make n.
A source / drain high concentration region 108a of the channel is formed. At this time, the source / drain high concentration region 108a
Is wider than the ion-implanted layer 108, so that the oxide films 102, 1 having a stacked structure that determines the offset amount of the thin film transistor
It is necessary to allow for this as the film thickness of 04.

Finally, after depositing a 0.4 μm thick CVD silicon oxide film 109 as a cover film,
An opening is formed in the high-concentration drain region 108a to provide an aluminum electrode 110. These electrodes 110 correspond to source and drain terminals when two transistors having a common gate electrode are connected in series [FIG.
(D)].

When the characteristics of the n-channel thin-film transistor of the first embodiment are measured in comparison with those of the conventional structure, the leakage current of the conventional structure is found to be an average of 84 in the wafer surface per 1 μm of gate width. In this example, the characteristics were improved to 3.4 pA and the variation was about 18%, whereas in the case of this example, the variation was about 0.17 pA and the variation was about 3%.

Referring to FIG. 2, which is a cross-sectional view in the order of steps for explaining a method of manufacturing a MOS thin film transistor,
The MOS thin film transistor according to the second embodiment of the present invention
After performing the same manufacturing steps as in the first embodiment up to the CVD silicon oxide film 109 (see FIG. 1D), CV is applied to the high-concentration region 108a formed on the upper part of the laminated structure.
Opening the D silicon oxide film 109 (FIG. 2A),
Further, an aluminum electrode 110 is arranged [FIG. 2 (b)].

In the second embodiment, thin film transistors connected in parallel are formed. The structure of the present embodiment has an advantage that a transistor having a smaller total area and a longer total gate width can be formed than the conventional structure.

In a third embodiment of the present invention, the present invention
This is applied to an S transistor. In the case of a CMOS configuration, it is necessary to make both n-channel and p-channel thin film transistors. In order to operate at the same gate potential, the polycrystalline silicon layer in the channel region is lightly doped, It is necessary to make the threshold values of the channel transistors uniform.

Referring to FIG. 3 for explaining a method of manufacturing a CMOS transistor including a thin film transistor,
In the third embodiment, first, similarly to the first embodiment, after forming the polycrystalline silicon layer 106 (see FIG. 1B), only the portion where the n-channel thin film transistor is to be formed is an opening. The pattern of the photo resist 117a thus formed is formed. Next, boron ions are implanted for controlling the threshold value, so that the polycrystalline silicon layer 106 becomes a polycrystalline silicon layer 106a. At this time, it is effective that the flow of the implanted ions is inclined at a large angle from perpendicular to the substrate surface. Further, the n-type ion implantation region 108
In order to form GaAs, arsenic ion implantation is performed at an angle perpendicular to the substrate surface (FIG. 3A).

Next, the photoresist 117a is removed.
A photoresist 117b having only a region where a p-channel thin film transistor is to be formed is opened in a complementary manner, and channel doping is performed by phosphorus ion implantation for controlling a threshold value. 106b. Further, in order to form a p-type ion implantation region 118, fluorinated boron is implanted into the ion perpendicular to the substrate [FIG. 3 (b)].

Next, the photoresist 117b is removed, and the CVD silicon oxide film 11 having a total thickness of 0.2 μm is removed.
9 is formed, and an opening is formed near the upper portion of the gate / insulating film laminated structure. After that, a titanium layer 1 having a thickness of 0.1 μm was formed.
20 is deposited by sputtering and annealed. Thereby, the n-type and p-type ion implantation regions 108 and 118 are formed.
Are n-channel and p-channel high-concentration source / drain regions 108a and 118a, respectively. At the same time, only the high-concentration regions 108a and 118a at the openings of the oxide film are used as the silicide layers 121 (FIG. 3C).

The unreacted titanium layer 120 and CV in other regions
After the D silicon oxide film 119 is removed, a 0.4 μm thick CVD oxide film 109 is formed as a cover film as a whole, and an opening is formed to establish electrical conduction with the aluminum electrode 110 [FIG. (D)].

The third embodiment has an advantage that a CMOS transistor can be formed in close proximity.

[0027]

As described above, according to the present invention, since the length of the offset region of the MOS thin film transistor is determined by the thickness of the insulating film laminated on the gate electrode, the leakage current of the MOS thin film transistor is reduced. Becomes easier. Also, control of the gate length is facilitated.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view in a process order for explaining a first embodiment of the present invention along a manufacturing method.

FIG. 2 is a cross-sectional view in the order of steps for explaining a second embodiment of the present invention along a manufacturing method.

FIG. 3 is a cross-sectional view in a process order for explaining a third embodiment of the present invention along a manufacturing method.

FIG. 4 is a cross-sectional view for explaining a conventional MOS thin film transistor.

[Explanation of symbols]

101, 201 Base insulating film 102, 104, 105, 109, 119 CVD silicon oxide film 103, 106, 106a, 106b Polycrystalline silicon layer 107, 117a, 117b Photo resist 108, 118 Ion implanted region 108a, 118a, 208 Source・ Drain high concentration region 110,210 Aluminum electrode 120 Titanium layer 121 Silicide layer 203 Gate electrode 205 Gate oxide film 209 Cover film 222 Offset region

Claims (1)

(57) [Claims] 1. A bottom provided on a surface of a base insulating film.
A gate type thin film transistor, wherein a first insulating film and a gate electrode are provided on a surface of the base insulating film;
And a second insulating film, and a top surface and side surfaces of the stacked structure and a surface of the base insulating film.
The upper portion has a silicon layer serving as an active region, and has a portion covering a part of the upper surface and a part of the side surface of the second insulating film.
A part of a side surface of the silicon layer and the first insulating film;
And a portion of the silicon covering a part of the upper surface of the base insulating film.
Each of the layers has a source / drain region , and a gate length is controlled by a film thickness of the gate electrode .
The above-mentioned source provided below the gate electrode with the thickness of the insulating film.
Offset between the source / drain region and the gate electrode
The width of the region is controlled, and the thickness of the gate is determined by the thickness of the second insulating film.
The source / drain region provided above the electrode;
A MOS thin film transistor, wherein a width of an offset region between the gate electrode and the gate electrode is controlled .