JP2856716B2 - Multiple selection detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to Tranlatio.
n Look-aside Buffer (hereinafter TL)
B), and more particularly to a multiple selection detection circuit used in an address conversion circuit requiring high-speed operation.

[0002]

2. Description of the Related Art A memory management unit mounted on a microprocessor allocates a large virtual address by address conversion to provide a logically expanded memory space. The TLB used for this address conversion expands the address space of the microprocessor by converting addresses in the virtual memory space into physical addresses.

Referring to FIG. 4 which shows a block diagram of a basic structure of a conventional TLB, an address space and a virtual page number in a virtual address 402 sent from a processor are used for address conversion. TLB
The address space and the virtual page number of the virtual address of the entry 404 are compared with each other, and when the virtual page number and the address space of this virtual address match, the TLB4
03 is a hit, and reads the page frame number of the physical address from the TLB 403.

The lower bits of the address in the virtual address 402 sent from the processor become the physical address 405 together with the page frame number of the address read from the TLB 403 without passing through the TLB 403.

Here, if the TLB hits are multiplexed in the virtual page number and address space in the TLB entry 404, the page frame numbers of the physical addresses to be read overlap, so the TLB hits must be read before the page frame number is read. Is TLB entry 40
4 is detected using a detection circuit, and the present invention relates to a circuit configuration for detecting a plurality of addresses.

Referring to FIG. 5, which shows a circuit configuration diagram of a conventional multiple selection detection circuit for addresses, this multiple selection detection circuit has a two-input NOR (hereinafter referred to as 2NO) input signal IN1.
R) and one input terminal of 29 and AND-NOR2
8 is supplied to one input terminal on the AND side. AND-N
The NOR-side input terminal of the OR circuit 28, the other input terminal on the AND side, and the other input terminal of the 2NOR 29 are grounded. The output terminal of AND-NOR 28 is OR-NAND 30
Of the OR-NAND 30
One input terminal on the R side has an output terminal of 2NOR 29, and the other input terminal on the OR side has an input signal I via an inverter 31.
N2 is supplied. Inverters 31 and 2 NOR29
Are further connected to two input terminals of a two-input NAND (hereinafter, referred to as 2NAND) 32, respectively.

The output terminal of the OR-NAND 30 is AND-N
Connected to the NOR-side input terminal of OR33, AND-NOR
The output terminal of the 2NAND 32 is connected to one input terminal on the AND side of 33, and the input signal IN3 is supplied to the other input terminal. The output terminals of the input signals IN3 and 2NAND32 are further connected to the two input terminals of 2NOR34, respectively.

The output terminal of the AND-NOR 33 is OR-NA
Connected to the NAND-side input terminal of ND35, OR-NAN
The output terminal of 2NOR 34 is connected to one input terminal on the OR side of D 35, and the input signal IN 4 is supplied to the other input terminal via the inverter 36. The output terminals of the inverters 36 and 2NOR34 are further connected to the two input terminals of the 2NAND 37, respectively.

The output terminal of the OR-NAND 35 is AND-N
Connected to the NOR-side input terminal of OR38, AND-NOR
The output terminal of the 2NAND 37 is connected to one input terminal on the AND side of 35, and the input signal IN5 is supplied to the other input terminal. The output terminals of the input signal IN5 and the 2NAND 37 are further connected to the 2 input terminals of the 2NOR 39, respectively.

The output terminal of the AND-NOR 38 is OR-NA.
Connected to NAND side input terminal of ND40, OR-NAN
The output terminal of 2NOR39 is connected to one input terminal on the OR side of D40, and the input signal IN6 is supplied to the other input terminal via the inverter 41. The output terminals of the inverters 41 and 2NOR39 are further connected to the two input terminals of the 2NAND 42, respectively.

The output terminal of the OR-NAND 40 is AND-N.
Connected to the NOR-side input terminal of OR43, AND-NOR
The output terminal of the 2NAND 42 is connected to one input terminal on the AND side of the 43, and the input signal IN7 is supplied to the other input terminal. The output terminals of the input signal IN7 and the 2NAND 42 are further connected to the 2 input terminals of the 2NOR 44, respectively.

The output terminal of the AND-NOR 43 is OR-NA.
Connected to the NAND-side input terminal of ND46, OR-NAN
The output terminal of the 2NOR 44 is connected to one input terminal on the OR side of D46, the input signal IN8 is supplied to the other input terminal via the inverter 45, and the output signal OUT is output from the OR-NAND 46. Be composed.

This circuit detects that at least two bits out of n bits (n is a positive integer) of the total number of inputs, which are the result of the address comparison, are at a high level, but mathematically, (n-1) +
+ (N− (n−1)) / 2.

Next, the circuit operation will be described. AND-
Since the ground potential is supplied to the AND-side input and the NOR-side input terminal, the output of the NOR 28 always becomes the high level of the logic level regardless of the state of the input signal IN1. Next, when a high level is input to IN1 of the input signal, IN1
The output of the 2NOR 29 in which 1 is an input signal becomes a low level of the logic level, and the 2NAND 32 to which the output signal of the 2NOR 29 is input outputs a high level.

2 The output signal of the NAND 32 is used as an input.
The NOR 34 outputs a low level, and the 2NAND 37 receiving the output signal of the 2NOR 34 outputs a high level. The output signal of the 2NAND 37 is used as an input.
The NOR 39 outputs a low level, and the 2NAND 42 which receives the output signal of the 2NOR 39 outputs a high level. The output signal of the 2NAND 42 is used as an input.
The NOR 44 outputs a low level.

Thus, the high level of the 1-bit input signal is sensed and the level is transmitted. This 2NOR2
9, 2NAND32, 2NOR34, 2NAND37,
A series of level transmissions in the order of 2NOR39, 2NAND42, and 2NOR44 are performed not only for the input signal IN1, but also for the input signals IN2, IN3, IN4, IN5, IN6, and IN6.
7, when the input signal IN3 goes high, for example, the level is transmitted only to the inputs of the 2NAND37, 2NOR39, 2NAND42 and 2NOR44 after the 2NOR34 to which the input signal IN3 is input.

This level transmission is performed by the combinational circuit OR-
NAND 30, 35, 40 and 46 and AND-N
Since it is also connected to the input terminals of the ORs 33, 38 and 43, if there is a high level in two or more bits in all the input signals, it is detected as multiple selection and a high level is output.

Here, for example, if the input signals IN1 and IN2 are at a high level, the OR-side inputs of the OR-NAND 30 are both at a low level.
Is at a high level, and the output of the AND-NOR 33 that uses this output as an input signal on the NOR side is at a low level. This output signal is used as an input signal on the NAND side.
The output of the NAND 35 goes high, and the output of the AND-NOR 38, which uses this output signal as an input signal on the NOR side, goes low. The output of the OR-NAND 40 having this output signal as an input signal on the NAND side becomes high level, and the output signal of the OR-NAND 40 as an input signal on the NOR side is output.
The output of the NOR 43 becomes low level.

This output is used as an input signal on the NAND side.
The output of the R-NAND 46 is detected as multiple selection and outputs a high level.

In addition to the above-described conventional circuit example, Japanese Patent Publication No.
In a circuit for detecting a high level or a low level which is an input signal state occupying a majority of the total number of input signals, as in a majority circuit configuration shown on page 4 of JP-A-6568,
An adjacent 2-bit input signal is input to a half adder as a 1-bit half adder, and its output is also input as a 2-bit half adder configured by arranging half adders. A majority circuit is realized by a configuration of inputting as a 3-bit half adder having a configuration of arrangement, that is, a circuit configuration in which half adders are stacked.

Referring to FIG. 6 which shows a circuit diagram of an 8-bit input signal realized by a circuit configuration in which the half adders are stacked, a half adder 105 includes a 2NAND 47 and an OR side of a combinational circuit OR-NAND49. An input signal IN1 is commonly input to one input terminal, and an input signal IN2 is commonly input to each other input terminal.
47 is connected to the signal line 209 via the inverter 48, and the output terminal of the OR-NAND 49 is connected to the inverter 5
0 to be connected to the signal line 210.

The half adders 105, 106, 107, 1
07, 109, 110 and 111, and the half adder 1
Output signal lines 210 and 212 of 05 and 106 are connected to two inputs of the half adder 109, respectively, and output signal lines 214 and 216 of half adders 107 and 108 are connected to two inputs of the half adder 110, respectively. You. Output signal lines 218 and 22 of half adders 109 and 110
0 is connected to two input terminals of the half adder 111, respectively.
Output signal lines 209, 211, 213 and 2 of the inverter 48 of the half adders 105, 106, 107 and 108
15 is connected to the input terminal of the 4NOR 51 and the half adder 10
Output signal lines 217, 219 and 221 of the inverters 9, 110 and 111 are connected to the input terminals of the 3NOR 52.

The output ends of the 4NORs 51 and 52 are 2NA.
It is connected to the input terminal of the ND 53, and is configured so that the output of the 2NAND 53 is used as the output signal OUT of the multiple selection detection circuit.

Next, the operation of this circuit will be described. In this circuit, as in the circuit of the conventional example described above, if there is a high level in any two or more bits of the input signal of eight bits, a plurality of selections are detected and a high level is output. For example, two sets of input signals IN1 and IN2, IN3 and IN4, respectively input to the half adders 105 to 108,
If the input signals of IN5 and IN6 or IN7 and IN8 are both at the high level, the half adder 105
The signal lines 209, 211, which are detected by the 2NAND 47 in the middle and output from the half adder 105 via the inverter 48,
Since a high level is output to either 213 or 215, it is detected that the output of the 4NOR 51 to which this is input goes low and the output of the 2NAND 53 to which it is input goes high.

Next, if one of the input signals IN1 and IN2 of the half adder 105 is at a high level, OR-N
The signal is detected by the AND 49, and a high level is output to the signal line 210 output from the half adder 105 via the inverter 50. This is the same for the half adders 106, 107 and 108 that input the input signals IN3 and IN4, IN5 and IN6, or IN7 and IN8, and the signal lines 212, 214 and 216 also have a high level in either of these input signals. When a level is input, a high level is output.

When the output signal lines 210 and 212 or 214 and 216 are input to the half adders 109 and 110, IN1, IN2, IN3 and IN
4 or IN5, IN6, IN7 and IN8 detect that a high level has been input to any two bits, and output signal lines 217 and 219, and input signals IN1, IN2, IN3 and IN4 or IN5, I5
N, IN7, and IN8 detect that a high level has been input to any one bit, and detect signal lines 218 and 22.
0, and input this to the half adder 111,
Detecting that a high level has been input to any two of the eight bits, the signal is output to a signal line 221, and these signals are output from a detection circuit via 3NOR 52 and 2NAND 53.

As described above, the input signal state can be simultaneously detected for each 2-bit input signal unit of the half adder.

[0028]

SUMMARY OF THE INVENTION The above-mentioned conventional TLB
In the example described with reference to FIG. 5 among the multi-selection detection circuits used in FIG. 5, the combinational circuits AND-NOR and OR-NAND
Are alternately combined to detect the high level state of all input signals with two or more bits.
In this circuit configuration, the detection time of the detection circuit differs depending on the state of the input signal.

For example, as described above, in the detection circuit in the case where a high level is input to the input signals of IN1 and IN2, the OR-NAND 30 through INOR 29 through the inverter 31 if IN1 and the inverter 31 through IN31 if IN2, respectively. A
ND-NOR33, OR-NAND35, AND-NO
A plurality of detections are performed through eight combination circuits of R38, OR-NAND40, AND-NOR43, and OR-NAND46.

On the other hand, when a high level is input to the input signals of IN7 and IN8, if the input signal is IN7, 2NOR4
4 and IN8, a plurality of detections are performed via the two logic circuits of the OR-NAND 46 via the respective inverters 45. Therefore, the detection time of the detection circuit depends on the state of the input signal, and the number of input signals is large. Has a disadvantage that it cannot be used because the detection time is different.

On the other hand, in the example described with reference to FIG. 6, the detection time of this circuit also depends on the state of the input signal. For example, when the states of the input signals of the half adders are both at the high level, detection can be performed in at least four stages. In other cases, detection is performed from the states of all input signals by a circuit configuration in which half adders are stacked. Therefore, there are disadvantages that the number of logic stages increases to a maximum of eight stages, and the detection time depends on the state of the input signal.

There is also a disadvantage that the number of elements is large because half adders are stacked. The multiple selection detection circuit is required to have a circuit that has a small number of elements and realizes a detection time independent of the state of the input signal.

As described above, the conventional multi-selection detection circuit used in the TLB has a problem that the detection time is affected by the state of the input address signal due to its circuit configuration. If the number of input address signals is large, the detection time is further delayed due to the configuration, so that there is a problem that the circuit cannot be used for a product requiring a higher speed operation.

An object of the multiple selection detection circuit of the present invention is that the detection time is always equal irrespective of the state of the input address signal, and the detection time deteriorates even when the number of input address selection signals increases. It is an object of the present invention to provide a circuit configuration that does not cause a problem. Another object of the present invention is to provide a circuit with lower power consumption by reducing the number of circuit elements to be realized as compared with the conventional circuit configuration.

[0035]

The feature of the multiple selection detection circuit of the present invention is that a 2n (n is a natural number of 4 or more) input signals and a 2n-th (n ≦ 2m) input signal and 2n−1 A first input signal, and when both signals have one polarity, outputs a first output signal of the other polarity, and when the two signals have different polarities, the second output signal of the other polarity A first NAND circuit for inputting the m first output signals, and a first to n-th second output signals for inputting the m first output signals. A condition combination circuit for detecting that either the 2n-th input signal or the 2n-1th input signal has the other polarity;
And a first NOR circuit to which the output of the NOR circuit is inputted, and the output of the first NOR circuit is an output of a plurality of detections.

Further, the minimum unit detection circuit commonly inputs a 2n-th input signal and a 2n-1st input signal to a second NAND circuit and a second NOR circuit, respectively. The output signal of the NAND circuit is the first output signal of the minimum unit detection circuit, and the output signal of the second NOR circuit is the second output signal.

Further, the condition combination circuit combines m-2 first AND circuits and m-2 third NOR circuits, and generates an n-th third NOR circuit. Is connected to the n-th second output signal, and the n-th first AND circuit is connected to the (n−1) -th to m-th second output signals, The (m-1) th and m-th second output signals are connected to the inputs of the NOR circuit of No. 4, and these outputs can be output as output signals of a condition combination.

Another feature of the multiple selection detection circuit of the present invention is that
2n in the first NAND circuit and the first NOR circuit
The (n ≦ 2m) th input signal and the (2n−1) th input signal are commonly input, the output signal of the first NAND circuit is used as the first output signal, and the first NOR circuit is used. M and m-2 first AND circuits and m-2 second NOR circuits are combined with the minimum unit detection circuit using the output signal of The input of the second NOR circuit is connected to the n-th second output signal, and the n-th first AND circuit is connected to the (n−1) -th to the m-th second output signals. An output signal is connected, and the (m-1) th and mth second output signals are connected to the input of the third NOR circuit, and these outputs are output as output signals of the condition combination. A second negation to input n first output signals of the circuit and the minimum unit detection circuit Third inputting a fourth said second output signal of the NOR gate and the n number of the input and the AND circuit output of the condition combining circuit and the second NAND circuit
M (m
Is a natural number of 4 or more), (m−2) first OR circuits and (m−2) fourth NAND circuits, and the input of the n-th fourth NAND circuit Is connected to the n-th second output signal, the n-th first OR circuit is connected to the second to n-th second output signals, and the fifth NAND First and second second output signals are connected to the input of the circuit, and a logic inversion circuit of a condition combination circuit in which these outputs are output as output signals of a condition combination, and a logic inversion of the condition combination circuit And a sixth NAND circuit for receiving an output of the multiple selection detecting means.

Still another feature of the multiple selection detection circuit of the present invention is that a 2nd input signal and a 2n-1st input signal are commonly input to a first NAND circuit and a first NOR circuit, respectively. And outputs the output signal of the first NAND circuit to the first
M, the minimum unit detection circuit that uses the output signal of the first NOR circuit as the second output signal, and all the second output signals other than the complement of the n + 1th signal M connected third NOR circuits, and n−2
N first AND circuits and n−2 third NOR circuits are combined, and the input of the n-th third NOR circuit is the n-th second output signal, respectively. Are connected to the m first AND circuits, each of which includes m combination circuits to which all of the second output signals other than the n-th output signal are connected, the second NOR circuit, Fourth and fifth NOR circuits into which the outputs of the combinational circuits are divided into m / 2 groups and input, and a second NAND circuit to which the outputs of these NOR circuits are input, respectively. Consists of

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings. FIG. 1 shows a first embodiment of the present invention.
FIG. 9 is a circuit diagram of an 8-bit configuration multiple selection detection circuit in which an 8-bit address comparison result is an input signal. Referring to FIG. 1, the multiple selection detection circuit includes a minimum unit detection circuit 10.
1a, 101b, 101c and 101d, a condition combination circuit 102, 4NAND3 and 4NOR7, and the minimum unit detection circuit 101 is composed of 2NAND1 and 2NOR2, and one input terminal of each of them is commonly connected to receive an input signal IN1. The other input terminals are also connected in common and supplied with an input signal IN2, and the other minimum unit detection circuits 101b, 101c and 101d have the same configuration.

The condition combination circuit 102 includes a combination circuit AN
D-NORs 4 and 5 and NOR6. The output line 201 of the minimum unit detection circuit 101 is connected to N of AND-NOR4.
The output line 202 of the minimum unit detection circuit 101b is connected to the NOR input terminal of the AND-NOR5 and A
The ND-NOR4 is commonly connected to the first input terminal on the AND side, and the output line 203 of the minimum unit detection circuit 101c is connected to one input terminal of the 2NOR6 and the AND of the AND-NOR5.
Side first input terminal and AND-side second terminal of AND-NOR4
Are connected in common to the input terminals of
01d output line 204 is connected to the other input terminal of 2NOR6 and A
ND-NOR5 AND-side second input terminal and AND-
It is commonly connected to a third input terminal on the AND side of NOR4.

The minimum unit detection circuits 101a, 101b, 1
The output terminals of the 2NANDs 01c and 101d are connected to the input terminals of the 4NAND3, respectively.
The output terminals of the ND-NORs 4 and 5 and the 2NOR 6 are connected to the input terminal of the 4NOR 7, and the output terminal thereof is connected via the inverter 8 to the output terminal OUT of the multiple selection detection signal.

These minimum unit detection circuits 101, 101
b, 101c and 101d are input in common, and 2 bits of the address comparison result are input.
By arranging them, an 8-bit input is obtained.

Next, the circuit operation will be described. In this multiple selection detection circuit, the input signals IN1 to
It is detected that two bits of IN8 are at a high level, and the minimum unit detection circuits 101a to 101d supply input signals IN1 and IN2, IN3, which are address comparison results.
By inputting all the signals in units of IN4, IN5 and IN6 or IN7 and IN8, even if any of the input signals is at a high level, it is simultaneously detected.

For example, if the two inputs of the minimum unit detection circuit 101a are both at a high level, it is detected by 2NAND1.
The low level which is the output is input to 4NAND3,
The high level of the output is input to 4NOR7, and the low level of the 4NOR7 output becomes high level via the inverter 8 and is output as the output of the multiple selection detection circuit.

For example, when one of the two inputs of the minimum unit detection circuit 101 is at a high level, it is detected by 2NOR2 and input to the condition combination circuit 102. In the condition combination circuit 101b, a circuit configuration for comparing all input bits to detect that two bits are at a high level as in the circuit shown in FIG. 5 which is a conventional circuit configuration, or a circuit configuration as shown in FIG. , A signal line 201, 202 which is a NOR of two bits of an input signal detected by 2NOR2 in the minimum unit detection circuit 101a. , 203 and 204 are realized by circuits, thereby reducing the number of circuit stages.

For example, if all of the signal lines 201, 202, 203 and 204 are at a low level, it indicates that either of the two bits of the input signal is at a high level or both bits are at a high level. As described above, the high level state corresponds to the 2 in the minimum unit detection circuit 101a.
Since the signal is detected by the NAND1, it is sufficient to detect that one of the two bits of the input signal is at the high level. Therefore, if two signals in the signal lines 201, 202, 203 and 204 are at a low level, it can be said that two bits in the input signal as an address comparison result are at a high level. Make a decision.

The AND-NOR4 detects that the signal line 201 is at low level and any of the signal lines 202, 203 and 204 is at low level. That is, under these input conditions, the output of the AND-NOR4 on the AND side becomes low level, the output of AND-NOR4 becomes high level, and the output of 4NOR7 becomes low level and OUT-NOR4 becomes low level.
Is a high level.

The AND-NOR5 detects that the signal line 202 is at a low level and one of the signal lines 203 and 204 is at a low level. That is, AND-NO
The output on the AND side of R5 goes low, and AND-N
The output of OR5 becomes high level, the output of 4NOR7 becomes low level, and high level is detected in the output signal OUT.

The 2NOR 6 detects that the signal lines 203 and 204 are at a low level. That is, 2NOR6
Is at a high level, and similarly, the output of 4NOR7 is at a low level, and a high level is detected in the output signal OUT.

As described above, one of the outputs of AND-NOR5 and AND-NOR4 and 2NOR6 and 4NAND3
When both the input signals of the minimum unit detection circuit 101a are at a high level, the input of the 4NOR7 is at a high level, so that the output of the multi-selection detection circuit 401a of 8-bit configuration is at a low level, The level is output from the detection circuit.

Even if the number of address comparison results, which is an input signal of this circuit, increases due to the configuration of the TLB, a detection circuit can be configured based on this circuit configuration.

Next, as a second embodiment, referring to FIG. 2 which shows a multiple selection detection circuit when the address comparison result serving as an input signal is 32 bits, an 8-bit multiple selection detection circuit 401a is shown here. A configuration is adopted in which four arrays are arranged as the number of input signals increases. That is, the input signals IN1 to IN8
, A NOR7 detection signal line of the multiple selection detection circuit 401a for inputting the input signals IN9 to IN16, a 4NOR7 detection signal line of the multiple selection detection circuit 401b for inputting the input signals IN17 to IN24, and a multiple selection detection circuit 401 for inputting the input signals IN17 to IN24.
c, the NOR7 detection signal line and the input signals IN25 to IN3
The 4NOR7 detection signal line of the multiple selection detection circuit 401d for inputting 2 is connected to 4 of 7 input terminals of 7NAND16, respectively.

Further, a plurality of selection detecting circuits 401a to 401a
Of the 4NANDs 9 to 12 included in each of 1d, the output terminal of 4NAND12 of the multiple selection detection circuit 40zd is OR-N constituting the logical inversion circuit 103 of the conditional combination circuit.
It is connected to the input terminal on the NAND side of AND15.

4NAND1 of the multiple selection detection circuit 401c
1 is connected to a first input terminal on the OR side of the OR-NAND 15 and an input terminal on the NAND side of the OR-NAND 14.

4NAND1 of the multiple selection detection circuit 401b
0 is connected to the second input terminal on the OR side of the OR-NAND 15 and the first input terminal on the OR side of the OR-NAND 14 and 2N.
It is connected to one input terminal of AND13.

4NAND9 of the multiple selection detection circuit 401a
Are connected to a third input terminal on the OR side of the OR-NAND 15, a second input terminal on the OR side of the OR-NAND 14, and 2NA.
Connected to the other input terminal of ND13.

OR-NAND 15, OR-NAND 14
And the output terminals of 2 NAND 13 are 7-input NAN respectively.
D16 is connected to the remaining three input terminals, and is output from the output terminal thereof as an output signal OUT of the multiple selection detection circuit.

The operation of this circuit will now be described.
By using the output of the NAND 16 as the output of the multiple selection detection circuit, it is detected that the input signal of 2 bits out of 8 bits has a high level.

It is the 4 NAND that detects that only one bit of the 8-bit input signal is at the high level.
9, 10, 11 and 12, and the signal lines 201, 202, 203 and 204, which are the outputs of 2NOR2 in the minimum unit detection circuits 101a to 101d, respectively, are input;
These outputs are connected to signal lines 205, 206, 207 and 2
08, it is input to the logical inversion circuit 103 of the condition combination circuit, and it is detected that two bits in the signal lines 205, 206, 207 and 208 are at a high level,
A high level is output to the output of the multiple selection detection circuit via D16.

As described above, even when only one bit in the multi-selection detection circuits 401a to 401d having the 8-bit configuration is at the high level, if there is a high level in the 2-bit input signal out of the 32 bits, the detection is performed. It is done.

Next, as a third embodiment, FIG. 3 shows a circuit diagram of a multiple selection detection circuit for detecting that a high level is inputted to three or more bits of an input signal of eight bits. For reference, this multiple selection detection circuit includes minimum unit detection circuits 101a, 101b, 101c and 10c.
1d and 3-bit detection condition combination circuit 104 and 4NOR2
5 and 4 NOR 26 and 2 NAND 27 are provided.

The minimum unit detection circuit 101a is a 2 NAND
1 and 2 NOR2, each having one input terminal commonly connected and supplied with an input signal IN1, and the other input terminal also commonly connected and supplied with an input signal IN2. Other minimum unit detection circuits 101b, 1
01c and 101d have the same configuration.

The 3-bit detection condition combination circuit 104 comprises combination circuits AND-NORs 17, 19, 21 and 23 and 3NORs 18, 20, 22 and 24.

2NAND1 of minimum unit detection circuit 101a
Is an AND line of the 3-bit detection condition combination circuit 104.
The output line 209 of 2NOR2 of the minimum unit detection circuit 101a is connected to the first input terminals of 3NOR18, 20, 22 of the 3-bit detection condition combination circuit 104 and the NOR-NOR19, 21, 23 of the minimum unit detection circuit 101a. AN
Each is connected to the first input terminal on the D side.

2NAND1 of the minimum unit detection circuit 101b
Is an AND line of the 3-bit detection condition combination circuit 104.
The output line 210 of 2NOR2 of the minimum unit detection circuit 101b is connected to the second input terminal of 3NOR18, 20 of the 3-bit detection condition combination circuit 104, the first input terminal of 3NOR24, and AND-. NOR
17 AND-side first input terminal and AND-NOR21,
23 and a second input terminal on the AND side.

The 2NAND1 of the minimum unit detection circuit 101c
Is an AND line of the 3-bit detection condition combination circuit 104.
The output line 211 of 2NOR2 of the minimum unit detection circuit 101c is connected to the 3rd input terminal of 3NOR18, the 2nd input terminal of 3NOR22, 24 and AND- NOR
17 and 19, the second input terminal on the AND side and AND-NOR
23 and the third input terminal on the AND side.

The output line of NAND1 of the minimum unit detection circuit 101d is connected to the AND-
The output line 212 of 2NOR2 of the minimum unit detection circuit 101d is connected to the 3rd input terminals of 3NOR20, 22, and 24 of the 3-bit detection condition combination circuit 104 and the AND of NOR-NOR17, 19, and 21.
And a third input terminal on the side.

That is, 3NORs 18, 20, 22, 24
Is the n-th NO, if there are m NOR and m minimum unit detection circuits, respectively.
If R, output signals other than the output signal of the (m-n + 1) -th minimum unit detection circuit, which is the n-th n's complement + 1, are input, and AND-NOR17,
If the minimum unit detection circuits input at 19, 21 and 23 are the n-th AND-NOR, there is a relation that each of the output signals other than the n-th minimum unit detection circuit is input.

3N of 3-bit detection condition combination circuit 104
The output lines of OR 18 and 20 and AND-NOR 17 and 19 are connected to the input terminal of 4NOR 25 and 3NOR 22
And 24 and AND-NORs 21 and 23 have their output lines connected to the input terminal of 4NOR 26, respectively.
And 26 are connected to the input terminal of the 2NAND 27, and the output is configured as the output OUT of the multiple selection detection circuit.

Also in this circuit, the minimum unit detection circuit 1
01a to 101d can generate a detection signal by changing the condition combination circuit without changing. That is, the 3-bit detection condition combination circuit 104 that performs high-level detection of 3 bits in the input signal includes, for example, the minimum unit detection circuit 101
The AND-NOR circuits 17 and 1 detect a state in which both the input signals IN1 and IN2 are at a high level and any of the other inputs IN3 to IN8 is at a high level.
9, 21 and 23. 3NOR1 detects when one of the two input signals of the minimum unit detection circuits 101a to 101d is at a high level.
8, 20, 22, and 24.

The AND-NORs 17, 19, 21 and 23 detect when the input signals of the minimum unit detection circuit 101a are both at a high level and the other input signals are at a high level, and output a high level. Also, 3
In the NOR 18, 20, 22, and 24, the signal line 2 which is the output of NOR 2 in the minimum unit detection circuits 101 to 101d.
By taking a combination in which three of the four signal lines 01, 202, 203 and 204 have a high level, it is detected that at least three bits of the input signal have a high level.

The three-bit detection condition combination circuit 104
Is an input of 4NOR 25 and 26, an output of which is an input of 2NAND 27, an output of which is an output of a detection circuit for detecting that a 3-bit or more input signal has a high level, and outputs a high level upon detection. .

As described above, for example, a basic circuit configuration can be applied to a circuit other than the detection circuit for detecting that the address comparison results used in the TLB circuit are duplicated.
In the circuit configuration of the multiple selection detection circuit of the present invention, the number of logic circuits from the input signal to the output of the detection circuit is 8 in FIG.
Each of the embodiments of the multiple selection detection circuit having a bit configuration, the multiple selection detection circuit having a 32-bit configuration shown in FIG. 2, and the circuit for detecting the high level of 3 bits out of 8 bits shown in FIG. The detection time is not affected by the increase or decrease of the signal, and a high-level detection circuit can be used for an input signal of 3 bits or more as shown in FIG. 3 without increasing the number of logic circuit stages.

[0075]

As is clear from the above description, it has been found that the detection time of the detection circuit depends on the state of the input signal, which is the result of the address comparison, or that the detection circuit has a large number of elements and performs high-speed operation. Although there was a problem that it could not be diverted, by using the multiple selection detection circuit of the present invention, as a first effect, without being affected by the state of the input signal,
Even when a high level is input to which input signal and which input signal, the number of logic circuit stages is fixed at four and the detection time is not affected by the state of the input signal. FIG.
In the conventional circuit of FIG. 7, the number of logical stages is at most eight and at least two for the detecting operation. In the conventional circuit of FIG. 6, the number of logical stages of at most eight and at least four is required for the detecting operation. This improves the range of the detection time.

The second effect is that the number of elements in the circuit of the present invention can be reduced from the circuit configuration as compared with the conventional circuit, and the power consumed in this circuit can be reduced. Although the circuit configuration of the present invention is realized with 68 transistors, the conventional circuit shown in FIG. 5 has 84 transistors and the circuit shown in FIG. Thus, the layout area can be reduced, so that it is possible to cope with a semiconductor integrated circuit requiring higher integration.

In the third effect, as shown in FIG.
As is apparent from the detection circuit for detecting that a high level has been input to three bits of the input signal, which is an application of the multiple selection detection circuit used in the above, the basic configuration of the multiple selection detection circuit of the present invention shown in FIG. A circuit can be realized by application, and it can also be used as a detection circuit other than the TLB.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an 8-bit multi-selection detection circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a multiple selection detection circuit having a 32-bit configuration according to the first embodiment;

FIG. 3 is a circuit diagram of a high-level detection circuit of 3 bits out of 8 bits according to the first embodiment;

FIG. 4 is a block diagram showing a basic TLB operation.

FIG. 5 is a circuit diagram of a conventional 8-bit multiple selection detection circuit.

FIG. 6 is a circuit diagram of a conventional multiple selection detection circuit using an 8-bit half adder.

[Explanation of symbols]

1,13,27,22,37,42,47,53 2
NAND 2, 6, 29, 34, 38, 432 NOR 3, 9, 10, 11, 124 NAND 4, 5, 17, 19, 21, 23, 28, 33, 39,
44 AND-NOR 7,25,26,514 NOR 8,31,36,41,45,48,50 Inverter 9,10,11,124 NAND 14,15,30,35,40,46,49 OR-
NAND 16 7 NAND 18, 20, 22, 24, 52 3 NOR 101a-101d Minimum unit detection circuit 102 Condition combination circuit 103 Logical inversion circuit of condition combination circuit 104 3-bit detection condition combination circuit 105 Half adder 201-221 Signal line 401a- 401d 8-bit multiple selection detection circuit 402 Virtual address 403 TLB 404 TLB entry 405 Physical address GND Ground potential IN1 to IN32 Input signal OUT Detection circuit output

Claims (5)

(57) [Claims] 1. An input signal of the 2nth (n ≦ 2m) and 2n−1 for 2m input signals (m is a natural number of 4 or more).
A first input signal, and when both signals have one polarity, outputs a first output signal of the other polarity, and when the two signals have different polarities, the second output signal of the other polarity A first NAND circuit for inputting the m first output signals, and a first to n-th second output signals for inputting the m first output signals. A condition combination circuit for detecting that either the 2n-th input signal or the 2n-1th input signal has the other polarity, and an output of the condition combination circuit and the first NAND circuit A plurality of selection detection circuits, comprising: a first NOR circuit that performs the above operation, and an output of the first NOR circuit is an output of a plurality of detections. 2. The minimum unit detection circuit commonly inputs a 2n-th input signal and a 2n−1-th input signal to a second NAND circuit and a second NOR circuit, respectively. 2. The multiple selection detection according to claim 1, wherein an output signal of the NAND circuit is the first output signal of the minimum unit detection circuit, and an output signal of the second NOR circuit is the second output signal. circuit. 3. The condition combination circuit according to claim 2, wherein the m-2 first condition combination circuits include:
And m−2 third NOR circuits, and the input of the n-th third NOR circuit is n.
The second output signal is connected to the n-th first AND circuit, the (n-1) th to m-th second output signals are connected to the n-th first AND circuit, and the fourth NOR 2. The multiple selection detection circuit according to claim 1, wherein the (m-1) th and mth second output signals are connected to an input of the circuit, and these outputs are output as output signals of a condition combination. 4. A 2nd (n.ltoreq.2m) th input signal and a 2n-1st input signal are commonly input to a first NAND circuit and a first NOR circuit, respectively. M and m-2 first and second minimum unit detection circuits each having an output signal of an AND circuit as a first output signal and an output signal of the first NOR circuit as the second output signal; An AND circuit and m−2 second NOR circuits are combined, and an n-th second output signal is connected to an input of the n-th second NOR circuit, and an n-th second output signal is connected. The first AND circuit is connected to the (n-1) -th to m-th second output signals, and the inputs of a third NOR circuit are the (m-1) -th and m-th second signals. Output signals are connected, and these outputs are output as output signals of condition combinations. A second NAND circuit for inputting the n first output signals of the position detection circuit, a fourth NOR circuit for receiving the outputs of the conditional combination circuit and the second NAND circuit, m (m is a natural number of 4 or more) plural selection detection means including n third output circuits for inputting the second output signals, and m-2 first OR circuits And m−2 fourth NAND circuits, and the input of the n-th fourth NAND circuit is connected to the n-th second output signal, and the n-th fourth NAND circuit is connected. 1
Are connected to the second to n-th second output signals, and the input of the fifth NAND circuit is 1
A logic inversion circuit of a condition combination circuit, to which the second and second output signals are connected, and outputs thereof as output signals of a condition combination; a logic inversion circuit of the condition combination circuit; And a sixth NAND circuit for inputting an output of the means. 5. A 2nd input signal and a 2n-1st input signal are commonly input to a first NAND circuit and a first NOR circuit, respectively, and an output of the first NAND circuit is provided. M minimum unit detection circuits that use the signal as the first output signal and the output signal of the first NOR circuit as the second output signal; M of the third NOR circuits to which the output signals of
n-2 first AND circuits and n-2 third NOR circuits are combined, and an input of the n-th third NOR circuit is an n-th second NOR circuit, respectively. Are connected to the m number of first AND circuits, and m combinational circuits are connected to all of the second output signals except n-th, respectively, and the second NOR circuit Fourth and fifth NOR circuits into which the outputs of the circuit and the combinational circuit are divided into m / 2 groups, respectively, and a second NOR circuit to which the outputs of these NOR circuits are inputted A multi-selection detection circuit, comprising a product circuit.