JP2857446B2 - ATM switch - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Overview Industrial application field Conventional technology (Figs. 7 to 9) Problems to be solved by the invention Means for solving the problems (Figs. 1 and 2) (FIGS. 1 to 3) Embodiment (FIGS. 4 to 6) Effect of the Invention [Overview] A switch module having buffers for storing asynchronously multiplexed cells is configured in multiple stages, and this cell is ATM swapping between input and output highways
The exchange is congested on the downstream side by having the function of notifying the buffer on the upstream side of the use state of the buffer on the upstream side and the function of controlling the transmission of cells for each output route at the downstream side on the upstream side. The purpose is to stop reading only to the buffer and enable reading to other buffers. Determination / notification means for notifying the preceding switch module of a regulation request to regulate the transmission of cells to the buffer; and reading of cells in a path toward the buffer exceeding a predetermined value in the preceding switch module. And a buffer control means for reading cells to other routes. The switch module comprises a cell storage buffer provided between a pair of input / output highways, and management means for managing output path number information of the cells in the buffer in association with the cells. Buffer means for comparing the departure number information obtained from the restriction request notified from the determination / notification means with the managed departure number information managed by the management means; Based on the result of the comparison, cell reading control means for stopping reading cells to the path to the buffer exceeding the prescribed value and reading cells to the other paths is provided.

[Industrial applications]

The present invention provides a multi-stage switch module having a buffer for storing asynchronously multiplexed cells,
The present invention relates to an ATM [Asynchronous Transfer Mode; ATM] exchange for exchanging these cells between an input highway and an output highway.

In recent years, as a method for realizing broadband ISDN, it has both the bandwidth flexibility of packet switching and the time transparency of circuit switching.
ATM exchange technology using ATM has been agreed at CCITT, and research is being actively conducted at each institution.

[Conventional technology]

In such an ATM switch, cells are exchanged between input and output highways in which information is statistically multiplexed in units of fixed-length blocks with headers called cells, while looking at headers in which destinations are written.

At this time, as shown in FIG. 7, buffer memories (FIFO memories; first-in first-out memories) 101-11 to 101-nn are provided for each of the output highways # 1 to #n in order to avoid cell collision. Have been.

Then, these buffer memories 101-ij (i = 1 to
The reading of (n, j = 1 to n) is performed, for example, as follows. That is, focusing attention on the output highway # 1, as shown in FIG.
Cell presence / absence information from ~ 101-n1 [Empty
Flag; this flag indicates that the cell is present when the flag is 1, and that the cell is absent when the flag is 0.]. The read sequence controller 100 controls the reading of the cells from the buffer memories 101-11 to 101-n1 and sends the cells to the output highway # 1. The reading order control device 100 polls each of the buffer memories 101-11 to 101-n1, so that the output right of the output highway is transferred from the buffer memory 101-11 to the buffer memory 101-n1.
It gradually shifts to. After the buffer memory 101-n1, the process returns to the buffer memory 101-11.

In this case, the buffer memory given the transmission right sends the cell to the output highway if the cell is stored, but passes the transmission right to the next buffer memory if the cell is not stored.

The same applies to other output highways # 2 to #n.

In addition, the communication path shown in FIG.
For example, it has been considered to connect the switch modules Sij in multiple stages as shown in FIG.

[Problems to be solved by the invention]

By the way, in an ATM exchange, cells are generated in bursts to accommodate various traffic services. Therefore, in this case, cells are instantaneously concentrated in a specific buffer memory, but conventionally, such a case has not been dealt with, so that the buffer memory in which the cells are concentrated overflows and cells are discarded. .

To avoid such cell discard, it is conceivable to increase the size of the buffer memory.However, this is disadvantageous in terms of cost, and the time required for storing cells in the buffer memory becomes longer, so that the transmission delay becomes longer. There is a problem that becomes.

Furthermore, in a multi-stage ATM communication channel, cells are written to the buffer in the order in which they arrive, and cells are read out of the buffer in order without any control of the cell reading order and collisions are avoided. When cells are concentrated on the road, the buffer of the next stage overflows.

Further, in the ATM communication path, control is performed at the time of call setup so as to make the usage rate of each link uniform, but load imbalance may occur momentarily. If the traffic distribution in the communication path is not uniform as described above, there is a case where the usage rate of the preceding stage is low even if the usage rate of a specific buffer is high. In other words, there is a case where the load is concentrated on a specific buffer and the cell is discarded even though the other buffers are empty. In such a case, cells are stored in a low-load pre-stage connected to a high-load buffer, and transmission to a high-load path is refrained, so that cell loss in a high-load buffer is suppressed to a low level. be able to. However, since the cells of each route are multiplexed on the output highway of the switch, if the reading of the cells is stopped simply because one of the buffers in the next stage is congested, the reading of the next stage is stopped. Reading will be stopped up to the cells of the empty buffer.

For this purpose, it is necessary to selectively transmit cells for each route.

The present invention has been devised in such a situation, and has a function of notifying a preceding buffer of a use state of a subsequent buffer and a function of controlling cell transmission on a per output path basis in a preceding stage. It is an object of the present invention to provide an ATM switch in which only reading to a buffer that is congested at the subsequent stage is stopped, and reading to another buffer can be performed.

[Means for solving the problem]

In the present invention, as shown in FIG. 1, switch modules Sij each having a buffer for storing asynchronously multiplexed cells are configured in multiple stages, and the cells are exchanged between an input highway and an output highway. But first,
The switch module, which can be a relatively downstream side, is provided with means for determining whether or not the cell storage amount of the buffer exceeds a specified value.

Also, between the switch modules, a control line C [(j + 1) i → which notifies the preceding switch module of the fact that the specified value has been exceeded by the determination means of the subsequent switch module if the specified value is exceeded. (J) i] is provided. As described above, the switch module on the relatively subsequent stage includes, as determination / notification means, means for determining whether or not the cell storage amount of the buffer exceeds the regulation, and a regulation request for regulating transmission of cells to the preceding stage. And a control line for notifying that the specified value has been exceeded.

Further, the switch module that can be a relatively preceding stage stops reading cells from the information sent through the control line C [(j + 1) i → (j) i] to the buffer exceeding the specified value, There is provided a buffer control means for reading cells to other routes and sending the cells to the subsequent switch module.

Also, each switch part 200- of the switch module Sij
As shown in FIG. 2, ij is a cell storage buffer 1, a cell empty / busy management table 2, a shift register type FIFO memo 3 (management means), a search means 4, an outgoing route number storage means 5, a control means. 6
(Comparing means) and a readout circuit 7 (cell readout control means).

The search means 4, the outgoing route number storage means 5, the control means 6, and the read circuit 7 constitute the buffer control means.

Here, the cell storage buffer 1 is provided between a pair of input / output highways and is a memory for storing cells. The cell empty / busy management table 2 manages the empty / busy state of the cells in the buffer 1. is there.

The shift register type FIFO memory 3 stores the outgoing route number information and the storage address information of the cells in the buffer 1 as management information in the order of cell arrival and manages these information. That is, the shift register type FIFO memory 3 is
It functions as management means for managing the outgoing route number information of the cell in the buffer in association with the cell.

Also, the search means 4 is a shift register type FIFO memory 3
Are sequentially searched from the beginning of the cell, and if there is a cell, and if there is a cell, the outgoing route number is searched. Is stored in the outgoing route number in which the cell storage amount of the data exceeds the specified value.

The control means 6 compares the outgoing route number from which no cell is output from the outgoing route number storing means 5 with the retrieval result from the retrieving means 4, and finds that the switch module other than the switch module whose accumulated amount exceeds the specified value. This is to extract the management information of the cell going to. That is, the control unit 6 has a function of a comparing unit that compares the outgoing route number information obtained from the restriction request notified from the determining / notifying unit with the managed outgoing route number information managed by the managing unit. Things.

The readout circuit 7 (cell readout control means), based on the storage address information of the cells among the management information from the FIFO memory 3 extracted by the control means 6, extracts the cells in the buffer 1 from the cells to the designated output path. Are read out sequentially. When the read circuit 7 reads a cell from the buffer 1, the read circuit 7 outputs a signal for changing the cell empty / busy state in the cell empty / busy management table 2 to an empty state.

That is, the readout circuit 7 functions as a cell readout control unit that stops reading cells on the route to the buffer exceeding the specified value and reads cells on the other routes based on the comparison result by the comparison unit. I do. More specifically, the readout circuit 7 determines that the outgoing route number information obtained from the barring request notified from the determination / notifying unit is a barring output specified as the outgoing route number information for which cell transmission is to be barred. In the case of the route number information, if the regulated outgoing route number information matches the managed outgoing route number information based on the comparison result by the comparing means, the outgoing route specified by the managed outgoing route number information While the cell reading to the path is stopped, if the regulated departure number information does not match the management departure number information, the cell reading to read the cell to the departure path specified by the management departure number information is performed. Functions as control means.

As a result, each switch portion 200-ij of the switch module Sij searches for the presence or absence of a cell from the head of the FIFO memory 3 to the requested departure path, and switches other than the switch module whose accumulated amount exceeds the specified value. When the management information of the cell heading for the module is found, the management information is extracted from the FIFO memory 3 and read out in order from the cell to the designated departure route based on the obtained storage address information of the cell. It is.

(Operation)

In the above-described ATM switch of the present invention, when the determination unit detects that the cell storage amount of the buffer in the subsequent switch module has exceeded the specified value, the control line C
Through [(j + 1) i → (j) i], the effect is notified to the preceding switch module.

Then, in the switch module at the preceding stage which has received this notification, the buffer control means stops reading cells to the switch module exceeding the prescribed value, reads cells to other routes, and replaces the cells in the subsequent stage. It is sent to the switch module on the side.

For example, as shown in FIG. 3, when the load is biased such that the buffer going out to the second-stage outgoing route 4 is crowded and the buffer of the outgoing route 1 still has room. By way of example, the operation of the ATM switch of the present invention will be described as follows.

First, when the load of the buffer on the outgoing route 4 in the second stage becomes equal to or more than the specified value, a restriction request is issued in the first stage. This gives 1
In the buffer of the second stage, the cells going to the outgoing route 4 in the second stage are not read out from the buffer, but are read out from the cells going to the exceptional outgoing route and transmitted.

Also, as shown in FIG. 2, cells from the input highway are accumulated in the cell accumulation buffer 1. At this time, the empty / busy state of the cells in the buffer 1 is managed by the cell empty / busy management table 2. The outgoing route number information and the storage address information of the cells in the buffer 1 are managed in the shift register type FIFO memory 3 in the order of cell arrival.

In such a state, cell transmission from the buffer 1 is performed as follows. First, the search means 4 sequentially searches from the top of the shift register type FIFO memory 3,
If there is a cell, and if there is a cell, its outgoing route number is searched. Then, the control means 6 stores the departure route number storage means 5
, And when the cell is not equal to the search result from the search means 4, that is, when the cell is not a cell to a switch module whose cell transmission is regulated, the FIFO memory From 3, the management information of the cell going to the switch module other than the switch module whose accumulated amount exceeds the specified value is extracted.

After that, the read circuit 7 reads the cells in the buffer 1 based on the storage address information of the cells among the management information from the FIFO memory 3 extracted by the control means 6, and outputs the cells to the designated output path. Are read out sequentially. In addition,
When a cell is read from the buffer 1, the read circuit 7 sets the cell busy state in the cell busy management table 2 to an empty state.

As a result, each switch portion 200-ij of the switch module Sij searches for the presence or absence of a cell from the head of the FIFO memory 3 to the requested departure path, and switches other than the switch module whose accumulated amount exceeds the specified value. When the management information of the cell going to the module is found, the management information is extracted from the FIFO memory 3 and read out in order from the cell to the designated departure route based on the obtained storage address information of the cell. is there.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Also in this embodiment, as shown in FIG. 4 (a), switch modules Sij having buffers for storing asynchronously multiplexed cells are configured in multiple stages, and these cells are connected to an input highway and an output highway. Between the switch modules Sij.
A link and a control line C [(j + 1) i → (j) i] (corresponding to a notification unit) are interposed.

Here, the link is a line for transmitting the cell to the next-stage switch module, and the control line C [(j + 1) i → (j) i].
Is a line for notifying the preceding switch module that the cell storage amount of the buffer of the subsequent switch module has exceeded a specified value.

Incidentally, the switch module Sij is shown in FIG.
As shown in (1), in order to selectively transmit cells from input highways # 1 to #n to output highways # 1 to #n,
Input highways # 1 to #n and output highways # 1 to #n
Nxn switch portions (hereinafter, referred to as cross point portions) 200-1 provided at each cross point portion
1 to 200-nn, n selectors 201-1 to 201-n, and selector control units 202-1 to 20 to control each selector 201-j
2-n.

First, each cross point section 2 of the switch module Sij
00-ij is the cell storage buffer 1 as shown in FIG.
1, cell vacancy management table 12, shift register type FIFO memory (multi-port FIFO) 13 (corresponding to management means), cell write control unit 14, cell read control unit 15 (corresponding to buffer control means), cell storage amount judgment Part 16 (corresponding to the judgment means)
Is provided.

Here, the cell storage buffer 11 is a memory provided between a pair of input / output highways and capable of storing cells at required addresses. This is a memory for managing the state.

The shift register type FIFO memory 13 stores outgoing route number information and cell storage address information in the buffer 11 in order of cell arrival, and manages these information.
FIG. 6 shows a configuration example of the shift register type FIFO memory 13. That is, the shift register type FIFO memory 13 is of a four-stage shift type. The shift register type FIFO memory 13 includes register type data latches 131-1 to 131-4, a latch data selector 132, a data latch Read / write pulse transmission logic gate section 133-1 to 133-4 for control, RS flip-flop 134
-1 to 134-4, an address decoder 135, and a data empty information output selector 136 are provided.

The data latches 131-1 to 131-4 latch data. First, data from the input highway coming from the input terminal Din is latched by the data latch 131-1. Thereafter, data is sequentially shifted to the next data latch by signals from the read / write pulse transmission logic gates 133-1 to 133-4, and the corresponding data latch temporarily stores the data each time. It is supposed to.

The latch data selector 132 is connected to each data latch 134-1.
−４134-4 are selected and output from the output terminal Dout.

Read / write pulse transmission logic gates 133-1 to 133-
4 controls the data latches 131-1 to 131-4 together with the RS flip-flops 134-1 to 134-4. The read / write pulse transmission logic gate unit 133-1 includes an AND logic gate 131-1. The other read / write pulse transmission logic gates 133-2 to 133-4 include AND logic gates 1331-2 to 1331-4 and OR logic gates 1332 to 1332-4 for information feedback. With

The gate 1331-1 receives the write enable signal from the write enable terminal WE as it is, and also inverts and receives the Q output (non-inverted output) of the RS flip-flop 134-1 and the output of the gate 1332-2, respectively. AN
The D logic result is output to the clock terminal of the data latch 131-1 and the set terminal of the RS flip-flop 134-1.

The gates 1331-2 to 1331-4 receive the non-inverted outputs of the RS flip-flops 134-1 to 134-3 as they are, the Q outputs of the RS flip-flops 134-2 to 134-4, and the gates 1332-3 to 1332, respectively. -4, and outputs the AND logic result to the clock terminals of the data latches 131-2 to 131-4 and the set terminals of the RS flip-flops 134-2 to 134-4, respectively. is there.

Gates 1332-2 to 1332-4 are respectively gate 1331-
Receiving the outputs of 2-1331-4 and the corresponding decode bit output from decoder 135, the OR logic result is output to gate 1331.
-1 to 1331-3 and RS flip-flops 134-1 to 134
-3.

The RS flip-flops 134-1 to 134-4 latch data latch control outputs from the read / write pulse transmission logic gate units 133-1 to 133-4. The read / write pulse transmission logic gate section is set to the write enable state.
The signals are reset by signals from gates 1332-2 to 1332-4 of 133-2 to 133-4.

The decoder 135 decodes the address information input through the address terminal Addr using the write enable signal from the write enable terminal RE as a trigger signal into a code having a length corresponding to the number of shift stages (4 bits in this case). The corresponding decode bit output is output to the gate 1332-2 of the read / write pulse transmission logic gate unit 133-2 to 133-4.
~ 1332-4, and input to selectors 132 and 136.

The selector 136 includes RS flip-flops 134-1 to 134-
4 to output the data free information from the data free information output terminal EMP.

With such a configuration, a shift register type FIFO memory
13 is sequential data latch by write enable signal
Data is latched into 131-1 to 131-4. When reading data latched in one of the data latches, the required address information may be input by using the write enable signal as a trigger. For example, consider the case where the data latched by the data latch 131-2 is taken out. In this case, the selector 135 uses the decoded output from the decoder 135 (the second bit is "1") to select the data.
132 selects the output of the data latch 131-2 and the gate 313 of the read / write pulse transmission logic gate 133-3.
The RS flip-flop 134-2 is reset by the output from 2-3. In this way, this RS flip-flop
When the reset output of 134-2 is input to the read / write pulse transmission logic gate 133-2, the gate 1331-2 of the read / write pulse transmission logic gate 133-2 sends a latch control signal to the data latch 131-2. Then, the contents of the preceding data latch 131-1 are latched. This means that the data latch 131-1 has shifted to the data latch 131-2. When the data is thus shifted to the data latch 131-2, the RS flip-flop 134-2 is set again. The read / write pulse transmission logic gate 133-
In response to the signal from the second gate 1331-2, the gate 1332-2
Resets the RS flip-flop 134-1 and outputs information indicating that the RS flip-flop 134-1 is empty.

The above operation is performed in the same manner regardless of the data taken from any data latch.
When data is taken out from the data latch, the subsequent data autonomously fills the preceding stage.

Further, the cell write controller 14 shown in FIG. 5 finds an empty buffer from the information in the empty / busy management table 12 in response to a search start signal on the write side, and, when a cell arrives, returns to the write signal and buffers the cell. At the same time as writing to 11, the address of the buffer and the outgoing path number to the next stage are written to the shift register type FIFO memory 13, and furthermore, the corresponding part of the empty / busy management table 12 is closed, and the counters 141, 142, It is provided with a search gate 143, an RS flip-flop 145, a write control gate 144, and the like.

That is, in the cell write control unit 14, when a search start signal is input, at this time, if the gate 143
Is in the standby state after receiving the blockage signal “1” from the air / occupancy management table 12, a counter start signal (enable signal) is output from the gate 143, whereby the counter 142 starts counting, and A search is sequentially performed for the portion containing the 12 free / busy information. At this time, whether the gate 143 is empty or closed is output from the empty / occupied management table 12 as “0” and “1” information. And
If there is a vacant portion during the search, a signal “0” indicating that the gate 143 is vacant is output, and the counter 142 stops. As a result, when the vacancy information in the vacancy management table 12 is found, it stops at that portion and waits. The RS flip-flop 145 is set by a search start signal, and is reset by a signal obtained by inverting a vacant signal from the vacancy management table 12 to the gate 143. By this reset, the RS flip-flop 145 outputs a write enable signal. Thus, a write signal can be output at any time.

Thereafter, when a cell arrives, a write signal is output. At this time, the gate 144 is in an open state, and the counter 141 writes the cell into the buffer 11 by the length thereof. At this time, the corresponding portion of the empty / busy management table 12 is set to a closed state by a write signal. Further, since this write signal is also input to the write enable terminal WE of the shift register type FIFO memory 13, the address just written and the output path number to the next stage are written into the shift register type FIFO memory 13.

The cell read control unit 15 responds to a read cell search signal before reading a cell from the buffer 11.
Looking into the shift register type FIFO memory 13, a cell in which a regulation request has not been received from the next-stage switch module Sij is found, and when the cell reading timing comes, the corresponding part of the read / write management table 12 is vacated. State, counters 151 and 152, search gate 153,
154, RS flip-flop 156, write control gate 15
5, Comparator 157 (corresponding to comparison means), departure route number storage unit 158
And so on.

That is, when a search start signal (different from the above-described write-side search start signal) is input to the cell read control unit 15, at this time, the output path number from the shift register type FIFO memory 13 is Departure route number storage 15
If the output route number that does not output the cell from 8 matches, the low output is output from the comparator 157 to the gate 154, and the counter start signal (enable signal) is output from the gate 153, Thus, the counter 152 starts counting and sequentially searches the shift register type FIFO memory 13. By this search, the outgoing route number is output from the shift register type FIFO memory 13, and this is compared with the outgoing route number from the outgoing route number storage unit 158 which does not output the cell in the comparator 157. . And
At this time, if they are not equal, the comparator 157 outputs a high level signal. Thus, the counter 152 stops. The RS flip-flop 156 is reset by a search start signal and set by a signal from the comparator 157. Then, by this setting, the RS flip-flop 156 outputs a read enable signal. As a result, a read signal can be output at any time (this function corresponds to the function of the cell read control unit).

Thereafter, at the required cell read timing, a read signal is output. At this time, the gate 155 is in an open state, and the counter 151 reads cells from the buffer 11 by that length. At this time, the corresponding portion of the empty / busy management table 12 is set to an empty state by an output signal from the FIFO memory 13.

The cell storage amount determination unit 16 determines whether or not the cell storage amount of the buffer 11 has become equal to or greater than a specified value based on the idle / occupied state of the idle / occupancy management table 12. The corresponding outgoing route number is transmitted to the route number storage unit 158 via a control line.

With such a configuration, first, prior to cell writing and reading, a search start signal on the write side and a search side on the read side are input at required timings, respectively. , And a cell in which a regulation request has not been received from the next-stage switch module Sij by looking into the shift register type FIFO memory 13.

When a cell arrives in such a state, the cell write control unit 14 writes the cell to the buffer 11 by a write signal, and at the same time, writes the address of the buffer and the outgoing path number to the next stage in the shift register type FIFO memory. 13 is written, and the corresponding portion of the air / fault management table 12 is closed.

When reading cells from the buffer 11,
When the cell read timing comes, the cell is read from there, and the corresponding portion of the empty / busy management table 12 is made empty.

As a result, each cross point unit 200-ij of this switch module Sij searches for the presence / absence of cells from the top of the FIFO memory 13 to the requested outgoing route, and searches for cells other than the switch module whose accumulated amount exceeds the specified value. When the management information of the cell heading for the switch module is found, the management information is extracted from the FIFO memory 13 and read in order from the cell to the designated departure route based on the obtained storage address information of the cell. It is.

Further, the selector section 201-j shown in FIG. 4 (b) includes the n cross point sections 200 output as described above.
Select cells from -1j to 200-nj and output highway #
j, and the switching control of the selector unit 201-j is performed by the selector control unit 202-j. That is, the selector control unit 202-j determines whether the cross point unit 200
Upon receiving the read enable signals of -1j to 200-nj, the switching control of the selector 201-j is performed so that the cells from the crosspoint units 200-1j to 200-nj do not compete.

In this embodiment, switch modules having cross points shown in FIG. 5 are connected in multiple stages, and for the switch module used in the first stage, the use state of the next stage buffer is stored in the buffer of the previous stage. The function of notifying is not used, only the function of controlling the cell transmission in the previous stage for each output route of the next stage is used, and for the last switch module, the cell transmission is controlled in the previous stage by the output stage of the next stage. The function of controlling each path is not used, and only the function of notifying the use state of the next-stage buffer to the preceding buffer is used. However, the switch modules except for the first and last stages are shown in FIG. A switch module having a cross point section is used, and the switch module used in the first stage has only the function of controlling the cell transmission in the previous stage for each output route of the next stage. Using those withered, for further final stage switch modules may be used which is provided with a only a function of notifying the use state of the next buffer in front of the buffer.

Therefore, according to the ATM switch, when the cell storage amount determination unit 16 detects that the cell storage amount of the buffer in the subsequent switch module has exceeded the specified value, the control line informs the control unit of the fact through the control line. The switch module is notified.

Then, in the switch module of the preceding stage that has received this notification, the cell read control unit 15 stops reading cells going to the switch module whose accumulated amount exceeds the specified value, and reads cells going to other routes. The lever cell can be sent to the subsequent switch module.

In this embodiment, in order to manage cell reading for each output path, management information is extracted from each stage of the shift register type FIFO memory 13, and after the extraction, the subsequent information is autonomously forwarded. It is possible to use a buffer with a smaller capacity compared to one that has a buffer for each departure route, and the buffer is shared by each departure route. The cell transmission control can be performed with higher reliability as compared with a method in which a pointer chain indicating a storage address of a cell is assembled and managed for each route.

〔The invention's effect〕

As described in detail above, the ATM switch of the present invention (claim 1,
According to 2), the ATM switch has a determination / notification means in the subsequent switch module, a buffer control means in the preceding switch module, and a cell storage buffer, a management means, a comparison means, and a cell readout in each switch module. With the configuration including the control means, by having a function of notifying the use status of the next buffer to the previous buffer, and a function of controlling the transmission of cells in the previous stage for each output route of the next stage, Since there is an advantage that reading only to the next-stage crowded buffer can be stopped and reading to another buffer can be performed, each switch section of the switch module manages cell reading for each output path. Then, the management information is extracted from each stage of the shift register type FIFO memory, and after extraction, the information after that is automatically Which is configured as, it is possible to buffer the use of a small capacity, thereby addition it is possible to reduce the buffer amount is advantageous perform a cell transfer control with high reliability.

[Brief description of the drawings]

1 and 2 are block diagrams showing the principle of the present invention, FIG. 3 is a diagram for explaining the operation of the present invention, and FIG. 4 (a) shows an ATM communication path applied to one embodiment of the present invention. FIG. 4 (b) is a block diagram showing a switch module as one embodiment of the present invention, FIG. 5 is a block diagram showing a cross point portion of the switch module as one embodiment of the present invention, and FIG. The figure is a block diagram of a shift register type FIFO memory, FIG. 7 is a diagram schematically showing a communication path of a general ATM exchange, FIG. 8 is a block diagram showing a conventional example, and FIG. 9 is a multistage switch module. It is a block diagram in the case of comprising. In the figure, 1 is a cell storage buffer, 2 is an empty / busy management table, 3 is a shift register type FIFO memory, 4 is a search means, 5 is an outgoing path number storage means, 6 is a control means, 7 is a readout circuit, 11 Is a cell storage buffer, 12 is a cell empty / busy management table, 13 is a shift register type FIFO memory, 14 is a cell write control unit, 15 is a cell read control unit, 16 is a cell storage amount determination unit, and 131-1 to 131- 4 is a data latch, 132 is a latch data selector, 133-1 to 133-4 are read / write pulse transmission logic gates, 134-1 to 134-4 are RS flip-flops, 135 is an address decoder, and 136 is data empty information output Selector, 141 and 142 are counters, 143 and 144 are gates, 145 is an RS flip-flop, 151 and 152 are counters, 153 to 155 are gates, 156 is an RS flip-flop, 157 is a comparator, and 158 is an output path number storage unit. 200-ij is a cross point portion (switch portion), 201-j is a selector, 202-j is a selector control portion, 1331-1 to 1331-4, 1332-2 to 1332-4 are gates, and C [(j + 1) i → (j) i] is a control line, and Sij is a switch module.

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor: Jomasu Kamoi 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-63-62431 (JP, A) JP-A-63-63 117535 (JP, A) JP-A-63-102527 (JP, A) JP-A-63-67047 (JP, A) IEICE SE87-72 (58) Fields investigated (Int. Cl. ⁶ , DB name) ) H04L 12 / 56,12 / 28

Claims (2)

(57) [Claims] 1. A switch module having a buffer for storing asynchronously multiplexed cells is configured in multiple stages,
In an ATM switch that exchanges the cells between the input highway and the output highway, if the cell storage capacity of the buffer in the subsequent switch module exceeds the specified value, the transmission of cells to the buffer exceeding this specified value is restricted. Determination / notification means for notifying the preceding switch module of a restriction request to perform the control, and in the preceding switch module, stop reading cells on the route to the buffer exceeding the specified value, and Buffer control means for reading out a cell to a route and sending the cell to the subsequent switch module, wherein each switch portion of the switch module comprises a cell storage buffer provided between a pair of input / output highways; And management means for managing the outgoing route number information of the cell in the buffer in association with the cell. The buffer control means provided in the switch module of the preceding stage comprises: a departure number information obtained from the restriction request notified from the determination / notification means; and a management departure number managed by the management means. Comparing means for comparing information with the information, and cell reading for stopping reading of cells to a route to a buffer exceeding the specified value and reading cells to other routes based on a comparison result by the comparing means. An ATM exchange characterized by comprising control means. 2. The outgoing route number information obtained from the control request notified from the determining / notifying means is regulated outgoing route number information defined as outgoing route number information for which cell transmission should be controlled. And when the cell readout control means matches the regulated outgoing route number information with the managed outgoing route number information based on the comparison result by the comparing means, While reading out the cell to the prescribed outgoing route is stopped, if the regulated outgoing route number information does not match the managed outgoing route number information, the output specified by the managed outgoing route number information is not performed. 2. The ATM exchange according to claim 1, wherein the ATM exchange is configured to read cells to a route.