JP3356141B2 - ATM switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ATM (Asynchronou).
The present invention relates to cell contention control technology in s Transfer Mode (asynchronous transfer mode), and specifically to an ATM switch.

[0002]

2. Description of the Related Art ATM technology is applied to a method of transmitting information in a broadband service integrated digital network. The ATM divides various kinds of information into short fixed-length blocks with headers called "cells", and multiplexes the blocks for transmission. This A
TM combines the advantages of conventional circuit switching and packet switching. Further, broadband transmission is possible, and the present invention can be applied to transmission of multimedia data having various data formats.

[0003] For the cell exchange in such ATM communication, an ATM exchange device for exchanging fixed-length cells at high speed by hardware using a simplified protocol is used. The ATM switch used in the ATM switching apparatus has a possibility that a cell collision, that is, a state in which a plurality of cells arriving from different input lines simultaneously require a connection to the same output line may occur.

When such a cell collision occurs, A
By temporarily storing cells in a cell buffer provided inside the TM switching device, cell discard is avoided, and A
It is necessary to keep the cell loss rate in the TM switching device low. As a method for achieving this object, an input buffer type AT in which a cell buffer is arranged in a preceding stage of the space switch without increasing the operation speed of the space switch.
It is known that the M switch is preferable for hardware implementation.

However, in such an input buffer type ATM switch, the throughput of the ATM switch is reduced due to HOL (Head-of-Line) blocking.
Here, the HOL blocking means that, for example, a cell located at the head of an input cell buffer that operates on a FIFO (First-In-First-Out) rule and is temporarily stored in order to avoid cell collision is allocated to a certain input line. In this case, the second and subsequent cells stored in the input cell buffer cannot be connected to the output line even if the output line to be connected is empty.

Accordingly, the throughput can be improved without increasing the operation speed of the space switch relative to the input / output line speed, cell loss is reduced, and HO
There is a demand for the development of an ATM switch that can reduce L blocking. In order to respond to this request, for example, as disclosed in Japanese Patent Application Laid-Open No. Hei 10-51461, there are N input lines and M output lines, and M.times.N arrangements are arranged at the cross points to arrive. A space switch at the preceding stage for connecting to the output line in accordance with the destination information of the cell, and an ATM switch including M output cell buffers for storing cells connected to the output line, respectively. A subsequent spatial switch provided with an output line in which cells not connected to the output of the preceding spatial switch provided at each cross point of the switch are respectively input and the outputs are respectively connected to the M output cell buffers. An ATM switch having a configuration including the following has been proposed.

According to the technique disclosed in this prior art document, for a cell lost in the first contention control in the preceding space switch connected to a certain output buffer through one output line, another output is provided. In a subsequent space switch connected to the output buffer through a line, 2
The second competition control can be performed. Therefore, even if there is a cell that has lost due to contention control, cell transmission is performed smoothly and
It is said that it can be performed while satisfying a certain throughput. That is, in the ATM switch described in the above publication, an input line is always connected to a space switch in a preceding stage connected to an output buffer through one output line. As a result, the input line is connected to the output line in a concentrated manner.

On the other hand, there is no input line directly connected to the subsequent space switch connected to the output buffer through another output line, and the contention control is performed at least once and the contention control loses. Only cells will arrive.

[0009]

However, according to the technique described in the above publication, as described in the following document 1, when the number N of input lines is small, continuous input buffers connected to the same input line are connected. Therefore, the probability of input of cells requesting connection to the same output buffer increases in inverse proportion to N. Therefore, if the first cell loses the contention control in the preceding space switch where the input lines are concentrated, even if the output line connected to the next space switch is vacant, It is stored in the input cell buffer and causes HOL blocking. That is, when the number N of input lines is small, there is a problem that the throughput is reduced due to the HOL blocking. (Reference 1: ICI Transaction on Communication E81-B Volume 215-22
3 pages. )

The present invention has been made in view of such circumstances, and is an ATM switch which improves throughput without increasing the operation speed of a space switch relative to the input / output line speed. An object of the present invention is to provide an ATM switch in which a decrease in throughput due to HOL blocking is small even when the number of output lines is small.

[0011]

The ATM switch according to the present invention has N input cell buffers, and M.times.N ones are arranged at cross points between N input lines and M output lines. It has space switches with two inputs and two outputs, each with 2
In an ATM switch which is connected to the one-input two-output spatial switch through the output lines and has M output cell buffers for accumulating cells, the one-input two-output spatial switch uses destination information of an incoming cell. , Cascade-connected two one-input / one-output space switches that perform connection to the output according to the following equation, and one of N output lines among two output lines connected to the same cell buffer. More than N
For the cells input from less than L input lines and the cells not connected to the output by the other output line contention control among the cells input to the remaining (NL) input lines, The output line for performing contention control, the cells input from the remaining (NL) input lines and the cells input from the L input lines are not connected to the output due to the contention control on the output line. And an output line that performs contention control on the cell.

The present invention provides a one-input / one-output space switch to two output lines connected to the same output buffer, as compared with the prior art described in Japanese Patent Application Laid-Open No. 10-51461 or Document 1. 1 composed of two cascaded connections
By devising a method of connecting the two outputs of the input two-output space switch to the two output lines, the input line can be connected to only one output line via the preceding one-input one-output space switch without being concentrated. The difference is that the input line is connected by being distributed to two output lines.

[0013] That is, the problem to be solved in the prior art is:
Since the input lines are concentrated only on the output line of the preceding one-input one-output spatial switch, even if the output line connected to the latter one-input one-output spatial switch is vacant, the former stage spatial switch can be used for contention control. This is a phenomenon in which the output is lost and the output is not connected. This is due to the fact that, despite having two output lines, the throughput tends to be biased toward one output line. Therefore, as compared with the prior art, in the present invention, the input line connected to the output line is distributed to two output lines connected through one space switch.

As a result, the throughput of the two output lines becomes more equal. As a result, the probability of losing cells due to contention control in the preceding one-input / one-output space switch is reduced, so that even when the number of input lines is small, the probability of occurrence of HOL blocking can be reduced. Switch can be realized.

Further, as the number L of one to less than M input lines out of the N input lines, an integer closest to a half of the number N of input lines can be selected as L. As a result, when the destination of the incoming cell is sufficiently random and a statistical multiplexing effect can be expected, the probability of losing a cell due to contention control can be minimized.

Further, in the one-input two-output spatial switch, a cell which is not connected to the output by the preceding one-input one-output spatial switch is delayed, and supplied to the input of the subsequent one-input one-output spatial switch. N delay circuits may be provided. Accordingly, when a cell that has not been output in the first conflict control is subjected to the second conflict control, a margin is provided by the delay circuit, so that the conflict control circuit can be configured as a pipeline, and the high frequency of the clock can be increased. Therefore, it is easy to increase the throughput.

Further, according to the delay times of the M × N delay circuits, the timing of cells transmitted from the input cell buffers connected to the L input lines and (N−
L) It is desirable to provide a time difference in the timing of cells transmitted from the input cell buffer connected to the input lines. As a result, the timing of cells input to the cross point of each spatial switch can be made the same for each output line, so that there is no need to adjust the timing of cell arrival during cell contention control.

The cells which are not connected to the output of the preceding one-input one-output space switch and which are not connected to the output of the subsequent one-input one-output space switch are also replaced with the preceding one-input one-output space switch. Means may be provided for coupling to the input of the switch. Thereby, the competition control can be performed again on the cell lost in the second competition control. Therefore, even if there is a cell lost in the contention control, cell transmission can be performed smoothly and with high throughput.

In addition, there are provided M × N delay circuits for giving a delay to a cell which is not connected to an output by the latter one-input one-output spatial switch and supplying the same to the input of the preceding one-input one-output spatial switch. Can also. Thus, when a cell that has not been output in the second conflict control is subjected to the third conflict control, a margin is provided by the delay circuit, so that the conflict control circuit can be configured in a pipelined manner, and the high frequency of the clock can be increased. Therefore, it is easy to increase the throughput.

It is particularly desirable to use a delay line as a delay circuit. This makes it possible to increase the speed of the operation clock as compared with the case where a delay circuit having a low operation speed such as a shift register or a cell buffer is used.

It is particularly desirable to use a delay line made of a superconductive material as the delay line. As a result, compared to the case where an optical fiber delay line or a delay line made of a normal conductor metal is used, a planar circuit and a thinner signal line can be realized, and the size can be reduced.

It is particularly desirable to use a high-temperature superconductor as the superconducting material. As a result, the operating temperature can be increased as compared with the case where other superconducting materials are used,
Cooling becomes easy.

[0023]

Embodiments of the present invention will be described in detail with reference to the drawings. In the embodiment of the present invention, the ATM switch is divided into four input lines IN1 to IN4 for convenience of explanation.
And 4 × 4 for exchanging four output lines OUT1 to OUT4
This will be described by taking the ATM switch as an example. FIG. 1 shows an overall configuration of an ATM switch according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the i-th input port unit in FIG. 1, and FIG. 3 is a one-input / two-output space switch 10ij.
FIG. 3 is a block diagram of the configuration of FIG.

Here, if i = 1 or 2, M = 1, N
= 2, and if i = 3 or 4, M = 2 and N = 1 take integers M and N. As shown in FIG. 3, an output line 5Mj is connected to a preceding one-input one-output spatial switch comprised of the first control circuit 14 and the selector 12 in the one-input two-output spatial switch 10ij. On the other hand, the second control circuit 1
An output line 5Nj is connected to a subsequent one-input one-output space switch composed of the selector 5 and the selector 13.

Therefore, the features of the ATM switch according to the present embodiment are as shown in FIG. 1 when the output lines 51j and 52j are i = 1 or 2 and i = 2.
Since the switching is performed in the case of 3 or 4, the 1-input 1-output space switch of the preceding stage connected to the output line 51j and the output line 52j is two in number. That is, in the prior art described in the above publication, the input line is concentrated only on the space switch connected to the output line 51j, but in the present embodiment, the output line 51j and the output line 52j
Four input lines are distributed and connected two by two through the input 1 output space switch.

A feature of the ATM switch according to the present embodiment is that, as shown in FIG. 3, a line 45 from which a cell lost by competitive control of the selector 12 of the preceding one-input one-output space switch is output. , A delay circuit 17 is provided,
The point is that the output is connected to the input of the selector 13 of the subsequent one-input one-output space switch.

A feature of the ATM switch according to the present embodiment is that, as shown in FIG. 3, a line 49 for outputting a cell lost due to contention control of the selector 13 of the subsequent one-input one-output space switch. , A delay circuit 16 is provided,
The output is connected to the input of the selector 12 of the preceding one-input one-output space switch.

Next, the operation of the ATM switch according to this embodiment will be described. In FIG. 1, the i-th input port 3
The cell arriving at 2i via the input line INi is written to the input cell buffer 21i. This input cell buffer 21i operates according to the FIFO rule. In the input cell buffer 21i, a read stop instruction from the line 31 in FIG. 2 (for example, when the level is H (high level))
As long as there is no cell, the cell is read and the cell is sent out via the line 53i. The line 53i transfers RB (routing bits) and data signals.

In FIGS. 2 and 3, Arb_ of line 56i
The m result signal becomes level H when there is a cell that has been lost in the competitive control in the one-input one-output space switch preceding the one-input two-output space switch 10ij. Arb on line 59i
The _n result signal goes to level H when there is a cell lost in the competitive control in the one-input one-output spatial switch subsequent to the one-input two-output spatial switch 10ij. In FIG. 2, when a cell is transferred on line 53i, only RB
Is taken out through. When the Arb_N result signal on the line 59i is at level H, no cell is transferred on the line 53i, and RB is transferred from the RB2 buffer 20 via the line 37. Therefore, the selector 31 does not transfer two RBs at the same time, and selects one of the RBs.

In FIG. 2, the RB signal on line 34 is stored in RB1 buffer 19 via line 38. As a result of the contention control performed by Arb_m, if the Arb_m result signal is L, the RB of the RB1 buffer 19 is discarded. If the Arb_m result signal is H, that is, if the contention control is lost, Rb is transferred from the RB1 buffer to the RB2 buffer.
B is transferred. Similarly, as a result of performing the conflict control in Arb_n, if the Arb_n result signal is L (low level), the RB of the RB2 buffer 20 is discarded. Also, if the Arb_n result signal is H, that is, if the contention control is lost, RB is sent from the RB2 buffer and sent to the selector 31 via the line 37.

The RB 'of the head cell of the input cell buffer 21i is extracted via the line 32. The RB of the line 34 is compared with the RB 'of the line 32. If they match, the level is high at the line 36, and if they do not match, the level is low. Both the level of the line 36 and the line 56i are H
Only in the case of, the level of the line 35 becomes H, the level of the read stop signal of the line 31 becomes H, and a read stop command is issued. When the level of the line 38 is H, cells that have lost contention control remain in the space switch shown in FIG.
In this case, when a new cell is sent through the line 53i, the cell order may be reversed. Therefore, in this embodiment, cell reading is stopped, and the cell order is guaranteed.

Referring to FIG. 3, one input 1 of the ATM switch will be described.
The operation of the output space switch 10ij will be described. The cell transferred to the input cell line 53i refers to the RB by the AF (address filter) 18 and
If the address coincides with the address ij, the cell is fetched via the line 43, passed through the delay circuit 21, and simultaneously issues a cell output request to the first control circuit 14 via the line 42. The first control circuit 14 performs contention control on the same output line 5Mj by a space switch that requests cell output. As a method of contention control, for example, there is a method using a ring arbiter in which space switches on the same output line are sequentially given output permission on the ring.

If the contention control is won (OK), the cell is sent to the output line 5Mj, and the Arb_m result signal on the line 56i is set to L. If the contention control loses (NG), the cell is sent to the delay circuit 17 via the line 45, and the Arb_m result signal on the line 56i is set to the level H (NG). Further, the first control circuit 14 notifies the second control circuit 15 that the cell has lost the competitive control (cell output request). The second control circuit 15, which has been notified of the cell output request, performs contention control on the same output line 5Nj by a space switch having a cell output request.

If the contention control is won (OK), the cell is sent to the output line 5Nj, and the Arb_n result signal on the line 59i is set to level L (OK). Lost in competition control (N
In the case of G), the cell is sent to the delay circuit 16 via the line 49, and the Arb_n result signal on the line 59i is set to the level H (NG). The second control circuit notifies the first control circuit 14 through the line 47 that the contention control has been lost (cell output request). First control circuit 1 receiving a cell output request
4 performs the same operation as when a cell output request is received via the line 42. Accordingly, the total delay time required for one round from the selector 12 to the line 45, the delay circuit 17, the selector 13, the line 49, the delay circuit 16, and the line 48 is made equal to the cell cycle.

Since the equivalent circuit of one input and one output is a circuit configuration in which cascade connection is performed, the time from the arrival of a cell at the selector 12 to the arrival of the cell at the selector 13 is 0.5 cell cycle. It is preferable for hardware implementation. As a result, it is desirable that the cell transmission timing of the input cell buffers 323 and 324 be delayed by 0.5 cell cycle compared to the cell transmission timing of the input cell buffers 321 and 322 from the input buffer.

According to the above operation, in the case of the present embodiment, for example, even when cells destined for the output cell buffer 253 are transmitted to the input lines 531 and 533, the cells transmitted to the input line 531 Space switch 1
013 to the output line 513. On the other hand, the cell transmitted to the input line 533 is a space switch 1033.
Through the output line 523. Therefore, the two cells are connected to the output buffer 25 without losing any contention control.
3 is output.

On the other hand, in the case of the conventional ATM switch, for example, both cells
3 and 1033 to output to the same output line 513, one of the cells is inevitably lost once due to contention control, and the line 561 or the line 563 is lost.
Becomes level H (NG), and the cell transmission stop command is notified to the input cell buffer 211 or 213. Therefore, cell transmission is interrupted, and the throughput of the ATM switch is reduced.

As described above, in the present embodiment, the two input lines are distributed to the output line 51j and the output line 52j, so that the throughput is biased to one of the output lines 51j and 52j. Has been prevented.
That is, in the conventional ATM switch, when the number of input lines is small, HOL blocking is likely to occur, and the throughput is reduced.

However, the ATM according to the present embodiment
In the switch, even when the number of input / output lines is small, since the throughput is prevented from being concentrated on only one of the two output lines, a decrease in the throughput of the ATM switch can be prevented. On the other hand, if the number of input / output lines is sufficiently large, there may be a case where three or more cells request output for one output line at the same time.

In such a case, the effective throughputs of the ATM switch according to the embodiment of the present invention and the conventional ATM switch are saturated and coincide with each other. Therefore, according to the embodiment of the present invention, it is possible to realize an ATM switch in which the throughput is hardly reduced due to HOL blocking even when the number of input / output lines is small. By using delay lines for the delay circuits 16, 17, and 21 in FIG. 3 without using a cell buffer or a shift register, the clock frequency is not limited by a cell buffer or a shift register having a maximum operating frequency of about 3 GHz. For example, it can be operated at a high clock frequency of about 10 GHz.

Also, by using a delay line made of a superconducting material having extremely small conductor loss,
Compared to using a three-dimensional circuit, an optical fiber delay line that requires optical-electrical / electrical-optical conversion, or a delay line made of a normal metal such as copper, the circuit is flattened and the signal line is thinned. The size can be reduced from one tenth to one hundredth.

The invention of claim 9 uses a high-temperature superconductor as the superconducting material. Examples of the high-temperature superconducting material include copper oxide superconductors such as Bi-based, Tl-based, Hg-based, Y-based, and Ag-based superconductors, all of which can be used. Some high-temperature superconductors have a temperature at which the transition to the superconducting state exceeds 100K. In such a superconductor, for example, the boiling point of liquid nitrogen at 1 atm.
Superconducting state can be obtained only by cooling to about 4K,
The cooling means can be configured to be small and inexpensive.

[0043]

As described above, according to the present invention, the input line connected to the output line is distributed to two output lines connected through one space switch. An ATM switch for improving the throughput without increasing the operation speed of the space switch relative to the input / output line speed, and particularly reducing the throughput due to HOL blocking even when the number of input / output lines is small. Can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an ATM switch according to an embodiment of the present invention.

FIG. 2 shows the AT according to the embodiment of the present invention shown in FIG.
FIG. 9 is a block diagram showing an i-th input port of the M switch.

FIG. 3 shows the AT according to the embodiment of the present invention shown in FIG.
1-input 2-output space switch 10i in M switch
The block diagram which shows the structure of j.

[Explanation of symbols]

11-13 Selector 14 First control circuit 15 Second control circuit 16, 17, 21 Delay circuit 18 Address filter 19 RB1 buffer 20 RB2 buffer 31-50 Line 211-214 Input cell buffer 251-254 Output cell buffer 321-324 Input Port section 511-514, 521-524 Output line 531-534 Input cell line 561-564 Arb_m result signal line 591-594 Arb_n result signal line 611-614, 621-624 Arb_m signal line,
Arb_n signal line 1011-1044 1 input 1 output space switch IN1 IN4 In line OUT1 OUT4 Out line

Claims (9)

(57) [Claims] 1. A 1-input 2-output space switch comprising N input cell buffers and M × N arrangement at the cross point between N input lines and M output lines, An ATM switch connected to the one-input two-output spatial switch through two output lines and comprising M output cell buffers for accumulating cells, wherein the one-input two-output spatial switch includes a destination of an incoming cell; It is configured by cascading two one-input one-output spatial switches that connect to their outputs according to information, and one of N input lines out of two output lines connected to the same cell buffer. A cell input from L input lines equal to or more than N and a cell not connected to the output by the other output line contention control among the cells input to the remaining (NL) input lines Contention control The output line to be performed, and the cells input from the remaining (NL) input lines and the cells input from the L input lines which are not connected to the output due to contention control on the output line. An ATM switch having an output line for performing contention control on the ATM switch. 2. The method according to claim 1, wherein an integer closest to a half of the number N of input lines is selected as L as the number L of one or more and less than M of the N input lines. 1
The ATM switch according to 1. 3. In the one-input two-output spatial switch, a cell which is not connected to the output by the preceding one-input one-output spatial switch is delayed and supplied to the input of the subsequent one-input one-output spatial switch. 3. A circuit according to claim 1, wherein said circuit has N delay circuits.
TM switch. 4. The timing of cells transmitted from an input cell buffer connected to the L input lines and the (N−L) inputs according to delay times of the M × N delay circuits. 4. The ATM switch according to claim 3, wherein a time difference is provided in the timing of cells transmitted from the input cell buffer connected to the line. 5. A cell which is not connected to its output in the preceding one-input one-output spatial switch and is not connected to its output in the subsequent one-input one-output spatial switch as well. 5. The ATM switch according to claim 1, further comprising means for coupling to an input of the space switch. 6. An M × N delay circuit for providing a delay to a cell not connected to an output by the latter one-input one-output spatial switch and supplying the same to an input of a preceding one-input one-output spatial switch. The ATM according to claim 5, wherein:
switch. 7. The A according to claim 3, wherein a delay line is used as the delay circuit.
TM switch. 8. The A according to claim 7, wherein a delay line made of a superconducting material is used as the delay line.
TM switch. 9. The ATM switch according to claim 8, wherein a high-temperature superconductor is used as the superconducting material.