JP2864765B2 - Data carrier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data carrier used for an article identification system such as a tool of a machine tool, a component or a product in a factory, or a distribution system.

[0002]

2. Description of the Related Art Conventionally, in order to mechanize the management of tools of machine tools and the identification of parts and products on an assembly and transfer line in a factory, a system for identifying and managing various articles such as tools, parts and products has been developed. Required. Therefore, a data carrier having a memory is provided in the object to be identified as disclosed in Japanese Patent Application Laid-Open No. 1-151832, necessary information is written into the memory of the data carrier by external data transmission, and the information is read as necessary. An article identification system configured as described above has been proposed.

As shown in FIG. 6, such a data carrier has a resonance circuit 31 connected to a coil for reception, a signal obtained by the resonance circuit is shaped by a waveform shaping circuit 32, and is constituted by a gate array, a CPU and the like. Data is written to the memory 34 via the memory control unit 33 to be read, or data is read out based on a given command, and the vibration is absorbed by the vibration absorbing circuit 35 to transmit the data. I have.

[0004]

However, such a conventional data carrier is configured so that a memory having a relatively large capacity can be mounted. Therefore, there is a disadvantage that a memory control unit constituted by a gate array, a CPU, and the like becomes complicated, and the cost cannot be reduced because a memory having a large capacity is used. Therefore, there is a disadvantage that such a large-capacity memory is not required and is not suitable when a small capacity, for example, a memory capacity of several bits to several tens of bits is sufficient.

The present invention has been made in view of such a problem of the conventional data carrier, and holds a small amount of data with an extremely simple configuration suitable for reducing the size of a conventional data carrier. It is a technical object to write data or reset the data using the control unit as it is so that new data can be written or read.

[0006]

According to the present invention, there is provided a resonance circuit for receiving a PWM signal having a different duty ratio in a transmission mode in response to write data including a start bit or a clear command and having a constant duty ratio in a reception mode; A waveform shaping circuit for smoothing a received output obtained by the resonance circuit and shaping the waveform; and a shift register for receiving a signal obtained from the waveform shaping circuit as a shift pulse and circulating and holding write data obtained from the waveform shaping circuit. Signal switching means for switching the input supplied to the shift register by the output of the shift register from the output of the waveform shaping circuit to the output of the shift register, and detecting a clear command obtained from the waveform shaping circuit, and resetting the shift register upon detection. A clear signal detector and a signal with a constant duty ratio It is characterized in that it comprises a vibration absorbing circuit for controlling reverberations of the resonant circuit based on the read-out signal from the shift register when.

[0007]

According to the present invention having the above features, signals having different duty ratios are given at the time of writing data on a data carrier or sending a clear command, and the signals are received by a resonance circuit and shaped by a waveform shaping circuit. . Then, a shift pulse is supplied from the signal to the shift register, and is written into the shift register as a write signal. When the signal is output from the shift register, the input of the shift register is switched by the signal switching means to prohibit the subsequent writing of the signal and the data is circulated in the shift register. When data is read, a signal read from the shift register is supplied to a vibration absorbing circuit based on the shift pulse, and the vibration is absorbed to transmit data to the outside. When a clear command is transmitted after writing data, the clear signal detector detects the command and resets the shift register so that new data can be written again.

[0008]

FIG. 1 is a block diagram showing an overall configuration of a data carrier according to one embodiment of the present invention, and FIG. 2 is a block diagram showing a configuration of a clear signal detecting section. In these figures, the data carrier is a receiving coil L and a capacitor C.
And a PWM modulating signal supplied from the outside to the waveform shaping circuit 2. The waveform shaping circuit 2 performs envelope detection on the applied signal and discriminates the signal at a predetermined level to obtain a received signal corresponding to the intermittent signal, and the output is a multiplexer (MPX).
3 and one input terminal (Y ₀ ) and monostable multivibrators (MM) 4, 5. The monostable multivibrator 4 generates a clock signal having a duty ratio of 40% as described later based on the received signal provided, and the monostable multivibrator 5 has a duty ratio of 50% as described later based on the received signal. The clock signal is generated. The output of the monostable multivibrator 4 is given as a shift pulse to the shift register 6 and the shift register 8 of the clear signal detector 7. The shift register 6 is composed of, for example, 8 bits. The output of the multiplexer 3 is provided to a data input terminal (IN), and the output of the data output terminal (OUT) is a flip-flop (FF).
9 and the input terminal of the AND circuit 10 and the other input terminal (Y ₁ ) of the multiplexer 3. Also provided is a clear signal source 11 composed of a resistor and a capacitor connected in series to the power supply, and an inverter connected to the midpoint between the resistor and the capacitor. One end of the clear signal source 11 is connected to the clear signal detector 7, and supplies a clear signal to the clear input terminal of the shift register 6, the flip-flop 9, and the clear signal detector 7. The flip-flop 9 switches the input of the multiplexer 3 and the input of the multiplexer 12 of the clear signal detector 7 according to the Q output. The multiplexer 3 outputs the output (Y ₀ ) of the waveform shaping circuit 2 when the Q output is at the L level, and shifts the shift register 6 when the Q output is at the H level.
Providing data out input of (Y ₁₎ on the input side of the shift register 6 (IN). When the Q output of the flip-flop 9 is at the L level, the input to the shift register 8 is always at the L level, and when the Q output is at the H level, the output of the waveform shaping circuit 2 is the input of the shift register 8. Here, the multiplexer 3 and the flip-flop 9 constitute signal switching means 13 for switching an input signal to the shift register 6.

The shift register 8 of the clear signal detecting section 7 has a bit number of の of the shift register 6, that is, 4 in this embodiment.
A bit shift register, each bit of which is provided to a digital comparator 14. When the parallel signal of the shift register 8 is a data string of a predetermined clear command, for example, “0011”, the comparator 14 detects the data string and gives it to the shunt circuit 15. The shunt circuit 15 clears each part by grounding the output terminal of the clear signal source 11. The output of the monostable multivibrator 5 is supplied to an AND circuit 10. The AND circuit 10 gives the logical product of the input signals to the monostable multivibrator 16. The monostable multivibrator 16 operates for a short time in accordance with the data read from the shift register 6, and its output is provided to the vibration absorbing circuit 17. The vibration absorbing circuit 17 stops reverberation of a received signal by closing a switching element that grounds both ends of the resonance circuit 1 when an H-level signal is given. This data carrier has a backup battery 18 for holding data of the shift register 6.
Is installed.

Here, when writing data to the data carrier, the shift register 6 and the flip-flop 9 are reset using the clear signal source 11, and thereafter, a signal having a different duty ratio is received at a constant cycle for receiving the data carrier. This is performed by sending out to the coil L. The configuration of the write / read control unit for such a data carrier is the same as that shown in the above-mentioned conventional example.

Next, the operation of this embodiment will be described with reference to the waveform diagrams of FIGS. In these figures, (a)
1 to (k) show waveforms a to k in FIG. First, when power is turned on before writing data, the shift register 6 and the flip-flop 9 are reset by the clear signal source 11. A constant period T with a duty ratio corresponding to data to be written from a write / read control unit (not shown)
Input a waveform in which the signal is intermittent. For example, a logic “1” has a duty ratio of 70%, and a logic “0” has a duty ratio of 70%.
A signal of 30% is output as shown in FIG. Then, the signal is received by the resonance circuit 1, the envelope is detected by the waveform shaping circuit 2, and the signal is discriminated at a predetermined level to obtain a signal as shown in FIG. 3 (c). This signal is supplied to the monostable multivibrator 4, and is supplied to the shift register 6 as a signal having a duty ratio of 40% for dividing the period T into four to six as shown in FIG. Since the flip-flop 9 is reset at first, the output of the waveform shaping circuit 2 is directly written into the shift register 6 via the multiplexer 3.

Since the shift register 6 has an 8-bit structure, the output of the data output terminal of the shift register 6 becomes H level when 8-bit data is written as shown in FIG. Become. Therefore, the flip-flop 9 is inverted as shown in FIG. 3 (f), and thereafter the output of the shift register 6 becomes the input of the shift register 6 via the multiplexer 3 as it is. Therefore, even if the data is transmitted, the data is not overwritten and the data in the shift register 6 circulates, and the data is held in the shift register 6. Here, in order to change the shift register 6 from the write mode to the cyclic mode, it is necessary to set the data (start bit) to be written first to "1". FIG.
After the signal is written into the shift register 4 as shown in FIG.

Next, data reading will be described with reference to the waveform diagram of FIG. When reading data from the data carrier, the write / read control unit has a constant duty ratio, for example, 50%, in the same cycle as the data write cycle.
The signal of is output. Then, the signal is shaped through the resonance circuit 1 and the waveform shaping circuit 2, and the waveform is shaped by the waveform shaping circuit 2. Accordingly, a signal having a duty ratio of 40% is output from the monostable multivibrator 4 as shown in FIG. 4D, and this signal is given to the shift register 6 as a shift pulse. Accordingly, the held NRZ data "11010001" is read from the shift register 6 as shown in FIG. At this time, a signal having a duty ratio of 50% is given to the AND circuit 10 by the monostable multivibrator 5 in synchronization with the output of the waveform shaping circuit 2 as shown in FIG. Accordingly, the AND signal shown in FIG. 4 (i) is output from the AND circuit 10 and applied to the monostable multivibrator 16. The monostable multivibrator 16 generates a vibration absorption control signal and supplies it to the vibration absorption circuit 17 as shown in FIG. The vibration absorbing circuit 17 closes switching elements connected to both ends of the resonance circuit 1. This pulse stops the reverberation of the resonance as shown in FIG. Therefore, a reverberation signal is received by the receiving unit of the read / write head (not shown), and data can be received by demodulating this signal.

Now, as shown in FIG. 5B, the read / write head issues a clear command with a duty ratio of 70% or 30%.
When a 4-bit signal consisting of%, for example, "0011" is transmitted, the signal is transmitted to the shift register 8 at the same time. When this signal is detected by the comparator 14, a detection signal of a clear command is given to the shunt circuit 15. In the shunt circuit 15, FIG.
As shown in the figure, the output terminal of the clear signal source 11 is grounded for a certain time. Therefore, the clear operation is performed again, and the data in the shift register 6 is cleared. Thereafter, by sending new data from the read / write head side, another data can be written to the data carrier as described above.

In this embodiment, two monostable multivibrators 4 and 5 for generating signals having different duty ratios are used. If the monostable multivibrator 5 having a duty ratio of 50% is used for the shift pulse of the shift register 6, the data may be accidentally coincident with the clear command at the time of data reading. In this case, the data is erased. I will. Therefore, it is necessary to prevent such a situation. Therefore, the monostable multivibrator 4 having a duty ratio of 40% is used for reading data, and the monostable multivibrator 5 having a duty ratio of 50% is used.
Is used to generate a vibration absorption pulse, thereby preventing data erasure and performing vibration absorption in response to a signal from a read / write head.

In this embodiment, the shift register of the data carrier has an 8-bit configuration, but it goes without saying that the present invention can be applied to other configurations. The clear signal can be detected by using a shift register having a bit number corresponding to the clear signal and a comparator as the shift register for detecting the clear signal.

[0017]

As described in detail above, according to the present invention, a shift register is used as a memory of a data carrier. Therefore, once data is written, it is held as it is, and thereafter, data can be repeatedly read by applying a signal having a predetermined duty ratio from the outside. By transmitting a clear command from the read / write head side, data in the data carrier can be erased and new data can be written. Therefore, there is obtained an effect that a data carrier having a wide versatility and capable of writing and erasing data of a small capacity with an extremely simple configuration can be formed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a data carrier according to one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a data carrier clear signal detection unit according to the embodiment;

FIG. 3 is a waveform chart showing waveforms of various parts at the time of data writing.

FIG. 4 is a waveform diagram showing waveforms of respective units when data is read.

FIG. 5 is a waveform diagram showing waveforms of respective units when data on a data carrier is cleared.

FIG. 6 is a block diagram illustrating an example of a conventional data carrier.

[Explanation of symbols]

 Reference Signs List 1 resonance circuit 2 waveform shaping circuit 3, 12 multiplexer 4, 5, 16 monostable multivibrator 6, 8 shift register 7 clear signal detection unit 9 flip-flop 10 signal switching means 11 clear signal source 14 comparator 15 shunt circuit 17 vibration absorbing circuit

Claims (1)

(57) [Claims] 1. In a transmission mode, a duty ratio is different in accordance with write data including a start bit or a clear command, and in a reception mode, a PWM having a constant duty ratio is provided.
A resonance circuit that receives a signal, a waveform shaping circuit that smoothes a received output obtained by the resonance circuit to shape the waveform, and a signal obtained by the waveform shaping circuit is given as a shift pulse, and is obtained by the waveform shaping circuit. A shift register for circulating and holding write data, signal switching means for switching an input given to the shift register by an output of the shift register from an output of the waveform shaping circuit to an output of the shift register, A clear signal detection unit that detects the obtained clear command and resets the shift register upon detection, and performs the resonance based on a signal read from the shift register when a signal having a constant duty ratio is given in a reception mode. And a vibration absorption circuit for controlling reverberation of the circuit. .