JP2864766B2 - Data carrier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data carrier used for an article identification system such as a tool of a machine tool, a component or a product in a factory, or a distribution system.

[0002]

2. Description of the Related Art Conventionally, in order to mechanize the management of tools of machine tools and the identification of parts and products on an assembly and transfer line in a factory, a system for identifying and managing various articles such as tools, parts and products has been developed. Required. Therefore, a data carrier having a memory is provided in the object to be identified as disclosed in Japanese Patent Application Laid-Open No. 1-151832, necessary information is written into the memory of the data carrier by external data transmission, and the information is read as necessary. An article identification system configured as described above has been proposed.

In such a data carrier, a resonance circuit 31 is connected to a coil for reception as shown in FIG. 4, a signal obtained by the resonance circuit 31 is shaped by a waveform shaping circuit 32, and the data is shaped by a gate array or a CPU. Data is written to the large-capacity memory 34 via the configured memory control unit 33, or data is read out based on a given command, and data is sent out by the vibration absorbing circuit 35 absorbing the vibration of the resonance circuit 31. I am trying to do it.

[0004]

However, such a conventional data carrier is configured so that a memory having a relatively large capacity can be mounted. Therefore, there is a disadvantage that a memory control unit constituted by a gate array, a CPU, and the like becomes complicated, and the cost cannot be reduced because a memory having a large capacity is used. Therefore, there is a disadvantage that such a large-capacity memory is not required and is not suitable when a small capacity, for example, a memory capacity of several bits to several tens of bits is sufficient.

The present invention has been made in view of such a problem of the conventional data carrier, and holds a small amount of data with an extremely simple configuration suitable for reducing the size of a conventional data carrier. It is a technical object to enable data to be written and read using the control unit as it is.

[0006]

According to the present invention, in the transmission mode, the duty ratio differs according to the write data including the start bit, and in the reception mode, the duty ratio is constant.
A resonance circuit for receiving the WM signal, a waveform shaping circuit for smoothing the received output obtained by the resonance circuit and shaping the waveform, and a signal obtained from the waveform shaping circuit being given as a shift pulse and being written by the waveform shaping circuit A shift register that circulates and holds data, signal switching means for switching an input supplied to the shift register by an output of the shift register from an output of the waveform shaping circuit to an output of the shift register, and counting the same number of bits as the shift register A counter for inverting the output, read data selecting means for selecting a shaped pulse obtained from the waveform shaping circuit and an output of the shift register based on the output of the counter, and when a signal having a constant duty ratio is given in the reception mode. Vibration for controlling reverberation of the resonance circuit based on a signal read by the read data selection means And Osamu circuit, is characterized in that it has a.

[0007]

According to the present invention having the above-mentioned features, signals having different duty ratios are given at the time of writing data to the data carrier, and the signals are received by the resonance circuit and shaped by the waveform shaping circuit. Then, a shift pulse is supplied from the signal to the shift register, and is written into the shift register as a write signal. And when that signal is output from the shift register,
By switching the input of the shift register by the signal switching means, the subsequent writing of the signal is prohibited, and the data is circulated in the shift register. When data is read, the shift pulse is counted by a counter, and when the same number of bits as the number of bits of the shift register are counted, the output of the shift register and the clock pulse are alternately selected by the read data selecting means and supplied to the vibration absorbing circuit. The data transmission is performed to the outside by absorbing the vibration.

[0008]

FIG. 1 is a block diagram showing the configuration of a data carrier according to one embodiment of the present invention. In this figure, the data carrier has a resonance circuit 1 including a receiving coil L and a capacitor C, and supplies a PWM modulation signal supplied from the outside to a waveform shaping circuit 2. Waveform shaping circuit 2
Obtains a received signal corresponding to the intermittent signal by detecting the given signal by envelope detection and discriminating the signal at a predetermined level. The output of the signal is one input terminal (Y ₀ ) of the multiplexer (MPX) 3 and Monostable multivibrator (MM) 4
Given to. The monostable multivibrator 4 delays the received signal by a half period, and its output is supplied to the shift register 5 as a shift pulse. The shift register 5 is composed of, for example, 8 bits. The output of the multiplexer 3 is provided to a data input terminal (IN). The output of the data output terminal (OUT) is connected to a set input terminal of a flip-flop (FF) 6 and an AND circuit. 7 and the other input terminal (Y ₁ ) of the multiplexer 3.
Also provided is a clear signal source 8 comprising a resistor and a capacitor connected in series to the power supply, and an inverter connected to the midpoint between the resistor and the capacitor. The clear signal source 8 supplies a clear signal which becomes H level after power-on and becomes L level after a predetermined time delay, to the clear input terminal of the shift register 5 and the reset input terminal of the flip-flop 6. Flip-flop 6
Switches the input of the multiplexer 3 according to the Q output. When the Q output is at L level, the output (Y ₀ ) of the waveform shaping circuit 2 is shifted. When the Q output is at H level, the data out input (Y ₁ ) of the shift register 5 is shifted. It is given to the input side (IN) of the register 5. Here, the multiplexer 3 and the flip-flop 6 constitute signal switching means 9 for switching an input signal to the shift register 5.

The output of the monostable multivibrator 4 is also supplied to an AND circuit 7 and a counter 10. The counter 10 counts output pulses of the monostable multivibrator 4 which are cleared by the clear signal source 8,
In this embodiment, the counter inverts the output with the same number of bits as the shift register 5, that is, 8 bits in this embodiment. The output of the counter 10 is provided to the AND circuits 7 and 11. The AND circuits 7 and 11 supply the respective AND signals to the monostable multivibrator 13 via the OR circuit 12. The monostable multivibrator 13 is a shift register 5
The operation is performed for a short time in response to the data and clock pulse read out from the memory, and the output is applied to the AND circuit 14.
The Q output of the flip-flop 6 is also applied to the other input terminal of the AND circuit 14, and the AND signal thereof is applied to the vibration absorbing circuit 15. Here, the AND circuits 7, 11,
The OR circuit 12 constitutes read data selection means 16 for selecting a shaped pulse of the waveform shaping circuit 2 and an output pulse from the shift register 5. The vibration absorbing circuit 15 stops the reverberation of the received signal by closing a switching element that grounds both ends of the resonance circuit 1 when an H-level signal is given. A backup battery 17 for holding data of the shift register 5 is attached to the data carrier.

Here, when writing data to the data carrier, the shift register 5 and the flip-flop 6 are reset by using the clear signal source 8, and thereafter, a signal having a different duty ratio is received at a constant cycle for receiving the data carrier. Coil L
By sending it to The configuration of the write / read control unit for such a data carrier is the same as that shown in the above-mentioned conventional example.

Next, the operation of this embodiment will be described with reference to the waveform diagrams of FIGS. In these figures, (a)
1 to (k) show waveforms a to k in FIG. First, when the power is turned on before data writing, the shift register 5, flip-flop 6, monostable multivibrator 4, and counter 10 are reset by the clear signal source 8. Then, a non-illustrated write / read control unit inputs a waveform in which a signal having a constant period T is intermittent at a duty ratio corresponding to data to be written. For example, a signal having a duty ratio of 70% for logic "1" and a signal having a duty ratio of 30% for logic "0" is output as shown in FIG. Then, the signal is received by the resonance circuit 1,
A signal as shown in FIG. 2 (c) is obtained by performing envelope detection by the waveform shaping circuit 2 and discriminating at a predetermined level. This signal is supplied to the monostable multivibrator 4, and as shown in FIG. 2D, the signal is supplied to the shift register 5 as a signal having a duty ratio of about 50% delayed by 1/2 cycle from the rising point. Since the flip-flop 6 is reset at first, the output of the waveform shaping circuit 2 is written to the shift register 5 via the multiplexer 3 as it is. Since the flip-flop 6 has been reset, no signal is transmitted from the monostable multivibrator 13 to the vibration absorbing circuit 15.

Since the shift register 5 has an 8-bit configuration, the output of the data output terminal of the shift register 5 becomes H level when 8-bit data is written as shown in FIG. Become. Therefore, the flip-flop 6 is inverted as shown in FIG. 2 (f), and thereafter, the output of the shift register 5 becomes the input of the shift register 5 via the multiplexer 3 as it is. Therefore, even if the data is transmitted, the data is not overwritten and the data in the shift register 5 circulates, and the data is held in the shift register 5. Here, in order to change the shift register 5 from the write mode to the cyclic mode, it is necessary to set the data (start bit) to be written first to "1". Thus, FIG.
After the signal is written to the shift register 5 as shown in FIG.

Next, data reading will be described with reference to the waveform diagram of FIG. When reading data from the data carrier, the write / read control unit has a constant duty ratio, for example, 50%, in the same cycle as the data write cycle.
The signal of is output. Then, the signal is shaped through the resonance circuit 1 and the waveform shaping circuit 2. Therefore, the signal shown in FIG. 3D is output from the monostable multivibrator 4,
This signal is supplied to the shift register 5, AND circuit 7, and counter 10 as a clock pulse. Therefore, a signal corresponding to the shift pulse is output from the shift register 5 in FIG.
Reading is performed as shown in (g). As shown in FIG. 3 (h), a signal which repeats H and L levels every time 8 bits are read is obtained from the 8-bit counter 10.
Then, while the counter 10 is at the H level, the AND circuit 7 performs a logical product of this clock and the output read from the shift register 5 to output the NRZ signal “10110011” as shown in FIGS. Is output to the monostable multivibrator 13 via the OR circuit 12. Accordingly, the monostable multivibrator 13 outputs a signal as shown in FIG. Monostable multivibrator 1
In 3, a vibration absorption control signal is generated and supplied to the vibration absorption circuit 15 when the input pulse falls for a short period of time equal to or less than a half cycle. The vibration absorbing circuit 15 closes switching elements connected to both ends of the resonance circuit 1. This pulse stops the amplitude of the resonance as shown in FIG. 3 (b). Therefore, a signal as shown in FIG. 3 (m) is received by the receiving section of the read / write head (not shown), and data can be received by demodulating this signal.

When the 8-bit counter 10 goes low, the output of the shift register 5 is inhibited from being read out by the AND circuit 7 and the output of the shift register 5 is not read. ), The clock signal is read as it is. Therefore, a clock pulse is applied to the monostable multivibrator 13 via the OR circuit 12 as shown in FIG. 3 (k), and a vibration absorbing pulse as shown in FIG. 3 (l) is applied to the resonance circuit 1. Accordingly, during this time, the reception of the read / write head is always 0. When the counter 10 becomes H level again, the data is sequentially read following the start bit 1 read from the shift register 5, and a vibration absorption pulse is generated via the AND circuit 7. Reverberation is prohibited during the period when this pulse is given, as shown in FIG. Therefore, as shown in FIG. 3 (b), both ends of the resonance circuit 1 have reverberation at a fixed duty ratio when the logic signal is H, and a signal without reverberation is obtained when the logic signal is 0. Since this signal is similarly detected on the read / write head side (not shown), the read / write head operates based on the presence or absence of reverberation as shown in FIG.
As shown in (h) and (i), the signal written in the shift register 5 can be read. In this case, the first bit of the shift register is used as a start bit (ST),
The other part can store data as data bits (here, 7 bits). Also, even when data reading is stopped halfway, a frame identification bit is used so that the start position of data can be accurately grasped in the next reading. By reading out the frame identification bits by the number of bits using the same number of bits as the shift register, the data portion can be clearly recognized.

In this embodiment, the shift register of the data carrier has an 8-bit configuration, but it goes without saying that the present invention can be applied to other configurations. For example, when a 16-bit shift register is used, the counter is also a hexadecimal counter that is inverted every time it counts 16 bits.

[0016]

As described in detail above, according to the present invention, a shift register is used as a memory of a data carrier. Therefore, once data is written, it is held as it is, and thereafter, data can be repeatedly read by applying a signal having a predetermined duty ratio from the outside. Even if the reading is stopped halfway, the written data can be reliably read from the start bit after the end of the frame identification bit in the next reading. Therefore, an effect that a small-capacity data carrier can be configured with an extremely simple configuration is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data carrier according to an embodiment of the present invention.

FIG. 2 is a waveform chart showing waveforms of respective units at the time of data writing.

FIG. 3 is a waveform chart showing waveforms of respective units at the time of data reading.

FIG. 4 is a block diagram showing an example of a conventional data carrier.

[Explanation of symbols]

 Reference Signs List 1 resonance circuit 2 waveform shaping circuit 3 multiplexer 4, 13 monostable multivibrator 5 shift register 6 flip-flop 7, 11, 14 AND circuit 9 signal switching means 10 counter 15 vibration absorbing circuit 16 read data selection means

Claims (1)

(57) [Claims] In a transmission mode, a duty ratio differs according to write data including a start bit, and in a reception mode, a resonance circuit for receiving a PWM signal having a constant duty ratio and a reception output obtained by the resonance circuit are smoothed. A waveform shaping circuit for performing waveform shaping, a signal obtained from the waveform shaping circuit is provided as a shift pulse, and a shift register for circulating and holding write data obtained from the waveform shaping circuit; and an output of the shift register. Signal switching means for switching the input supplied to the shift register from the output of the waveform shaping circuit to the output of the shift register; a counter for inverting the output when the same number of bits as the shift register is counted; The shaped pulse obtained from the circuit and the output of the shift register are output to the output of the counter. Therefore, a read data selecting means to select, and a vibration absorbing circuit for controlling reverberation of the resonance circuit based on a signal read by the read data selecting means when a signal having a constant duty ratio is given in a reception mode, A data carrier comprising: