JP2867553B2 - Packet transfer device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet transfer device, and more particularly, to a packet transfer device that shortens the processing time of an external loopback test of a packet bus.

[Prior Art] In a conventional external loopback test of a packet bus of this type, first, an external loopback requesting packet transfer device issues a bus capture request to a bus arbiter to acquire a transmission right to the bus. Thereafter, an instruction to return the return data is given to the external return request destination packet transfer device, and the bus is released (the right to use the bus is released).

Upon receiving the external return instruction packet, the external return request destination packet transfer device sets the return data to the external return request by software processing or hardware processing, makes a transmission request to the bus arbiter, and obtains the bus transmission right. Later, the return data is transmitted to the external return requesting packet transfer device.

The external return request source packet transfer device receives this return data and compares it with the transmitted return data by software processing.

In the conventional packet transfer apparatus, the external loopback test of the packet bus was performed in this manner.

[Problems to be Solved by the Invention] However, in an external loopback test of a packet bus of a conventional packet transfer apparatus, an external loopback request packet and
When transmitting an external return response packet as a response to the external return instruction, each packet transfer device always issues a bus capture request to the bus arbiter when transferring packet data, thereby acquiring the transmission right. , The time required from the external return request to the reception of the external return response is long and not constant depending on the traffic state of the bus.

For this reason, there is a problem that real-time performance is lost in the test of the packet transfer device connected to the bus and the test of the packet bus.

In addition, since the reception loopback data is read and the data is compared, when the software processing is performed, there is a problem that the processing time of the external loopback test becomes long.

[Means for Solving the Problems] The present invention has been made in view of the above problems, and has as its object to reduce the processing time of an external loopback test of a packet bus. Return instruction means for returning the test data transmitted to another packet transfer apparatus; and a bus arbiter for transmitting the return data by the source packet transfer apparatus until receiving the return data transmitted from the destination packet transfer apparatus. Means for holding a transmission request for, a source address and return data extracted from the received return instruction packet, and means for transmitting return data to the source packet transfer device;
A comparison means for comparing the received return data with the transmitted return data is provided.

Preferably, the means for transmitting the return data includes:
The return data is transmitted to the source packet transfer device without making a transmission request to the bus arbiter.

Further, it is preferable that storage means for storing the comparison result of the comparison means is provided.

[Operation] In the packet transfer device having the above configuration, since the means for holding the transmission request of the external return request source captures the bus, the transmission right is transmitted every packet transfer to transfer the external return request and the external return response. There is no need to win.

Therefore, a response to the external loopback instruction can be received without depending on the traffic on the bus, and the time required to confirm the normality of the bus and the validity of the transfer control between the packet transfer devices is reduced and becomes substantially constant. .

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing a configuration for performing packet data transfer using the packet transfer device according to the present invention. In FIG. 2, for clarity of explanation, a description will be given of a minimum-scale configuration for performing data transfer between the packet transfer device 11 and the packet transfer device 12.

In FIG. 2, a packet transfer device 11 and a packet transfer device 12 are connected to a bus arbiter 13 by an arbiter bus 14. The bus arbiter 13 arbitrates a transfer request from each packet transfer device 11 or 12 to give a transmission right. The packet transfer device 11 or the packet transfer device 12 that has obtained the transmission right transmits the packet transfer device 11 or the packet transfer device 12
Data transfer.

FIG. 3 shows a sequence of an external loopback test from the packet transfer apparatus 11 to the packet transfer apparatus 12 shown in FIG.

The packet transfer device 11 issues a transmission request to the bus arbiter 13, and the packet transfer device 11
Transmits the external return request bucket to the packet transfer device 12. The packet transfer device 11 does not release the transmission right until receiving the external return instruction response packet from the packet transfer device 12.

Packet transfer device that has received an external loopback request packet
12 extracts the source address and return data from the external return request packet by hardware processing and assembles an external return instruction response packet. After assembling the external return instruction response packet, the packet is returned to the packet transfer device 11 that is the external return request source without making a transmission request to the bus arbiter 13.

The packet transfer device 11 that is the external return request source receives the external return data, stores
The transmission request to 13 is stopped and the packet bus 15 is released.
The transfer response shown in FIG. 3 is a control signal for notifying that the transfer of one packet is normal.

An example of the packet transfer device 11 and the packet transfer device 12 which perform this transfer control and compare the transmission return data and the reception return data by hardware will be described below.

FIG. 1 is a block diagram showing one embodiment of a packet transfer device according to the present invention.

In FIG. 1, the transmission / reception control circuit 303 obtains the right to use the packet bus 15 from the bus arbiter 13 via the arbiter bus 14, and then transmits the packet to the designated packet transfer apparatus 11 (or the packet transfer apparatus 12) as an external return instruction request packet. Then, the set data is transmitted to the transmission return data storage register 304. With the packet bus 15 captured, the request source packet transfer device 11 (or the packet transfer device 1
The received data from 2) is received, only the return data is extracted by the transmission / reception control circuit 303, and stored in the reception return data storage register 305 as the reception return data set signal 310.

At this time, the data notified as the transmission return data signal 308 from the transmission return data storage register 304 and the reception return data 3 from the reception return data storage register 305.
The data notified as 09 is compared with the comparison circuit 306,
The comparison result of the match or mismatch is stored in the comparison result storage register 307 from the transmission / reception control circuit 303 as the comparison result set signal 311.

Therefore, the packet bus 15 is normal only by reading the comparison result storage register 307, and the packet transfer device 12 (or the packet transfer device
It can be confirmed that the transfer operation between 11) is normal.

According to the above embodiment, when the external return request packet and the external return response packet are transmitted during the external return transfer control, the external return request is transferred in a situation where the external return request source is capturing the bus. Since the transmission right is not acquired for each packet transfer, a response to the external return instruction can be received without being present in the traffic of the bus.
For this reason, the time required to confirm the normality of the bus and the validity of the transfer control between the packet transfer devices is reduced and substantially constant.

Also, when performing bus capture for each packet transfer, since the external return response is not always a request packet received in the order of requests, the address of the external return source must be confirmed by software processing.
The external loopback response packet can be received while the packet transfer device of the external loopback requester is capturing the packet bus, and the transmitted loopback data and the received loopback data can be compared by hardware processing, reducing the burden of software processing. Can be reduced.

[Effects of the Invention] As described above, according to the present invention, return instruction means for returning test data transmitted to another packet transfer apparatus, and return data transmitted from a destination packet transfer apparatus are received. Until the source packet transfer device holds the transmission request to the bus arbiter for transmitting the return data, and extracts the source address and the return data from the received return instruction packet and returns the return data to the source packet transfer device. , And comparing means for comparing the received return data with the transmitted return data.

With this configuration, since the means for holding the transmission request of the external return request source captures the bus, it is necessary to acquire the transmission right for each packet transfer to transfer the external return request and the external return response. There is no.

Therefore, a response to an external loopback instruction can be received without depending on the traffic on the bus, and the time required to confirm the normality of the bus and the validity of the transfer control between the packet transfer devices is reduced, and is substantially constant. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a packet transfer device according to the present invention, FIG. 2 is a block diagram showing a configuration when packet data transfer is performed using the packet transfer device according to the present invention, FIG. Is a sequence of the external loopback test between the packet transfer devices shown in FIG. 11 Packet transfer device 12 Packet transfer device 13 Bus arbiter 14 Arbiter bus 15 Packet bus 303 Transmission / reception control circuit 304 Transmission return data storage register 305… Reception return data storage register 306 Comparison circuit 307: comparison result storage register 308: transmission return data signal 309: reception return data 310: reception return data set signal 311: comparison result set signal

Claims (3)

(57) [Claims] 1. A return instruction means for returning test data transmitted to another packet transfer apparatus, and a source packet transfer apparatus transmits return data until return data transmitted from a destination packet transfer apparatus is received. Means for holding a transmission request to the bus arbiter for transmission, means for extracting the source address and return data from the received return instruction packet, and transmitting the return data to the source packet transfer device; A packet transfer device comprising: comparing means for comparing the transmitted return data. 2. The packet transfer device according to claim 1, wherein the means for transmitting the return data transmits the return data to the source packet transfer device without making a transmission request to the bus arbiter. 3. The packet transfer device according to claim 1, further comprising storage means for storing a comparison result of said comparison means.