JP2869982B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2869982B2 JP2869982B2 JP63301603A JP30160388A JP2869982B2 JP 2869982 B2 JP2869982 B2 JP 2869982B2 JP 63301603 A JP63301603 A JP 63301603A JP 30160388 A JP30160388 A JP 30160388A JP 2869982 B2 JP2869982 B2 JP 2869982B2
- Authority
- JP
- Japan
- Prior art keywords
- grain size
- gas
- semiconductor device
- crystal grain
- sputtering
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 title description 7
- 239000007789 gas Substances 0.000 claims description 31
- 238000004544 sputter deposition Methods 0.000 claims description 17
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 3
- 239000013078 crystal Substances 0.000 description 18
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 10
- 239000002245 particle Substances 0.000 description 8
- 229910052754 neon Inorganic materials 0.000 description 7
- 229910052786 argon Inorganic materials 0.000 description 5
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 229910052743 krypton Inorganic materials 0.000 description 2
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 229910008486 TiSix Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000005477 sputtering target Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の配線層形成に利用される。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for forming a wiring layer of a semiconductor device.
本発明は半導体装置の製造方法に関し、特に、半導体
集積回路に用いられる配線層をスパッタ法により形成す
る形成方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a wiring layer used in a semiconductor integrated circuit by a sputtering method.
本発明は、配線材料をターゲットとして希ガスをスパ
ッタリングガスとしてスパッタ法により半導体装置の配
線層を形成する工程を含む半導体装置の製造方法におい
て、 前記希ガスとして二種類以上の希ガスの混合ガスを用
いることにより、 堆積される前記配線材料の結晶粒の大きさのばらつき
を小さくし信頼性の高い配線が得られるようにしたもの
である。The present invention relates to a method for manufacturing a semiconductor device including a step of forming a wiring layer of a semiconductor device by a sputtering method using a rare gas as a sputtering gas with a wiring material as a target, wherein a mixed gas of two or more rare gases is used as the rare gas. By using this, variation in the size of crystal grains of the wiring material to be deposited is reduced, and a highly reliable wiring can be obtained.
従来、この種の半導体集積回路に用いられる配線層の
形成方法は、スパッタ蒸着法を用いアルゴンをスパッタ
リングガスとして、所望の配線材料に対応したターゲッ
トをスパッタリングガスすることにより堆積し形成して
いた。Conventionally, as a method of forming a wiring layer used in this type of semiconductor integrated circuit, a sputtering target is used to deposit and form a target corresponding to a desired wiring material by sputtering using argon as a sputtering gas.
前述した従来の単一のスパッタリングガスを用いてス
パッタ法により堆積し形成した配線層では、一般に同一
の基板温度において配線層の結晶粒径および粒径のばら
つきを制御することは困難であり、また半導体集積回路
上に存在する凹凸部の配線層領域で結晶粒径の不均一が
生じている。このため、堆積した配線層を公知の光リソ
グラフィーおよびドライエッチング技術によって所望の
配線パターンを形成すると、配線パターンの場所により
配線幅に対する結晶粒径の比が異なったり、また配線の
長さ方向で結晶粒径にばらつきを生じたりする。エレク
トロマイグレーションおよびストレスマイグレーション
などの信頼性はこれら結晶粒径に依存するため、耐性の
ある最適値に制御性よく形成することが重要であるが、
現状では困難である。特に段差のある領域に設けられた
配線部分は、結晶粒径が他の配線部分に比べて不均一に
なるため、エレクトロマイグレーション現象による配線
材料の蓄積・空孔形成が発生し易く配線が断線しやすい
欠点がある。In the wiring layer deposited and formed by the sputtering method using the conventional single sputtering gas described above, it is generally difficult to control the crystal grain size and the variation in the grain size of the wiring layer at the same substrate temperature, and The crystal grain size is non-uniform in the wiring layer region of the uneven portion existing on the semiconductor integrated circuit. For this reason, when a desired wiring pattern is formed on the deposited wiring layer by a known photolithography and dry etching technique, the ratio of the crystal grain size to the wiring width varies depending on the location of the wiring pattern, or the crystal size in the length direction of the wiring may vary. Variations occur in the particle size. Since reliability such as electromigration and stress migration depends on these crystal grain diameters, it is important to form a resistive optimum value with good controllability.
It is difficult at present. In particular, the wiring portion provided in the stepped region has a non-uniform crystal grain size compared to other wiring portions, so that the wiring material is likely to accumulate and form voids due to the electromigration phenomenon and the wiring is disconnected. There is an easy disadvantage.
本発明の目的は、前記の欠点を除去することにより、
配線層の結晶粒径のばらつきを小さくし、信頼性の高い
配線を形成することができる半導体装置の製造方法を提
供することにある。The object of the present invention is to eliminate the disadvantages mentioned above,
It is an object of the present invention to provide a method of manufacturing a semiconductor device which can reduce variation in crystal grain size of a wiring layer and can form a highly reliable wiring.
本発明は、半導体基板上にアルミニウムを含む配線層
を堆積する半導体装置の製造方法において、NeとNeを除
く希ガスを含む二種類以上の希ガスからなる混合ガスを
スパッタリングガスとして配線層を堆積することを特徴
とする。The present invention provides a method for manufacturing a semiconductor device for depositing a wiring layer containing aluminum on a semiconductor substrate, wherein the wiring layer is deposited using a mixed gas of two or more kinds of rare gases including Ne and a rare gas other than Ne as a sputtering gas. It is characterized by doing.
単一の希ガスによりスパッタされた被スパッタ粒子の
持つエネルギーが希ガスの質量に依存し、またスパッタ
された被スパッタ粒子の結晶粒径が被スパッタ粒子の持
つエネルギーに依存する。この結晶粒径が被スパッタ粒
子の持つエネルギーに依存することは本発明者が初めて
明らかにしたものである。すなわち、被スパッタ粒子の
持つエネルギーに幅をもたせること、また高エネルギー
の粒子数を増加させることで結晶粒径を制御できる。The energy of the sputtered particles sputtered by a single rare gas depends on the mass of the rare gas, and the crystal grain size of the sputtered particles depends on the energy of the sputtered particles. The present inventors have first clarified that the crystal grain size depends on the energy of the particles to be sputtered. In other words, the crystal grain size can be controlled by giving the energy to the sputtered particles a wide range and increasing the number of high energy particles.
本発明は、質量数の異なる複数の希ガスを用いてスパ
ッタすることにより、このようなエネルギー分布をもつ
被スパッタ粒子を発生させ、配線層を堆積することによ
り、単一の希ガスをスパッタリングガスとしたものに比
べて結晶粒径および粒径のばらつきを容易に制御できる
ようにしたものである。The present invention generates sputtered particles having such an energy distribution by sputtering using a plurality of rare gases having different mass numbers, and deposits a wiring layer, thereby forming a single rare gas as a sputtering gas. Thus, the crystal grain size and the variation in the grain size can be more easily controlled as compared with those described above.
以下、本発明の実施例について図面を参照して説明す
る。Hereinafter, embodiments of the present invention will be described with reference to the drawings.
図は本発明の第一実施例を説明するためのスパッタ装
置の模式的縦断面図である。図において、１は電源、２
はターゲット、３は半導体ウェハー、４は陽極、５は陰
極、６は真空槽、７は排気系、８はガス導入口、および
９は磁石である。図は典型的な平板直流マグネトロンス
パッタ装置を示しており、図ではスパッタリングガス導
入口は二つ設けてある。FIG. 1 is a schematic longitudinal sectional view of a sputtering apparatus for explaining a first embodiment of the present invention. In the figure, 1 is a power supply, 2
Is a target, 3 is a semiconductor wafer, 4 is an anode, 5 is a cathode, 6 is a vacuum chamber, 7 is an exhaust system, 8 is a gas inlet, and 9 is a magnet. The figure shows a typical flat plate DC magnetron sputtering apparatus, in which two sputtering gas inlets are provided.
本第一実施例では、ターゲット２としてアルミニウム
を用い、スパッタリングガスにアルゴンとネオンをガス
導入口８より同時に真空槽６内に導入し、半導体ウェハ
ー３上にアルミニウム膜を堆積する場合を例に説明す
る。このとき、ターゲット２の投入電力密度は23.0〜2
8.0W/cm2、真空度は1.0mTorr〜8.0mTorr、半導体ウェハ
ー３の直径は15cm、ヒーターの温度は300〜400℃であ
り、アルゴンのネオンに対する分圧を100％〜20％に変
化させる。このような条件でアルミニウム膜を堆積する
と、堆積膜の平均結晶粒径を約1.0μｍ、粒径のばらつ
きを、ネオンを使わないときに比べて最大20％減少させ
ることができる。In the first embodiment, an example is described in which aluminum is used as the target 2, argon and neon are simultaneously introduced into the vacuum chamber 6 from the gas inlet 8 as a sputtering gas, and an aluminum film is deposited on the semiconductor wafer 3. I do. At this time, the input power density of the target 2 is 23.0 to 2
8.0 W / cm 2 , the degree of vacuum is 1.0 mTorr to 8.0 mTorr, the diameter of the semiconductor wafer 3 is 15 cm, the temperature of the heater is 300 to 400 ° C., and the partial pressure of argon to neon is changed to 100% to 20%. When an aluminum film is deposited under such conditions, the average crystal grain size of the deposited film can be reduced to about 1.0 μm, and the variation in grain size can be reduced by up to 20% as compared with the case where neon is not used.
次に、第二実施例として、スパッタリングガスとして
ネオン、アルゴン、およびクリプトンの三種類を用い、
アルミニウム膜を堆積する場合を説明する。用いる装置
は第一実施例で用いたものと同様の装置で、ガス導入口
８が三つのものを用いる。ネオン：アルゴン：クリプト
ン＝０％:100％:0％〜20％:50％:30％程度まで分圧比を
変えてアルミニウム膜を堆積すると、半導体ウェハー３
上に存在する段差部での結晶粒径の不均一を平坦部と同
様に1.5μｍ程度にすることができる。この第二実施例
では、第一実施例に比べて結晶粒径が大きくなる傾向は
あるものの、段差部における結晶粒径の不均一性を改善
できる利点がある。Next, as a second embodiment, using three types of neon, argon, and krypton as a sputtering gas,
The case of depositing an aluminum film will be described. The apparatus used is the same as that used in the first embodiment, and has three gas inlets 8. Neon: Argon: Krypton = 0%: 100%: 0% to 20%: 50%: 30% When the aluminum film is deposited by changing the partial pressure ratio, the semiconductor wafer 3
The non-uniformity of the crystal grain size at the step portion existing above can be reduced to about 1.5 μm as in the case of the flat portion. In the second embodiment, although the crystal grain size tends to be larger than in the first embodiment, there is an advantage that the nonuniformity of the crystal grain size in the step portion can be improved.
なお、前記実施例では、アルミニウム（Al）膜を堆積
する場合を例にとり説明したが、本発明は他の金属、例
えば、Si添加Al膜、Cu添加Al膜ならびにCu、Ti、Ptおよ
びＷ等の金属膜、さらにTiNおよびTiw等混合組成膜、WS
ixおよびTiSix等のシリサイド膜を堆積する場合にも適
用できる。In the above embodiment, the case of depositing an aluminum (Al) film has been described as an example. However, the present invention is not limited to other metals such as a Si-added Al film, a Cu-added Al film, and Cu, Ti, Pt and W. Metal film, further mixed film such as TiN and Tiw, WS
ix and TiSix can also be applied when depositing a silicide film.
以上説明したように、本発明は、スパッタ法を用いて
アルミニウムを含む配線層を形成する際に、スパッタリ
ングガスとして、NeとNeを除く希ガスを含む二種類以上
の希ガスからなる混合ガスを用いることにより、当該堆
積膜の結晶粒径および粒径のばらつきを小さくでき、特
に半導体集積回路上の段差部で生じる結晶粒径の不均一
を少なくすることができる効果がある。これにより、エ
レクトロマイグレーション耐性およびストレスマイグレ
ーション耐性を向上できる効果がある。As described above, in the present invention, when a wiring layer containing aluminum is formed by a sputtering method, a mixed gas containing two or more kinds of rare gases including a rare gas other than Ne and Ne is used as a sputtering gas. By using this, the crystal grain size and the variation in the grain size of the deposited film can be reduced, and in particular, the non-uniformity of the crystal grain size generated at the step portion on the semiconductor integrated circuit can be reduced. Thus, there is an effect that the electromigration resistance and the stress migration resistance can be improved.
図は本発明の第一実施例に用いる蒸着装置を示す模式的
縦断面図。 １……電源、２……ターゲット、３……半導体ウェハ
ー、４……陽極、５……陰極、６……真空槽、７……排
気系、８……ガス導入口、９……磁石。FIG. 1 is a schematic vertical sectional view showing a vapor deposition apparatus used in a first embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Power supply 2 ... Target 3 ... Semiconductor wafer 4 ... Anode 5 ... Cathode 6 ... Vacuum tank 7 ... Exhaust system 8 ... Gas inlet 9 ... Magnet.
Claims (1)
を堆積する半導体装置の製造方法において、NeとNeを除
く希ガスを含む二種類以上の希ガスからなる混合ガスを
スパッタリングガスとして前記配線層を堆積することを
特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device, wherein a wiring layer containing aluminum is deposited on a semiconductor substrate, wherein the mixed gas containing two or more kinds of rare gases including Ne and a rare gas other than Ne is used as a sputtering gas. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63301603A JP2869982B2 (en) | 1988-11-29 | 1988-11-29 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63301603A JP2869982B2 (en) | 1988-11-29 | 1988-11-29 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02148724A JPH02148724A (en) | 1990-06-07 |
| JP2869982B2 true JP2869982B2 (en) | 1999-03-10 |
Family
ID=17898936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63301603A Expired - Fee Related JP2869982B2 (en) | 1988-11-29 | 1988-11-29 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2869982B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5368663B2 (en) * | 2000-04-14 | 2013-12-18 | トーソー エスエムディー，インク． | Sputter target for reducing particulate emission during spattering and method for manufacturing the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61170561A (en) * | 1985-01-25 | 1986-08-01 | Nippon Telegr & Teleph Corp <Ntt> | High melting point metal film forming method |
| JPS61287121A (en) * | 1985-06-13 | 1986-12-17 | Oki Electric Ind Co Ltd | Manufacture of semiconductor integrated circuit |
| JPS6329504A (en) * | 1986-07-23 | 1988-02-08 | Hitachi Ltd | Bias sputtering method |
-
1988
- 1988-11-29 JP JP63301603A patent/JP2869982B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02148724A (en) | 1990-06-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |