JPS627263B2 - - Google Patents
Info
- Publication number
- JPS627263B2 JPS627263B2 JP57119914A JP11991482A JPS627263B2 JP S627263 B2 JPS627263 B2 JP S627263B2 JP 57119914 A JP57119914 A JP 57119914A JP 11991482 A JP11991482 A JP 11991482A JP S627263 B2 JPS627263 B2 JP S627263B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- bias
- film
- nitride thin
- metal nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/0021—Reactive sputtering or evaporation
- C23C14/0036—Reactive sputtering
Landscapes
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Physical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は内部応力が小さく、かつ比抵抗の小さ
い金属窒化物薄膜の製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a metal nitride thin film with low internal stress and low specific resistance.
一般にチタン、モリブデン、タンタル等の高融
点金属の窒化物はきわめて高い融点と高い機械的
硬度を有し、熱的、化学的にも安定であるために
各種装置、部品の機械的・熱的保護膜として使用
され、最近ではさらに半導体集積回路の高耐熱電
極材料の一つとして実用化されつつある。 In general, nitrides of high-melting point metals such as titanium, molybdenum, and tantalum have extremely high melting points and high mechanical hardness, and are thermally and chemically stable, providing mechanical and thermal protection for various devices and parts. It is used as a film, and has recently been put into practical use as a highly heat-resistant electrode material for semiconductor integrated circuits.
金属窒化物薄膜を半導体集積回路の電極材料と
して用いる場合、比抵抗が低いことが第1の条件
である。 When using a metal nitride thin film as an electrode material for a semiconductor integrated circuit, the first condition is that the specific resistance is low.
一般に、チタン、ジルコニウムなどの窒化物は
バルクで比較すると、もとの金属元素よりも比抵
抗が小さくなることが知られている。しかし、電
極材料に用いる厚さ数100〜数1000Åの薄膜で
は、種々の散乱機構のために比抵抗は一般に高く
なる傾向があり、これを下げることが一つの重要
な技術となつている。 Generally, it is known that nitrides such as titanium and zirconium have a lower resistivity than the original metal element when compared in bulk. However, thin films used as electrode materials with a thickness of several hundred to several thousand angstroms generally tend to have a high specific resistance due to various scattering mechanisms, and reducing this resistance is an important technique.
例えば、窒化チタン薄膜を、窒素・アルゴン混
合ガス中の反応性スパツタリングにより得る場
合、窒素分圧、窒素・アルゴン混合ガス圧力を増
加させると窒化チタン薄膜の元素組成膜中の不純
物の影響により比抵抗は増加するため、通常は放
電が持続できる最小の圧力に設定される。また、
さらに比抵抗を下げるために基板に負の直流バイ
アス電圧を印加することが効果的である。 For example, when a titanium nitride thin film is obtained by reactive sputtering in a nitrogen/argon mixed gas, when the nitrogen partial pressure and the nitrogen/argon mixed gas pressure are increased, the elemental composition of the titanium nitride thin film is affected by impurities in the film, resulting in specific resistance. increases, so it is usually set to the lowest pressure that can sustain a discharge. Also,
It is effective to apply a negative DC bias voltage to the substrate in order to further lower the resistivity.
第1図は基板に負のバイアス電圧を印加したス
パツタリング装置の概略図を示すもので、図にお
いて1は真空チヤンバ、2は排気系、3はチタ
ン、モリブデン、タンタル等の金属ターゲツト、
4はしやへい板、5は高周波電源回路、6は基
板、7はバイアス電源、8はガス導入口、9は流
量調節弁である。第2図および第3図は窒化チタ
ン薄膜の場合の膜の比抵抗と、膜内に発生した内
部応力についてそれぞれ基板バイアスの効果を示
したグラフである。ρは比抵抗、σは内部応力
(実線で示す)を示す。このデータは、窒素分圧
2.8mTorr、窒素・アルゴン混合ガス圧力16.8m
Torr、高周波電力400Wの場合である。 FIG. 1 shows a schematic diagram of a sputtering apparatus in which a negative bias voltage is applied to a substrate. In the figure, 1 is a vacuum chamber, 2 is an exhaust system, 3 is a metal target such as titanium, molybdenum, tantalum, etc.
4 is a shield plate, 5 is a high frequency power supply circuit, 6 is a substrate, 7 is a bias power supply, 8 is a gas inlet, and 9 is a flow rate control valve. FIGS. 2 and 3 are graphs showing the effect of substrate bias on the specific resistance of a titanium nitride thin film and the internal stress generated within the film, respectively. ρ indicates specific resistance, and σ indicates internal stress (shown as a solid line). This data is based on nitrogen partial pressure
2.8mTorr, nitrogen/argon mixed gas pressure 16.8m
This is the case with Torr and high frequency power of 400W.
このように、基板バイアス印加は窒化チタン薄
膜の比抵抗ρの低減に対してきわめて効果的では
あるが、反面、膜内に著しい内部応力σが発生す
るため、半導体集積回路を製造する際にウエハの
そりにより微細パターンの形成が困難となるこ
と、膜が厚い場合にはクラツクやはがれが発生す
るなど著しい障害の原因となつていた。 In this way, applying a substrate bias is extremely effective in reducing the resistivity ρ of a titanium nitride thin film, but on the other hand, it generates significant internal stress σ in the film, so it is difficult to apply a wafer bias when manufacturing semiconductor integrated circuits. The warping of the film makes it difficult to form fine patterns, and when the film is thick, it causes serious problems such as cracking and peeling.
それを解決する一つの方法に、第2図に示す遷
移領域すなわち、比抵抗および内部応力が急変す
る点にバイアス電圧を設定し、比抵抗も内部応力
も中程度の膜を得ることが考えられるが、遷移領
域を決めるバイアス電圧の範囲がきわめて狭く、
再現性を得るのが著しく困難であつた。 One way to solve this problem is to set the bias voltage in the transition region shown in Figure 2, that is, the point where the specific resistance and internal stress suddenly change, to obtain a film with intermediate specific resistance and internal stress. However, the range of bias voltage that determines the transition region is extremely narrow.
It was extremely difficult to obtain reproducibility.
本発明は以上の問題を解決するために、基板バ
イアスとしてバイアス電圧が零の状態と負の状態
とが交互にくり返えされるバイアス電圧を印加す
ることにより金属窒化物薄膜の内部応力ならびに
比抵抗を実用上問題のないレベルにまで下げるこ
とを目的とするものである。 In order to solve the above problems, the present invention applies a bias voltage in which a zero bias voltage state and a negative bias voltage state are alternately repeated as a substrate bias, thereby reducing the internal stress and specific resistance of a metal nitride thin film. The purpose is to reduce the amount of water to a level that poses no practical problems.
前記の目的を達成するため本発明は、導電性を
有する金属窒化物薄膜を反応性スパツタ法で形成
する金属窒化物薄膜の製造方法において、金属窒
化物が数Åの厚さ堆積する時間以内の時間で電圧
が零の状態と負の状態を交互に繰り返してなる基
板バイアスを被薄膜堆積基板に印加して前記金属
窒化物薄膜を堆積することを特徴とする金属窒化
物薄膜の製造方法を発明の要旨とするものであ
る。 To achieve the above object, the present invention provides a method for producing a metal nitride thin film having conductivity by a reactive sputtering method, in which a metal nitride is deposited to a thickness of several angstroms within a time. Invention of a method for manufacturing a metal nitride thin film, characterized in that the metal nitride thin film is deposited by applying a substrate bias in which the voltage is alternately in a zero state and a negative state over time to a substrate on which the thin film is to be deposited. This is the gist of the report.
次に本発明の実施例を添附図面について説明す
る。なお実施例は一つの例示であつて、本発明の
精神を逸脱しない範囲内で、種々の変更あるいは
改良を行いうることは云うまでもない。 Next, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.
本発明の実施に用いられる装置は第1図に示す
ものであり、手順はまずチヤンバ1内を排気後、
窒素を所定の分圧になるまでガス導入口8に設け
られた流量調節弁9を調節することにより導入す
る。つづいて、アルゴンを全圧力が所定の圧力に
なるまで導入したのち放電を開始させ、金属窒化
物薄膜を堆積させる。基板バイアス電源7にはバ
イアス電圧が零の状態と負の状態が交互にくり返
す波形の電圧を加える。第4図はバイアス電圧波
形の例を示すものであり、デユーテイ1/2の矩形
波である。電圧の大きさ−Vは例えば−50Vであ
り、周期Tは例えば100nSである。第5図は、バ
イアス電圧波形の他の例を示すものであり、商用
電源を半波整流するだけで簡単に得られる脈流バ
イアス電圧波形である。電圧の大きさ−Vは整流
する前の交流電圧の実効値をVrnSとすれば、
V=√2VrnS
で与えられる。周期Tは商用周波数が50Hzの場
合、20nSである。 The apparatus used to carry out the present invention is shown in FIG. 1, and the procedure is to first exhaust the chamber 1, then
Nitrogen is introduced by adjusting a flow rate control valve 9 provided at the gas inlet 8 until a predetermined partial pressure is reached. Subsequently, argon is introduced until the total pressure reaches a predetermined pressure, and then discharge is started to deposit a metal nitride thin film. A voltage having a waveform in which the bias voltage alternates between a zero state and a negative state is applied to the substrate bias power supply 7. FIG. 4 shows an example of the bias voltage waveform, which is a rectangular wave with a duty of 1/2. The voltage magnitude -V is, for example, -50V, and the period T is, for example, 100 nS . FIG. 5 shows another example of the bias voltage waveform, which is a pulsating bias voltage waveform that can be easily obtained by half-wave rectifying the commercial power supply. The magnitude of the voltage -V is given by V=√2V rnS , where V rnS is the effective value of the AC voltage before rectification. The period T is 20 nS when the commercial frequency is 50 Hz.
一例として、窒化チタン薄膜を窒素分圧2.8m
Torr、窒素・アルゴン混合ガス圧力を16.8m
Torr、高周波電力400Wとし、かつ、基板バイア
ス電圧として実効値30V、40Vおよび50Vの交流
電圧を半波整流して得た負の脈流バイアス電圧を
印加して堆積した窒化チタン薄膜の比抵抗および
内部応力を第2図および第3図に破線で示す。た
だし、横軸はバイアス電圧の実効値で表してあ
る。第2図および第3図に破線で示したデータか
ら、直流バイアス電圧印加の場合に見られた比抵
抗の急しゆんな変化が緩和され、かつ、内部応力
の発生し始める領域がバイアス電圧の高い側に移
るため、内部応力が小さくかつ比抵抗が実用上問
題にならない程度に低い膜を容易に得ることがで
きることがわかる。 As an example, a titanium nitride thin film with a nitrogen partial pressure of 2.8 m
Torr, nitrogen/argon mixed gas pressure 16.8m
Torr, high-frequency power of 400 W, and negative pulsating bias voltage obtained by half-wave rectification of AC voltage with effective values of 30 V, 40 V, and 50 V as substrate bias voltage. Internal stresses are shown in dashed lines in FIGS. 2 and 3. However, the horizontal axis represents the effective value of the bias voltage. From the data shown by the broken lines in Figures 2 and 3, it is clear that the rapid change in resistivity observed when DC bias voltage is applied is alleviated, and the region where internal stress begins to occur is It can be seen that it is possible to easily obtain a film in which the internal stress is small and the specific resistance is so low that it does not pose a practical problem.
以上のように、電圧が零および負の値を交互に
くり返すバイアス電圧を印加した場合の窒化チタ
ン薄膜の成長の機構を考察すると、基板バイアス
が零の場合に得られる比抵抗は大きいが内部応力
の小さい膜と、基板バイアスが負の値の場合に得
られる内部応力は大きいが比抵抗が小さな膜とが
交互に混じりあつて成長することにより、両方の
中間の膜が形成されるものと考えられ、結果的に
みれば、両者の長所を兼ね備えた膜と考えること
もできる。 As mentioned above, when considering the mechanism of growth of titanium nitride thin film when applying a bias voltage that alternates between zero and negative values, we find that the specific resistance obtained when the substrate bias is zero is large, but the internal By growing a film with low stress and a film with high internal stress but low resistivity obtained when the substrate bias is a negative value, an intermediate film between the two is formed. As a result, it can be considered as a film that combines the advantages of both.
本発明で印加する交流バイアスの周期は、この
種のスパツタ法での膜の堆積速度が数10Å毎秒で
あることを考えると短かく、半周期の間に数Å程
度しか膜が堆積されないような周期である。この
種のスパツタ法では、数Å程度の厚さの膜はきれ
いな単原子層のようには基板上には堆積されない
ので、次の半周期のバイアス状態でスパツタされ
た層と混じり合つて堆積され、均一な膜が堆積さ
れることになる。この均一な膜が、第2図と第3
図の破線で示した特性を生じさせるものと考えら
れる。 The period of the AC bias applied in the present invention is short considering that the film deposition rate in this type of sputtering method is several tens of angstroms per second, and the period of the alternating current bias applied is short, considering that the film deposition rate in this type of sputtering method is several tens of angstroms per second. It is a cycle. In this type of sputtering method, a film with a thickness of several angstroms is not deposited on the substrate as a clean monolayer, but is mixed with the sputtered layer under the bias conditions of the next half cycle. , a uniform film will be deposited. This uniform film is shown in Figures 2 and 3.
This is thought to cause the characteristics shown by the broken line in the figure.
以上説明した様に、本発明によれば反応性スパ
ツタリングにおいて基板バイアス電圧として、電
圧が零および負の状態を交互にくり返す波形のバ
イアス電圧を印加することにより、内部応力が小
さく、かつ比抵抗の小さい金属窒化物薄膜を容易
に得ることができ、この薄膜を半導体集積回路の
電極の一部に、例えば拡散障壁層として使用すれ
ば、耐熱性ならびに信頼性に優れた半導体集積回
路が歩留り良く、経済的に実現することができる
効果を有するものである。 As explained above, according to the present invention, internal stress is small and specific resistance is reduced by applying a waveform bias voltage in which the voltage is alternately zero and negative as the substrate bias voltage in reactive sputtering. A metal nitride thin film with a small amount of nitride can be easily obtained, and if this thin film is used as a part of the electrode of a semiconductor integrated circuit, for example as a diffusion barrier layer, a semiconductor integrated circuit with excellent heat resistance and reliability can be produced at a high yield. , which has effects that can be realized economically.
第1図はスパツタリング装置の概略図、第2図
および第3図は窒化チタン薄膜を高周波反応性ス
パツタリング法により形成した場合の膜のそれぞ
れ比抵抗と内部応力について基板直流バイアス効
果(実線)および基板バイアスとして、その電圧
が零および負の値を交互にくり返す波形のバイア
ス電圧を印加した場合の効果(破線)を示すグラ
フ、第4図および第5図は本発明の特徴とするバ
イアス電圧波形の一例を示すものであり、それぞ
れ矩形および脈流バイアス電圧である。
1……真空チヤンバ、2……排気系、3……金
属ターゲツト、4……しやへい板、5……高周波
電源回路、6……基板、7……バイアス電源、8
……ガス導入口、9……流量調節弁。
Figure 1 is a schematic diagram of the sputtering apparatus, and Figures 2 and 3 show the substrate DC bias effect (solid line) and the substrate DC bias effect (solid line) and the internal stress of the titanium nitride thin film formed by high-frequency reactive sputtering. A graph showing the effect (dashed line) of applying a bias voltage with a waveform in which the voltage alternately repeats zero and negative values as a bias, and FIGS. 4 and 5 show the bias voltage waveform that is a feature of the present invention. An example is shown for rectangular and pulsating bias voltages, respectively. 1... Vacuum chamber, 2... Exhaust system, 3... Metal target, 4... Shrink plate, 5... High frequency power supply circuit, 6... Substrate, 7... Bias power supply, 8
...Gas inlet, 9...Flow control valve.
Claims (1)
ツタ法で形成する金属窒化物薄膜の製造方法にお
いて、金属窒化物が数Åの厚さ堆積する時間以内
の時間で電圧が零の状態と負の状態を交互に繰り
返してなる基板バイアスを被薄膜堆積基板に印加
して前記金属窒化物薄膜を堆積することを特徴と
する金属窒化物薄膜の製造方法。1 In a metal nitride thin film manufacturing method in which a conductive metal nitride thin film is formed by a reactive sputtering method, the voltage is zero and negative within the time it takes for the metal nitride to be deposited to a thickness of several angstroms. A method for producing a metal nitride thin film, characterized in that the metal nitride thin film is deposited by applying a substrate bias having alternating conditions to a substrate on which the thin film is deposited.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11991482A JPS5913608A (en) | 1982-07-12 | 1982-07-12 | Manufacture of thin metallic nitride film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11991482A JPS5913608A (en) | 1982-07-12 | 1982-07-12 | Manufacture of thin metallic nitride film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5913608A JPS5913608A (en) | 1984-01-24 |
| JPS627263B2 true JPS627263B2 (en) | 1987-02-16 |
Family
ID=14773308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11991482A Granted JPS5913608A (en) | 1982-07-12 | 1982-07-12 | Manufacture of thin metallic nitride film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5913608A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6393861A (en) * | 1986-10-06 | 1988-04-25 | Nec Corp | Method for depositing low-stress thin film |
| JP2602276B2 (en) * | 1987-06-30 | 1997-04-23 | 株式会社日立製作所 | Sputtering method and apparatus |
| JPH089769B2 (en) * | 1987-07-09 | 1996-01-31 | 松下電器産業株式会社 | Preparation method of composition-modulated nitrided alloy film |
| JP4765001B2 (en) * | 2005-06-22 | 2011-09-07 | 富士電機株式会社 | Semiconductor device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5938307B2 (en) * | 1978-09-12 | 1984-09-14 | 富士通株式会社 | Method of forming metal compound film |
-
1982
- 1982-07-12 JP JP11991482A patent/JPS5913608A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5913608A (en) | 1984-01-24 |
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