JP2872098B2 - Counter device with test function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter device with a test function, and more particularly to a counter device with a test function for testing the quality of a timer counter device formed as a large-scale integrated circuit (LSI).

[0002]

2. Description of the Related Art In general, a function test is performed on an LSI by an LSI tester to judge the quality of the function. In order to accurately detect failure of each functional circuit constituting the LSI,
The design of test patterns is important. In order to completely determine whether the counter function is good or not for an LSI counter device, it is necessary to determine whether the count output and carry output for each count value are correct for each bit. is there. On the other hand, since the memory capacity for storing test patterns of the LSI tester is limited, it is difficult and impractical to test all count values in the case of a multi-bit counter. Therefore, it is necessary to reduce the data amount of the test pattern in order to determine the quality of the multi-bit counter.

A general serial scan path type n-bit counter with a test function described in Japanese Patent Application Laid-Open No. 3-259618 (literature 1) generally has an input terminal and an output terminal, and has a function of adding +1 or -1. The circuit comprises n scan macros corresponding to each bit, each having a serial-in terminal, a test clock terminal, a shift clock terminal, and a serial-out terminal. The normal operation and the test operation are switched by a test clock, and the scan macro is operated as a storage element such as a flip-flop or a latch during the normal operation. During the test operation, the scan macro operates as a serial-in / serial-out shift register, inputs the shift clock, supplies test data to the serial-in terminal, and serially outputs data from the serial-out terminal (scan). mode). Thereafter, the scan macro is regarded as a part of the external terminal, and the whole counter is operated by the data from the scan macro and the general input while supplying a clock from the test clock terminal (test clock mode). In the scan mode again, the data of the scan macro is output to the serial out terminal, and the test data is supplied from the serial in terminal. Thereafter, the test is performed by repeatedly operating the test clock mode and the scan mode alternately.

In this scan path test method, an LSI
Even if the number of test patterns in the tester is limited, a portion where a failure such as a disconnection may occur is searched, and test data for detecting the failure is automatically generated. It is repeated to supply the signal to the input terminal of the counter device, switch to the scan mode, switch to the test clock mode and supply the next test pattern, so that the multi-bit counter can accurately perform the pass / fail test. .

However, this test is only a failure test such as disconnection or short circuit of the LSI, and cannot be a function test as a counter. The function test as a counter requires a separate 2 n -th power test pattern number, which takes a long test time.

Next, referring to FIG. 3, which is a block diagram of a first conventional counter device with a test function described in Document 1 which aims to reduce the number of test pattern data, the first conventional counter device with a test function will be described. Is a counter 1 having a storage element 101 for outputting a count value and an adder 102 for adding a predetermined value and an output count value of the storage element 101.
00 and a pattern generating circuit 1 for generating a test pattern
03, and a selector 104 for supplying test pattern data of the pattern generation circuit 103 to the storage element 101 in the test mode.

Next, the operation of the conventional first counter device with a test function will be described with reference to FIG. 3 and FIG. 4 showing the operation waveforms in a time chart. First, the output pattern data of the pattern generation circuit 103 is described. As shown in Table 1, each time the storage element 101 counts a certain number of clocks, the output count value is set to a value that carries up.

[0008]

[Table 1]

Next, the test signal TEST is made active (H level) and the test pattern data is
00 is written to the storage element 101 (load value L). next,
When the test signal TEST is made inactive (L level), the selector 104 is switched to the output selection state of the adder 102. In this state, when the clock CLK is supplied, the output of the adder 102 is set to the loaded test pattern data value. The value changes to a value obtained by adding a value (for example, 1), and the added value is stored in the storage element 101 (count value N1). The output count value of the storage element 101 is input to the adder 102 again. Here, as shown in Table 1, the first load value is all 0, and the least significant bit of the first count value 1 obtained by adding 1 to this is 0. Next, once again, the clock CL
When K is supplied, the output count value N2 of the storage element at this time is carried by adding 1 to the least significant bit 1 so that only the second least significant bit becomes 1.
As described above, in the test mode, the potential changes to the H level for one clock cycle, and then changes to the L level for the duration of two clock cycles, and again changes to the H level. The above operation is repeated while changing the load value L as shown in Table 1, and the corresponding count values N1, N
By checking step 2, it can be determined whether the carry is normal. . According to this method, a test of whether or not the function of the counter 100 is normal can be performed by the operation of n × 3 patterns (24 patterns in the case of the 8-bit counter).
This can be greatly reduced as compared with a 2 n pattern.

However, the first conventional counter device with a test function switches the signal line connecting the adder 102 and the storage element 101 to the test pattern generating circuit 103 in the normal mode for each test mode, and switches the load line to the test pattern generating circuit 103. Is started, the count operation cannot be performed during this load cycle, and the load cycle becomes a factor for extending the test time.

Since the result of the counting operation using the load value L is a value independent of the result using the next load value L, it is necessary to output it to the outside each time and verify it. In this case, it is necessary to secure an n-bit terminal or stop the counter every time one count is completed and output the count value to the outside.

Next, referring to FIG. 5, which shows a block diagram of a second conventional counter device with a test function for reducing the number of test pattern data, the second conventional counter device with a test function has the same configuration. Is an 8-bit counter composed of bit elements 0 to 7,
Input data according to clock CLK1.
Latch circuits 10 to 17 for holding (bits 0 to 7 in the second digit indicate bit numbers), latch circuits 20 to 27 for inputting and holding data according to clock CLK2 and including storage elements such as flip-flops, A two-input EXOR circuit 30 to 37 constituting a half adder and a three-input A which constitutes a counter overflow (carry) detection circuit at the time of a normal counting operation and outputs an overflow detection signal OD.
ND circuits 140 to 147 and a two-input AND circuit 1 constituting a counter overflow detection circuit in a test mode
50 to 157, and two-input OR circuits 160 to 167 which form output gates of the overflow detection circuit and output overflow outputs OV0 to OV7, respectively.

For convenience of description, bit element 7 is representatively described.
The latch circuit 17 receives the output of the latch circuit 27 at the data input terminal. EXOR circuit 3
7 receives the output of the latch circuit 17 at one input terminal and the overflow output OV6 of the lower bit 6 at the other input terminal. However, only the EXOR circuit 30 of the least significant bit 0 receives the H level supply to the other input terminal. AND circuit 14
7 receives a test signal TEST at a first input terminal, an output of the latch circuit 17 at a third input terminal, and an overflow detection signal OD of the lower bit 6 at a second input terminal. However, the least significant bit 0 of the 3-input AND circuit 140
Only the second input receives an H level supply at the second input terminal. AND
The circuit 157 receives the input signal TEST at one input terminal, and receives the output of the latch circuit 17 at another input terminal. OR circuit 16
7, the output of the AND circuit 147 is supplied to one input terminal and the output of the AND circuit 157 is supplied to the other input terminal, and an overflow signal OV is output.

The clocks CLK1 and CLK2 have different phases. The reset RES initializes the latch circuits 10 to 17 and 20 to 27 when it is at the H level. The test signal TEST has the L level during the normal count operation. And the H level during the test operation.

Next, the operation of the second conventional counter device with a test function will be described with reference to FIG. 5. When the test signal TEST is at the H level, the output signals of the lower bit latch circuits 10 to 16 are output. The level is determined by the AND circuit 15
The bits are directly transmitted to the adjacent higher-order EXOR circuits 31 to 37 via the 0 to 156 and the OR circuits 160 to 166, respectively. The level of the output signal of the latch circuit 17 of the most significant bit is determined by the AND circuit 157 and the OR signal.
The signal is directly transmitted as an overflow signal OV via the circuit 167. Therefore, as shown in Table 2, each of the clocks CLK1 and CLK2 has a bit number of n × 2 clocks (16 clocks in the case of the 8-bit counter of this example).
, The level inversion operation of the latch circuit for all bits of the counter is performed and is reflected on the overflow output OV. Therefore, the number of test patterns required in this case is 34 including each reset pattern.

[0016]

[Table 2]

As described above, in the second conventional counter device with a test function, the overflow operation of each bit, that is, the carry is divided at the time of the test to perform the count operation, so that the latch circuit and the adder circuit can be tested. It is necessary to separately perform a test including a carry operation in a normal operation mode. Therefore, the test in the normal operation mode causes an increase in test time.

[0018]

In the above-described conventional counter device with a test function, the signal line connecting the adder and the storage element is switched to the test pattern generation circuit in the normal mode for each test mode. Since the load cycle is activated, the counting operation cannot be performed during the load cycle, and thus the load cycle has a drawback that the test time is extended.

Also, since the count operation results for each load value are mutually independent values, it is necessary to output them to the outside each time and verify them, so that the same number of external terminals as the number of counter bits are reserved for testing. Or it is necessary to stop the counter every time one count is completed and output the count value to the outside. In the former case, the chip area is increased, and in the latter case, the test time is shortened. was there.

In the conventional second counter device with a test function, the carry operation of each bit is divided at the time of the test to perform the count operation. Therefore, the latch circuit and the adder circuit can be tested, but the carry operation is included. The test must be separately performed in the normal operation mode, and there is a disadvantage that the test in the normal operation mode causes an increase in test time.

[0021]

In the counter device with a test function according to the present invention, each of the first count element of the most significant bit and N (positive integer) -1 second counter elements of the least significant bit is provided. A first latch circuit that is controlled by a first clock and outputs a first latch signal, an exclusive OR circuit that outputs an exclusive OR signal of the first latch signal and a carry input signal, A second latch circuit which is controlled by a second clock and outputs a second latch signal in response to the supply of the exclusive OR signal, and an AND signal of the first latch signal and the carry input signal AND circuit for outputting the carry output signal as a carry output signal, and an N-bit test circuit cascaded with the first and second count elements so as to supply the carry output signal as a carry input signal of an upper bit. In the counter device with a function, the second counter element has a first count signal as its own second latch signal and a second count signal as the second latch signal of an adjacent upper bit counter element. And a test operation circuit which generates a predetermined operation signal in response to the supply of the test signal and supplies the operation signal to the first latch circuit.

[0022]

FIG. 1 is a block diagram showing a first embodiment of the present invention, in which constituent elements common to those in FIG. The counter device with a test function according to the present embodiment shown in this figure is an 8-bit counter composed of common bit elements 0A to 6A and bit element 7A, and each of bit elements 0A to 7A is a conventional second test. Latch circuits 10 to 17, common to the counter device with function, latch circuits 20 to 27,
In addition to the two-input EXOR circuits 30 to 37 forming a half adder, a two-input EXOR circuit which receives a counter overflow (carry) signal of lower bits and forms an overflow detection circuit to output overflow output signals OV0 to OV. A
ND circuits 40 to 47 are provided.

Further, each of bit elements 0A to 6A is
In addition to the above components, a two-input EXNOR circuit 50-
56 and transfer gate 6 comprising P-type transistor
There are provided arithmetic circuits 80 to 86 each including transfer gates 0 to 66 and transfer gates 70 to 76 formed by connecting P and N type transistors in parallel.

The bit element 7A has a latch circuit 17 connected to the data input terminal, similarly to the conventional bit element 7.
EXOR circuit 37 receives the output of latch circuit 17 at one input terminal and lower bit element 6A at the other input terminal.
Are supplied respectively. A
The other input terminal of the output of the latch circuit 17 is commonly connected to one input terminal of the ND circuit 47 and the other input terminal of the EXOR 37, and receives each of the lower overflow outputs OV6.

The details of the connection of the bit elements 0A to 6A will be described with reference to the bit element 6A as a representative for convenience of explanation.
The output of the OR circuit 56 is supplied. The latch circuit 26 receives the output of the EXOR circuit 36 at the data input terminal. The EXOR circuit 36 receives the overflow output OV5 of the lower bit element 5A at one input terminal and the other input terminal of the output of the latch circuit 16 at the other input terminal. One input terminal of the AND circuit 46 and the other input terminal of the output of the latch circuit 16 are EXOR3
6 is commonly connected to the other input terminal and the lower overflow output O
V5 is supplied. However, only the least significant bit element 0A is connected to the EXOR circuits 30, AN connected in common.
The other input terminal of the D circuit 40 receives the supply of the H level.

Explaining the details of the connection of the arithmetic circuit 86, the EXNOR circuit 56 has one input terminal connected to the drain (output terminal) of the transfer gate 66 and the other input terminal connected to the output of the latch circuit 26. The transfer gate 66 has a gate connected to the power supply VD
D receives each supply. Transfer gate 76
Is the P of the test signal TEST applied to the gate of the N-type transistor.
The output of the latch circuit 27 is connected to one data terminal, and the drain of the transfer gate 66 is connected to the other data terminal.

The clocks CLK1 and CLK2 are clocks having different phases, the reset RES initializes the latch circuits 10 to 17 and 20 to 27 when it is at the H level, and the test signal TEST has the L level during the normal count operation. And the H level during the test operation.

Next, the operation of the present embodiment will be described with reference to FIG. 1. First, when the test signal TEST is at the L level, the EXNOR circuit 50 of the arithmetic circuits 80 to 86 will be described.
Since the H level is supplied to one input terminal of each of the EXNOR circuits 50 to 56 via the transfer gates 60 to 66, these EXNOR circuits 50 to 56
Latch circuits 10 to 16
Respectively, the operation becomes the same as that of the conventional counter, and the normal counting operation is performed as shown in Table 3.

[0029]

[Table 3]

Next, when the test signal TEST is at the H level, the output levels of the latch circuits 21 to 27 of the respective upper bit elements are connected to one input terminal of the EXNOR circuits 50 to 56 via the transfer gates 70 to 76. The EXNOR circuits 56 to 50 propagate the outputs of the latch circuits 21 to 27 of the upper bit elements and the EXNOR operation outputs of the latch circuits 20 to 26 of the own bit element to the latch circuits 10 to 16, respectively. I do. Therefore,
As shown in Table 4, the latch circuits 10 to 17, 20 to 27
Of the output level from L level to H level to L level, and an AND circuit 4 serving as an overflow detection circuit.
L level of each output level of 0 to 47 → H level → L
Level inversion operation and AND circuits 40 to 40 of all bit elements
Forty-seven carry propagation operations are performed in a series of nine clocks, and these results are reflected in the overflow output OV. By outputting the overflow output OV to the external terminal of the integrated circuit, the counter test result can be checked at the external terminal of the integrated circuit.

[0031]

[Table 4]

That is, in the present embodiment, the data held in the latch circuit 2 (i-1) of the bit element i-1 (i is 0 to 7) A is stored in the latch circuit 1 (i-1) as in the conventional case. )
In the meantime, the arithmetic circuit 8 (i-1) performs an arithmetic operation with the data held in the latch circuit 2i of the upper bit element n. By this operation, test data is generated from the data held in the latch circuit 2i such that an overflow or an underflow of the data held in the latch circuit 1i of the lower bit element iA of the bit element (i-1) occurs. Therefore, test data generated from latch circuit 2i is written into latch circuit 1i. This eliminates the need for the conventional process of writing test data for a function test from an external test data generation circuit to the counter.

A half adder circuit of the bit element i-1A, ie, one input terminal of the EXOR5 (i-1) has a latch 1 (i-
The held data of 1) is transmitted to the other input terminal by the lower bit element i-2.
The overflow / underflow output of the latch circuit 1 of A is input. Therefore, EXOR5 (i-
1) outputs the overflow / underflow of the latch circuit 1 below the lower-order bit element i-2A and the half addition operation result of the latch circuit 1, and the latch circuit 2 (i-1) receives the half addition operation result. Written. This operation is equivalent to the normal operation of the counter. Therefore, the normal count operation is performed, and the count result held in the latch circuit 2 is used as the test data value of the next count.

Therefore, in the n-bit counter, when the count operation is started from the state where the latch circuits 1i and 2i of each bit element iA are initialized, an overflow / underflow of the highest-order bit element nA occurs at n + 1 clocks. Therefore, whether or not the counter function is normal can be detected from the outside by testing the overflow / underflow with an external circuit.

Next, a second embodiment of the present invention will be described with reference to FIG. 2, which is a block diagram in which constituent elements common to those in FIG. The difference from the first embodiment is that the bit element 0B
6B are provided with arithmetic circuits 90 to 96 each comprising an ANDOR composite gate in place of the arithmetic circuits 80 to 86, respectively.

As a representative, the arithmetic circuit 96 of the bit element 6B
The operation circuit 96 is a composite circuit of a two-input AND circuit and a two-input OR whose output terminal is connected to one input terminal.
The output terminal of the OR circuit, that is, the output terminal of the arithmetic circuit 96 is connected to the input terminal of the
The other input terminal of the R circuit is connected to the output terminal of the latch circuit 26, and one input terminal of the AND circuit is connected to the inverted signal of the output of the latch circuit 27 of the upper bit element 7A, and the other input terminal is connected to the test signal TEST. Have been.

The operation of this embodiment will be described. First, when the test signal TEST is at the L level,
The arithmetic circuits 90 to 96 of the respective bit elements 0 to 6 perform the normal counter operation as in the first embodiment in order to propagate the outputs of the latch circuits 20 to 26 to the latch circuits 10 to 16, respectively. Next, when the test signal TEST is at the H level, the arithmetic circuits 90 to 96 respectively have their own bit elements 0 to 6
Of the outputs of the latch circuits 20 to 26 and the inverted values of the outputs of the latch circuits 21 to 27 of the upper bit elements are propagated to the latch circuits 10 to 16. Therefore, the same test operation as in the first embodiment can be obtained.

[0038]

As described above, in the counter device with the test function of the present invention, the counter element receives the supply of its own second latch signal and the second latch signal of the adjacent upper bit, and outputs the test signal. By providing a test operation circuit for supplying an operation signal generated in response to the supply to the first latch circuit, generation and writing of test data during a test mode operation is performed normally between the storage element inside the counter and the operation circuit. Since the test is performed with the same number of clocks as the time, a load cycle for writing test data for testing the counter function from the external test pattern generation circuit to the storage element becomes unnecessary, and the test time is shortened.

Since the count operation result based on the test data written in the counter is reflected in the test data value for the next count operation, the overflow / underflow output of the value held in the most significant bit storage element is tested. By doing so, it is possible to verify the counting operation from outside,
In order to verify the normal operation of the counter function, there is no need to read out the data of the counter storage element to the outside of the integrated circuit every time one count is completed or to output all the bits of the counter to the outside of the integrated circuit. There is an effect that no circuit is required.

Further, since the overflow / underflow detection circuit which is a bottleneck of the speed in the normal counting operation is used as it is in the test mode, the test pattern created in the test mode is used as it is for testing the operation speed of the counter. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a counter device with a test function according to the present invention.

FIG. 2 is a block diagram showing a first embodiment of a counter device with a test function according to the present invention.

FIG. 3 is a block diagram showing an example of a first conventional counter device with a test function.

FIG. 4 is a time chart showing the operation of the first conventional counter device with a test function.

FIG. 5 is a block diagram showing an example of a second conventional counter device with a test function.

[Explanation of symbols]

0-7 bit element 10-17,20-27 Latch circuit 30-37 EXOR circuit 40-47,140-147,150-157 AN
D circuit 50-56 EXNOR circuit 60-66, 70-76 Transfer gate 80-86, 90-96 Arithmetic circuit 100 Counter 101 Storage element 102 Adder 103 Pattern generation circuit 104 Selector 160-167 OR circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 31/28 H03K 21/40

Claims (4)

(57) [Claims] 1. A first count element of a most significant bit and N (positive integer) -1 second counter elements of a lower bit are each controlled by a first clock to generate a first latch signal. A first latch circuit for outputting, an exclusive OR circuit for outputting an exclusive OR signal of the first latch signal and the carry input signal, and an exclusive OR signal controlled by a second clock. A second latch circuit that outputs a second latch signal in response to the supply, and an AND circuit that outputs an AND signal of the first latch signal and the carry input signal as a carry output signal; An N-bit counter device with a test function, wherein the first and second count elements are cascaded so as to supply the carry output signal as a carry input signal of an upper bit. Receives the first count signal that is the second latch signal of itself and the second count signal that is the second latch signal of the counter element of the adjacent higher-order bit, and responds to the supply of the test signal. A test operation circuit for generating a predetermined operation signal and supplying the operation signal to the first latch circuit of the self. 2. The method according to claim 1, wherein the test operation circuit receives the second count signal at an input terminal, becomes conductive in response to the supply of the test signal, and outputs a switch signal corresponding to the second count signal. And a second switch element having an output terminal commonly connected to an output terminal of the first switch element, receiving a power supply potential at an input terminal, and becoming non-conductive in response to the supply of the test signal. The test function according to claim 1, further comprising: an exclusive NOR circuit for performing an exclusive NOR operation of the switch signal and the first count signal and outputting the operation signal. Counter device. 3. An AND circuit for receiving a supply of an inverted signal of the second count signal at one input terminal and receiving the supply of the test signal at another input terminal, and outputting a test count signal; 2. The test function according to claim 1, further comprising an OR circuit that receives the supply of the first count signal at one input terminal and receives the supply of the test count signal at another input terminal and outputs the operation signal. With counter device. 4. The first and second conductive elements of the first and second conductivity types, each of which has a drain and a source connected in parallel and receives a test signal of a first and a second polarity at each gate. 3. The counter device with a test function according to claim 2, further comprising first and second MOS transistors.