JP2874247B2 - Active matrix type display panel and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an active matrix type display panel used for an active matrix driving type liquid crystal display panel and the like, and a method of manufacturing the same, wherein an Al-Si alloy film formed on an insulating substrate is subjected to a subsequent process. In order to prevent damage even when exposed to high temperature or plasma, an aluminum / silicon alloy film is formed on an insulating substrate, and a metal film is overlaid with an insulating film on it. In the display panel having the structure described above, the composition ratio of aluminum in the aluminum-silicon alloy film is 8 to 12% by weight.
Configuration.

[Industrial applications]

The present invention relates to an active matrix type display panel such as an active matrix driving type liquid crystal display panel and a method of manufacturing the same.

In a thin film transistor matrix structure used for driving an active matrix display panel such as a liquid crystal display panel, a short circuit between a gate bus line and a drain bus line or a cross between a gate bus line and a source bus line that intersects each other via an insulating layer. There is a demand for a display screen free from defects. For this reason, there is a strong demand for preventing occurrence of short-circuit defects at intersections of bus lines.

[Conventional technology]

Active matrix drive type liquid crystal display panels
By arranging thin film transistors (TFTs) in a matrix corresponding to individual pixels that perform dot display, each pixel is provided with a memory function, enabling multi-line display with high contrast.

In such a liquid crystal display panel, for example, a large number of gate bus lines and a plurality of drain bus lines are respectively formed by X and Y lines.
The driving voltage is sequentially applied to each of the bus lines, and the thin film transistors arranged corresponding to the intersections of the bus lines are selectively driven to display desired pixels in a dot display. ing.

The structure of such a conventional thin film transistor matrix is
As shown in the plan view of FIG. 5A and the cross-sectional view of FIG. 5B [cross-sectional view taken along the line AA of FIG. 5A], for example, titanium ( A gate bus line GB and a drain bus line DB in which a Ti) film 21 and an aluminum (Al) film 22 are stacked are SiN films as gate insulating films.
3. Amorphous silicon film (a-
For example, they are disposed so as to intersect in the X and Y directions via an interlayer insulating layer 6 in which an SiO ₂ film 5 or the like as a protective film is laminated, and correspond to each intersection of both bus lines GB and DB. The TFTs 8 are arranged in a matrix.

The source electrode S of the TFT 8 is connected to the display electrode E, the gate electrode G is connected to the gate bus line GB, and the drain electrode D is connected to the drain bus line DB. In the drawing, the drain bus line DB has an example in which a chromium (Cr) film 71 and an Al film 72 are stacked.

[Problems to be solved by the invention]

By the way, in the above-mentioned conventional thin film transistor matrix, when a short circuit between bus lines occurs at the intersection of a large number of gate bus lines GB and drain bus lines DB, as is well known, a line defect occurs on the display screen. This is a fatal obstacle for a display panel.

The short-circuit failure at these intersections is mainly caused by a base failure when forming a bus line, an interlayer insulating layer, or the like, a pinhole of the interlayer insulating layer, or the like.

Such a short-circuit failure may be caused by a pre-treatment such as oxygen plasma ashing performed immediately after forming the lower bus line (the gate bus line GB in the example of FIG. 5) on the substrate and immediately before forming the interlayer insulating film 6, or In a plasma process or the like when forming the interlayer insulating film 6, the metal constituting the gate bus line GB is degraded due to segregation or crystallization of the interlayer insulating film. This phenomenon occurs particularly remarkably when Al which is a low melting point metal is used for the bus line on the substrate side.

Despite these problems, Al has a low resistivity and can reduce the resistance even if the bus line wiring is made thinner. This is a very useful metal element because the resistance of the bus line can be kept low even if the bus line width is reduced due to an increase in the required pixel size.

For this reason, conventionally, Al and silicon (Si) have been generally used for bus line wiring such as LSI. In that case, the content of silicon in the Al-Si alloy used is as low as about 3% by weight or less.

In the process of manufacturing a TFT matrix, a step of forming an interlayer insulating film on a bus line is required. When forming this interlayer insulating film, plasma chemical vapor deposition (P-CVD)
The Al—Si alloy film causes Al segregation or crystallization due to plasma treatment in the previous process or plasma or ambient temperature during formation of the interlayer insulating film, thereby causing a short circuit between bus lines.

Therefore, the present inventors have conducted various studies on a method for preventing the above process damage to the Al-Si alloy, and as a result,
It has been found that there is a close relationship between concentration and process damage.

The present invention has been made based on the knowledge obtained from the study results, and even if the Al-Si alloy film formed on the insulating substrate is exposed to plasma or high temperature in a subsequent process, damage is not caused. The purpose is to prevent receiving.

[Means for solving the problem]

In the present invention, as shown in FIG. 1, a metal film 7 serving as another wiring conductor is laminated on an Al-Si alloy film 24 serving as a wiring conductor formed on an insulating substrate 1 with an insulating film 6 interposed therebetween. In the active matrix type display panel having the combined configuration, the Al composition ratio in the Al-Si alloy film 24 was set to 8 to 12% by weight.

FIG. 1 shows that the Al—Si alloy film 24 and the metal film 7
As an example of a configuration in which the lower metal film 2 composed of a Ti film 23 and an Al—Si alloy film 24 is formed at an intersection of a bus line of an active matrix display device,
Constitutes a lower bus line (for example, a gate bus line), the upper metal film 7 composed of the Ti film 71 and the Al film 72 constitutes an upper bus line (for example, a drain bus line), This is an example in which a layer 4 and a protective film 5 constitute an insulating film 6 for insulating between layers.

(Operation)

In the thin film transistor matrix of the present invention, by setting the Si content of the Al—Si alloy film 24 to 8 to 12%, the gate insulating film or the like is formed by a plasma chemical vapor deposition (P-CVD) method in a subsequent step. In addition, even when the Al-Si alloy film 24 is exposed to plasma, the Al-Si alloy film 24 is prevented from being deteriorated, and a short circuit between the upper and lower metal films is less likely to occur.

FIG. 2 shows an Al-Si alloy constituting a gate bus line when the lower metal film 2 is a gate bus line, the upper metal film 7 is a drain bus line, and the total number of gate bus lines is 240. The composition ratio [wt%] of Si in the film 24 and P-
This shows the number of defective gate bus lines with respect to the film formation temperature [° C.] in the CVD process.

As can be seen in the figure, the composition ratio of Si in the Al-Si alloy film is
At around 10% by weight, the number of defects becomes lowest, and the defect increases when the composition ratio of Si is lower or higher.

The reason is that, when the composition ratio of Si is small, a phenomenon occurs in which Al crystallizes and whiskers grow, which penetrate an insulating film formed thereon. Conversely, when the composition ratio of Si is large, Si crystallizes and precipitates, so that the withstand voltage at that portion decreases.

As a result of various studies, the present inventors have found that there is a region in which neither Al nor Si is deposited, and that the region has a Si composition ratio of 8
~ 12% by weight. As shown in the figure, as shown in the figure, the lower the film forming temperature, the smaller the defect generation rate. In particular, when the film was formed at room temperature, almost no defect was observed.

〔Example〕

Hereinafter, one embodiment of the present invention will be described together with the manufacturing method thereof in a third embodiment.
This will be described with reference to the drawings.

In this embodiment, an aluminum / silicon alloy gate bus is formed by a sputtering method. (B) -1 to (b) -8 and (c) -1 to (c) -8 in FIG.
FIG. 2 is a cross-sectional view of a main part showing a cross section taken along line BB and a cross section taken along line CC of (a) -1 to (a) -8.

[Refer to FIGS. 3 (a) -1, (b) -1, and (c) -1] As shown in FIG. 4, a drum rotation method has three targets 51, 52, and 53, and the substrate temperature is reduced. Use a sputtering device that can raise the temperature to 200 ° C. The materials of the three targets 51, 52, 53 are Al, Ti, and Si, respectively.

First, the glass substrate 1 set in the sputtering apparatus
Is heated to about 200 ° C. by the lamp heater 56, and the rotating drum 5
5 is rotated at 6 rotations / minute, and Ti is first sputtered by DC sputtering in an Ar gas atmosphere at a pressure of about 0.001 Torr to form a Ti film 23 having a thickness of about 40 nm. Incidentally, reference numeral 54 in the drawing denotes a shutter.

Next, the glass substrate 1 is cooled to room temperature, the rotating drum is rotated at 6 revolutions / minute, and Al is sputtered by DC sputtering and Si is sputtered by RF sputtering in an Ar gas atmosphere at a pressure of about 0.001 Torr. In this step, while controlling the power so that the weight ratio of Al and Si becomes 9: 1, the two are simultaneously sputtered, and the Al-Si alloy film 24 is
It is formed to a thickness of about 80 nm.

Next, a resist film (not shown) having a pattern of the gate electrode G and the gate bus line GB to be formed is formed, and the exposed portion of the Al-Si alloy film 24 is removed by etching with a phosphoric acid-based etchant.

Next, using the above resist film as a mask, CCl ₄ (95%)
In a mixed gas atmosphere with O ₂ (5%), reactive ion etching is performed to etch the Ti film 23.

Further, using the resist film as a mask, side etching of the Al—Si alloy film 24 is performed using the above-mentioned phosphoric acid-based etchant. In this step, the etching time is controlled to such an extent that the Al-Si alloy film 24 on the gate electrode G is removed.

Thus, the gate electrode G consisting of only the Ti film 23 is formed.
Thus, a gate bus line GB composed of a laminated film of the Ti film 23 and the Al—Si alloy film 24 is obtained. However, the gate bus line GB
The upper Al—Si alloy film 24 has a reduced width due to the side etching, and is thinner than the lower Ti film 23.

Thereafter, the resist film used as the mask is removed.

[See FIGS. 3 (a) -1, (b) -2, (c) -2] Next, the substrate is heated to 300 ° C. in an oxygen (O ₂ ) and nitrogen (N ₂ ) atmosphere, and the plasma is applied. Then, the surface layer of the gate electrode G is oxidized to form a TiO ₂ film 25 which is an oxide film of a base material of the gate electrode G to a thickness of about 20 nm. At this time, the upper layer film of the gate bus line GB, Al-
The Si alloy film 24 is exposed to strong plasma.

Conventionally, in this step, the Al or Al-Si alloy film 24 is deteriorated, causing the above-described trouble.However, in the present embodiment, the Al-Si alloy film 24 has the above-described composition. Neither Al nor Si is segregated, and no alteration of the Al-Si alloy occurs.

[Refer to FIG. 3 (a) -3, (b) -3, (c) -3] Next, a SiN film (about 300 nm thick) 3 is used as a gate insulating film by a P-CVD method, and a- A Si film (about 25 nm thick) 4 and a SiO ₂ film (140 nm thick) 5 as a protective film are continuously formed.

The SiN film 3 is mixed gas atmosphere of SiH ₄ and NH _3, a-Si film 4 gas atmosphere SiH _4, SiO ₂ film 5 is formed in a mixed gas atmosphere of SiH ₄ and N ₂ O.

[Refer to FIGS. 3 (a) -4, (b) -4, (c) -4] Next, on the above-mentioned SiO ₂ film 5, the width is wider by about 5 μm on both sides on the gate bus line GB. On G, a resist film 9 having a width of about 1 μm on each side and a gap of about 5 μm between a gate bus line and a gate electrode is formed. Using this as a mask, an SiO ₂ film is formed using an ammonium fluoride-based etchant. 5 is selectively removed by etching.

[Refer to FIGS. 3 (a) -5, (b) -5, (c) -5] Further, while the resist film 9 is left, in the atmosphere of SiH ₄ doped with PH ₃ by P-CVD method. An n ⁺ a-Si film (thickness of about 50 nm) 10 is formed, followed by a Ti film (thickness of about 100 nm).
m) 71 is formed by a vacuum evaporation method.

[See FIGS. 3 (a) -6, (b) -6, (c) -6] The resist film 9 is dissolved with acetone, and the n ⁺ a-Si film 10 and the Ti film 71 on the gate electrode G are formed. Lift off.

[FIG. 3 (a) -7, (b) -7, (c) -7 reference] to form a source electrode and a resist film for the drain electrode formation (not shown), CCl ₄ (95 as a mask %) + 0 ₂
(5%) Reactive ion etching is performed in a mixed gas atmosphere to obtain a Ti film 71, an n ⁺ a-Si film 10 and a
By removing the exposed portion of the Si film 4, element isolation is performed, and a source electrode S and a drain electrode D are formed.

Note that the SiN film 3 remains on the entire surface even after performing this step.

[See FIGS. 3 (a) -8, (b) -8, (c) -8] Next, a drain bus line DB composed of an Al film (thickness: about 500 nm) 72 and an ITO film (thickness: about 200 nm) Is formed.

In the active matrix display panel of the present embodiment obtained as described above, the gate bus line GB formed on the insulating substrate 1 is not damaged even if it is exposed to plasma or heat treatment in a subsequent step. Therefore, occurrence of short circuit between upper and lower bus lines and deterioration of breakdown voltage can be prevented, and panel reliability and manufacturing yield can be improved.

〔The invention's effect〕

As described above, according to the present invention, it is possible to prevent the occurrence of a short circuit or deterioration in breakdown voltage due to deterioration of the lower metal film at the intersection of two bus lines, and to improve the reliability and manufacturing yield of the active matrix display panel.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the structure of the present invention, FIG. 2 is a diagram illustrating the principle and effects of the present invention, FIG. 3 is a diagram illustrating an embodiment of the present invention, and FIG. FIG. 5 is a view showing a device, and FIG. 5 is a diagram for explaining a problem of a conventional thin film transistor matrix. In the figure, 1 is an insulating substrate, 2 is a lower metal film, 3 is a gate insulating film, 4 is a working semiconductor layer, 5 is a protective film, 6 is an interlayer insulating film, 7 is an upper metal film, and 24 is an upper metal film. Al-Si alloy film, G
Indicates a gate electrode, GB indicates a gate bus line, and DB indicates a drain bus line.

────────────────────────────────────────────────── (5) References JP-A-57-88429 (JP, A) JP-A-60-128787 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G02F 1/1343 G02F 1/136 G09F 9/30 H01L 29/78

Claims (3)

(57) [Claims] An aluminum / silicon alloy film (24) serving as a wiring conductor is formed on an insulating substrate (1), and a metal film (7) serving as another wiring conductor is formed thereon via an insulating film (6). An active matrix display panel comprising a structure in which the aluminum-silicon alloy film has a composition ratio of 8 to 12% by weight. 2. The aluminum / silicon alloy film (24).
Is formed by a multi-source sputtering method. The method of manufacturing an active matrix display panel according to claim 1, wherein 3. The active matrix according to claim 2, wherein the step of forming the aluminum-silicon alloy film by the multi-source sputtering method is performed while maintaining the temperature of the substrate at room temperature. Method of manufacturing a type display panel.