JP2874672B2 - Automatic phase adjustment system for display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic phase adjusting system, and more particularly to a system for automatically adjusting a phase required for displaying video signals from various computers on a liquid crystal display device or the like.

[0002]

2. Description of the Related Art In a liquid crystal display device or the like, it is necessary to sample and hold an optimum point of an analog input signal and to lead each pixel to each pixel. For this purpose, it is necessary to adjust and determine the optimum point by adjusting the phase of the clock signal (dot clock) derived from the number of pixels and the horizontal and vertical frequencies.

[0003] If the phase adjustment is performed manually or the phase is adjusted by directly viewing the image, it is very difficult to achieve the optimization. For this reason, various techniques for automatically adjusting the phase have been proposed.

[0004] For example, there is an apparatus described in JP-A-6-102835. As shown in FIG. 10, the apparatus of the publication discloses a black and white signal or a color signal differentiator 13.
The comparator 14 compares the voltage differentiated by the differentiator 13 with the reference voltage 15 to detect an edge of a black-and-white signal or a color signal, and a comparison between the edge detected by the comparator 14 and the dot clock. Phase shift means for comparing the phase with the phase to correctly adjust the phase of the dot clock.

With this configuration, the monochrome signal or the color signal is differentiated, the differentiated voltage is compared with the reference voltage 15 to detect the edge of the monochrome signal or the color signal, and the detected edge and the phase of the dot clock are detected. Then, the phase of the dot clock is correctly adjusted by comparing with the above.

The phase adjusting means is provided with a dot clock (dot)
clock) generating circuit 19, a delay circuit (delayed buffer) 20 for dot clocks having a plurality of different delay time output terminals, and a counter 18 for counting the time when the edge and the peak or valley of the dot clock are in the same period. And the count number of the counter 18,
And a selection switch 21 for changing the selection of the output terminal of the delay circuit.

Incidentally, reference numeral 11 denotes an LCD (Liquid Cr).
, 12 is an analog / digital converter, 16 is an OR gate, and 17 is an AND gate.

[0008]

In the prior art described in the above-mentioned publication, since a delay circuit such as five divisions is used, the phase is adjusted stepwise. Therefore, there is a disadvantage that adjustment cannot be performed in the middle of each step, and fine phase adjustment cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has as its object to provide an automatic phase adjusting system capable of continuously adjusting the phase and sampling and holding an optimum point. That is.

[0010]

An automatic phase adjustment system according to the present invention has a conversion means for sequentially converting a video signal into a digital signal at a dot clock transition timing, and converts the converted signal to each dot on a screen. An automatic phase adjustment system in a display device for allocating and displaying an image, wherein the adjustment video signal, which alternately repeats a first signal level and a second signal level different from each other, is converted into a digital signal by the conversion means. Reference signal generating means for generating a reference signal having a voltage level corresponding to a difference between the first signal level and an ideal signal level which is an ideal level of the signal level, and according to the voltage level of the generated reference signal Phase control means for controlling the phase of the dot clock.

In short, in this system, a reference signal having a voltage level corresponding to a difference between a signal level when the adjustment video signal is converted into a digital signal and an ideal signal level which is an ideal signal level is generated. The phase of the dot clock is controlled according to the voltage level of the generated reference signal. Thus, the phase can be continuously adjusted, and the optimum point can be sampled and held.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an automatic phase adjustment system according to the present invention. In the figure, the automatic phase adjustment system includes an analog / digital converter (A / D) 1 that converts an analog video signal 100 into a digital signal at the transition timing of a dot clock 50 output from a phase adjustment unit 5, and A line memory 2 for storing the converted digital signals line by line; and a CPU (Central Processing Un) for reading the digital signals stored in the line memory 2 and controlling writing and reading of the phase adjustment unit 5 and the line memory 2.
It) 3 and the phase of the synchronizing signal 52 synchronized with the video signal are controlled according to the output 30 of the CPU 3, and the dot clock 5
And a phase adjustment unit 5 that outputs 0.
The output of the converter 1 is sent to a liquid crystal display unit or the like (not shown), and an image is displayed by being assigned to each dot on the screen.

The present automatic phase adjustment system includes a timing generator 4 for generating a write clock WCK for writing to the line memory 2. The timing generator 4 is a frequency divider for dividing the frequency of the dot clock 51 from the phase adjuster 5. Since the writing speed of the line memory 2 is limited, the dot clock 51 is frequency-divided up to the repetition frequency corresponding to the writing speed. However,
If the writing operation of the line memory 2 can correspond to the repetition frequency of the dot clock 51, the timing generator 4 is unnecessary. If necessary, a buffer may be provided between the converter 1 and the line memory 2 to adjust the writing speed.

The line memory 2 has a timing generator 4
Write clock WCK from the CPU 3
, And a read clock RCK. The waveforms of these signals and clocks are shown in FIG. In the figure, when the write enable signal WEN is at a high level, the line memory 2 performs a write operation.
Performs a read operation.

In this system, in order to perform phase adjustment,
A video signal is used in which the three primary colors, that is, the signal level of "white" having the maximum level of red, green and blue and the signal level of "black" having the minimum level are alternately repeated. When an 8-bit A / D converter is used, the level of the video signal is any value from 0 to 255. The signal level of “white” in this system is “25”.
5 ", and the signal level of" black "is" 0 ". Therefore, since the signal level of “white” and the signal level of “black” are alternately repeated, the video signals are “0”, “255”,
“0”, “255”...

Then, one line of the video is written into the line memory 2, and only one of the "white" signal level portion and the "black" signal level portion is read. For this reason,
As shown in the figure, the cycle of the read clock RCK is set to be twice the cycle of the write clock WCK,
One of the signal levels of "white" and "black" is read. The read signal level is C
The signal is input to the PU 3 and the average value of the signal levels for one line is calculated. The average value and the ideal signal level of the white level (black level) are compared in the CPU 3, and the difference signal is input to the phase adjustment unit 5.

Next, an example of the internal configuration of the phase adjustment unit 5 will be described with reference to FIG. Referring to FIG.
Is an integrator 6 that integrates the synchronization signal 52 to smooth the waveform.
And a PWM (Pulse Wi-Fi) that generates a pulse having a pulse width corresponding to the voltage level of the output 30 of the CPU 3.
dth Modulation) circuit 7, an integrator 8 that integrates the generated pulse into a substantially DC signal,
Comparator 9 which outputs a pulse having a pulse width corresponding to the result of comparison between output 60 of integrator 6 and output 80 of integrator 8
And a phase-locked loop (PLL) circuit 1 using the output 90 as a phase control input.
0 is included. Then, the output of the phase locked loop circuit 10 is sent to the A / D converter 1 and the timing generator 4 as a dot clock.

In such a configuration, the output 70 of the PWM circuit 7 is a pulse having a pulse width W as shown in FIG. This output 70 is integrated by the integrator 8 to become an output 80 which is a substantially DC signal.

The output 80 of the integrator 8 has a voltage level V
Is proportional to the pulse width W of the output 70. For this reason, PWM
As the pulse width of the output 70 of the circuit 7 increases, the voltage level of the output 80 also increases. That is, as shown in FIG. 5, the pulse width of the output 70 is larger than the pulse width W.
′, The voltage level of the output 80 becomes a larger voltage level V ′.

As shown in FIG. 6, the synchronizing signal 52 is integrated by the integrator 6 and its waveform is rounded, and the output signal 60 has a waveform that gradually falls and gradually rises. This output 60 is compared to the voltage level of output 80 described above. A period higher than the voltage level of the output 80 is a high level, and a period shorter than the voltage level is an output 90 having a low level waveform.

Here, as described above, since the voltage level of the output 80 changes in proportion to the pulse width of the output 70 of the PWM circuit 7, the phase of the output 90 changes.
That is, as shown in FIGS. 6A, 6B and 6C, when the voltage level of the output 80 changes as V1, V2 and V3, the pulse width changes and the phase changes. become. At this time, the rising and falling periods of the output 90 do not change.

That is, when the voltage level of the output 80 is the intermediate level V1 as shown in FIG. 2A, the width of the low level of the output 90 is W1. Further, when the voltage level of the output 80 is the low level V2 as shown in FIG. 3B, the width of the low level of the output 90 is narrow W2. Furthermore, FIG.
When the voltage level of the output 80 is the high level V3, the width of the low level of the output 90 is wide W3.

The output 9 whose pulse width is controlled as described above
0 is input to the PLL circuit 10. This PLL circuit 1
Numeral 0 is composed of a voltage controlled oscillator, a phase comparator, a low-pass filter and the like, and outputs a dot clock 50 phase-locked to the output 90 as shown in FIG. The output dot clock 50 is input to the A / D converter 1, and the video signal is converted into a digital signal at the transition timing (falling timing).

The operation of this conversion will be described with reference to FIG. As shown in the figure, the video signal 100 in the present system has a “white” signal level “255”.
And the "black" signal level "0" are alternately repeated. Then, this video signal is converted into a digital signal in the A / D converter 1 at the falling timing of the dot clock. The converted digital signal is written into the line memory 2 as described above, and the CPU 3 reads out only one of "white" and "black" signal levels.

If the dot clock falls at an optimum timing, the A / D converter 1 outputs "25".
"5" and "0" should be output alternately. In this case, the difference from the ideal signal level in the CPU 3 becomes zero, so that the above-described phase adjustment is not performed.

On the other hand, when the dot clock does not fall at the optimum timing, the A / D converter 1 outputs two different values other than "255" and "0" alternately. Become. And in this case, CP
Since the difference from the ideal signal level at U3 does not become zero, the above-described phase adjustment is performed to optimize the phase.

If the "white" signal level is an ideal signal level, as shown in FIG. 9, when the video signal 100 is converted at the dot clock falling timing a, the difference data becomes A. . Also, falling timing b
When the video signal 100 is converted by, the difference data becomes B,
When the video signal 100 is converted at the falling timing c, the difference data becomes C.

In this case, the CPU 3 outputs the output 30 to the PWM circuit 7 in the phase adjuster 5 according to the value of the difference data.
The value is sequentially incremented and set in a register in the CPU 3. Here, assuming that the data set in the register by the CPU 3 is 8 bits, "0" to "25"
5 "are sequentially set. The data is incremented, and when the data becomes “255”, the data returns to “0”. That is, the output 30 is:… → “254” →
“255” → “0” → “1” →... Note that the initial value of the output 30 may be set to “128” which is an intermediate value between “0” and “255”. However, it is not limited to this value.

The above-described dot clock phase adjustment is repeatedly performed until the difference data becomes zero.

The case where the video signal for adjustment alternates between white and black alternately has been described above. However, the present invention is not limited to this, and the phase can be similarly adjusted using a video signal which alternately repeats two types of signal levels. Is clear. In this case, an ideal signal level corresponding to the signal level may be prepared in the CPU. In general, "white", which is the maximum signal level of each of the three primary colors, red, green and blue, and "black", which is the minimum signal level, can be easily prepared. Therefore, these are used in this example.

As described above, according to the present system, since a delay device such as a five-divider is not used, the phase can be finely adjusted continuously, and the optimum point can be sampled and held.
Further, the labor and adjustment time required by manual operation can be reduced, that is, the speed can be increased. Further, it is possible to eliminate individual differences caused by manual adjustment and improve reliability.

The present invention can further take the following aspects in connection with the description of the claims.

(6) The reference signal generating means outputs one of the video signals.
The automatic phase according to claim 1, wherein a reference signal having a voltage level corresponding to a difference between the average value of the first signal level and the ideal signal level in a line is generated. Adjustment system.

(7) The automatic phase adjusting system according to any one of claims 1 to 6, wherein the pulse generating means generates a pulse whose pulse width changes sequentially when the difference is not zero.

[0036]

As described above, the present invention has a voltage level corresponding to the difference between the signal level when the adjustment video signal is converted into a digital signal and the ideal signal level which is the ideal signal level. By generating a reference signal and controlling the phase of the dot clock in accordance with the voltage level of the generated reference signal, the phase can be finely adjusted continuously, and the optimum point can be sampled and held. Further, there is an effect that the labor and adjustment time required by manual operation can be reduced, that is, the speed can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an automatic phase adjustment system according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of a write clock and a read clock to a line memory and a write enable signal;

FIG. 3 is a block diagram illustrating an example of an internal configuration of a phase adjustment unit 5;

FIG. 4 is a waveform diagram showing a relationship between an output of a PWM circuit and an output of an integrator.

FIG. 5 is a waveform diagram showing a relationship between an output of a PWM circuit and an output of an integrator.

FIG. 6 is a waveform chart showing an operation of the phase adjustment unit.

FIG. 7 is a waveform chart showing an operation of a PLL circuit in the phase adjustment unit.

FIG. 8 is a waveform chart showing a conversion operation in the A / D converter.

FIG. 9 is a diagram illustrating a difference between a signal level obtained by converting a video signal into a digital signal and an ideal signal level.

FIG. 10 is a block diagram showing a configuration of a conventional automatic phase adjustment system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D converter 2 Line memory 3 CPU 4 Timing generation part 5 Phase adjustment part 6, 8 Integrator 7 PWM circuit 9 Comparator 10 PLL circuit

Claims (5)

(57) [Claims] 1. An automatic phase adjustment system in a display device, comprising a conversion means for sequentially converting a video signal into a digital signal at a transition timing of a dot clock, and allocating the converted signal to each dot on a screen for display. The first signal level and the ideal level of the signal level when the adjustment video signal, which alternately repeats the first signal level and the second signal level different from each other, are converted into a digital signal by the conversion means. Reference signal generation means for generating a reference signal having a voltage level corresponding to a difference from a certain ideal signal level, and phase control means for controlling the phase of the dot clock according to the voltage level of the generated reference signal. An automatic phase adjustment system comprising: 2. The reference signal generating means includes: a pulse generating means for generating a pulse having a pulse width corresponding to the difference; and a first integrating means for integrating the generated pulse into a substantially DC signal. 2. The automatic phase adjustment system according to claim 1, wherein the integrated output is used as the reference signal. 3. The phase control means according to claim 1, wherein said phase control means integrates a synchronizing signal synchronized with said video signal with a predetermined time constant, and corresponds to a result of comparing a voltage level between said integrated output and said reference signal. 3. The apparatus according to claim 1, further comprising: means for generating a pulse having a pulse width; and phase-locked loop means for using the generated pulse as a phase control input, wherein the phase locked output is the dot clock. Automatic phase adjustment system. 4. The automatic phase adjustment system according to claim 1, wherein each of said first signal level and said ideal signal level is a maximum signal level for each of red, green and blue. . 5. The automatic phase adjustment system according to claim 1, wherein each of said first signal level and said ideal signal level is a minimum signal level of each of red, green and blue. .