JP3484958B2 - Liquid crystal display device sampling phase adjustment method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device for sampling and displaying a video output signal of a personal computer or the like.

[0002]

2. Description of the Related Art As an example of a liquid crystal display device for sampling and displaying a video output signal of a conventional personal computer or the like, for example, an optimum sampling clock as shown in the liquid crystal display device of Japanese Patent Laid-Open No. 7-219485. Attempts have been made to play. A conventional liquid crystal display device will be described below.

FIG. 5 is a block diagram of a conventional liquid crystal display device. With a sampling clock of a certain phase, some or all of the data of multiple lines of a frame,
Then, the data of the same portion after n frames is compared with the comparison circuit 1
The controller 111 determines for each horizontal scanning line whether or not they substantially match each other, and counts the number of substantially matching scanning lines.

The above operation is repeated while changing the sampling phase, and the count value and the sampling phase at that time are stored in the second memory 112. And n
The sampling phase having the largest number of scanning lines in which the data after the frame is substantially the same is adopted, and the sampling phase is used for displaying the video signal.

As a result, the phase of the sampling clock can be automatically set near the center of the pixel of the video signal, and proper sampling can be executed.

[0006]

As described above, when the phase of the sampling clock is automatically set, it cannot be set in the conventional liquid crystal display device unless the number of horizontal dots of the input signal is known. Further, even if the number of horizontal dots is known, there is a problem that the cost is increased because the frame memory (first memory 108) is used.

In view of the above problems, the present invention finely changes the phase of the sampling clock when detecting the horizontal start position and the horizontal end position of the input signal, and changes the detected value of the horizontal start value or the horizontal end value. The present invention provides a liquid crystal display device that detects the correlation with the phase of the sampling clock and obtains the optimum phase of the sampling clock without using a frame memory.

[0008]

In order to solve the above-mentioned problems, a sampling phase adjusting method for a liquid crystal display device of the present invention.
, Corresponding to the horizontal synchronizing signal of the input signal to the setting value input reproduces the dot clock the Dottoku
A PLL circuit having means for changing the lock phase, the <br/> horizontal synchronizing signal and a horizontal counter counting the number of dot clock relative to the horizontal counter when the horizontal effective display start time or end of the input signal The value of
The value of the horizontal counter is detected and the horizontal start value
Is equipped with a horizontal position detection circuit that outputs as a horizontal end value .
The horizontal start value or horizontal end value
The horizontal start value or horizontal end value changes
And the horizontal start value or horizontal end value
Calculate an intermediate value with the changing second setting value,
Is input to the PLL means as the set value.
It is characterized by adjusting the phase of the dot clock .

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION A liquid crystal display device according to the first invention of the present invention detects a horizontal start position and a horizontal end position of an input signal, and performs sampling so that the difference between them is the same as the number of horizontal effective pixels. It generates a clock and has an effect of being able to reproduce an optimum dot clock.

In a concrete liquid crystal display device of the present invention, an A / D converter which samples an input signal with a reproduced dot clock and converts it into a digital signal, and a dot clock is reproduced from a horizontal synchronizing signal of the input signal. A PLL circuit,
A horizontal counter that counts the number of dot clocks based on the horizontal synchronizing signal of the input signal, a horizontal start position detection circuit that detects the value of the horizontal counter when the horizontal effective screen of the digitized input signal is detected, and the digital counter. Horizontal end position detection circuit that detects the value of the horizontal counter at the horizontal effective screen end of the converted input signal, and the difference between the counter value at the horizontal start and the counter value at the horizontal end is calculated, and the horizontal A liquid crystal display device is driven using a CPU that controls the value of the frequency division counter of the PLL so as to match the number of effective pixels, and a horizontal synchronizing signal, a vertical synchronizing signal of the input signal, and a reproduced dot clock. It is equipped with a liquid crystal driving means that enables to reproduce an optimum dot clock. Having.

In the liquid crystal display device according to the second aspect of the present invention, when detecting the horizontal start position and the horizontal end position of the input signal, the phase of the sampling clock is finely changed, and the horizontal start value or the horizontal end value is changed. It has an effect that the correlation between the change of the detected value and the phase of the sampling clock can be detected and the optimum phase of the sampling clock can be obtained.

In a concrete liquid crystal display device of the present invention, an A / D converter which samples an input signal with a reproduced dot clock and converts it into a digital signal, and a dot clock is reproduced from a horizontal synchronizing signal of the input signal. A PLL circuit,
A horizontal counter that counts the number of dot clocks based on the horizontal synchronizing signal of the input signal, and a horizontal position detection circuit that detects the value of the horizontal counter of the digitized input signal when the horizontal effective screen starts or ends or both. A phase adjusting device for changing the phase of the sampling clock, a CPU for detecting an optimum sampling clock phase by detecting the correlation between the phase of the sampling clock and the value of the horizontal counter, and a horizontal synchronizing signal for the input signal, A liquid crystal driving means for driving the liquid crystal display element using the vertical synchronizing signal and the reproduced dot clock is provided, and it has an effect that an optimum phase of the sampling clock can be obtained.

Embodiments of the liquid crystal display device of the present invention will be described below with reference to the drawings.

(Embodiment 1) An embodiment of the liquid crystal display device of the first invention of the present invention will be described with reference to FIG.

In FIG. 1, reference numeral 1 is an input video signal, 2
Is an input synchronizing signal, 3 is an A / D converter, 4 is a PLL circuit,
5 is a horizontal counter, 6 is a horizontal start position detection circuit, 7
Is a horizontal end position detection circuit, 8 is a CPU, 9 is a liquid crystal drive circuit, and 10 is a liquid crystal display element.

The A / D converter 3 digitizes the input video signal based on the input horizontal synchronizing signal 2 according to the sampling clock clock-reproduced by the PLL circuit 4.
At this time, the PLL circuit 4 can reproduce the sampling clock having the same frequency as the dot clock frequency of the input signal if the multiplication rate is the same as the number of horizontal dots of the input signal. However, the number of horizontal dots of the input signal differs depending on the signal because the horizontal blanking ratio is different even if the number of effective screens is the same. Further, normally, the number of horizontal dots cannot be known from the input horizontal synchronizing signal and other information.

There is provided a horizontal counter 5 which reproduces the sampling clock at an arbitrary multiplication rate and counts up the clock. The horizontal counter 5 is reset by the input horizontal synchronizing signal, and the counter value corresponds to the horizontal position. When a signal with a high brightness level (for example, a white field) is applied to the input signal in the entire effective screen area, the brightness level is low during the horizontal blanking period, so the brightness signal should be above a certain value after the horizontal sync signal. The horizontal start position is when it exceeds, and the horizontal end position is when it exceeds a certain value at the end .

The horizontal start position detection circuit 6 and the horizontal end position detection circuit 7 respectively load the values of the horizontal counters of the horizontal start position and the end position and transmit them to the CPU 8. In the CPU 8, the counter value at the horizontal end position is C
a, horizontal start position counter value is Cb, horizontal is valid
Number of pixels (eg VGA: Video Graphics)
640 in the case of Array, XGA: Xtended
In the case of VGA, when 1024) is set to N, the multiplication rate of the PLL circuit 4 is set so that Ca-Cb = N. Further, it can be easily imagined that the multiplication rate should be small when Ca−Cb> N and that the multiplication rate should be increased in the opposite case.

With the above configuration, A / D conversion can be performed with the same sampling clock as the dot clock of the input signal, and a stable digital signal can be obtained. The clock recovered sampling clock drives the liquid crystal display device 10 together with the horizontal and vertical synchronization signals.
It is supplied to the liquid crystal drive circuit 9.

With this configuration, the optimum sampling clock can be reproduced without knowing the number of horizontal dots of the input signal.

(Embodiment 2) FIGS. 2, 3, and 4 show an embodiment of a liquid crystal display device according to the second invention of the present invention.
Will be explained. The same components as those of the liquid crystal display device according to the first embodiment described above are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 2, reference numeral 11 is a D / A converter for converting data from the CPU into an analog signal. FIG. 3 is an internal configuration diagram of the PLL circuit. In FIG. 3, 31 is a horizontal synchronizing signal, 32 is a phase comparator, 33 is a DC bias which is the output of D / A, 34 is the output of the phase comparator 32 and DC.
Adder for adding the bias 33, 35 a loop filter, 36 VCO, 37 clock output, 38 CPU
Is a frequency division ratio setting value, and 39 is a frequency divider. Figure 4 is CP
It is a figure showing the relation between the value of the D / A converter 11 controlled by U, and the horizontal start position detection value. Although the sampling clock is obtained in the first embodiment, the optimum sampling phase without jitter is obtained in the present embodiment.

As for the sampling phase, the D / A converter 11 and the adder 34 add a DC bias corresponding to the set value from the CPU to the output of the phase comparator 32, and the phase of the clock output 37 with respect to the horizontal synchronizing signal 31. Can be changed. Each time the phase shift of the sampling clock exceeds the clock cycle, the counter value of the horizontal counter 5 also shifts, so the horizontal start value (or horizontal end value) also shifts.

In the example of FIG. 4, when the value of D / A is 0 to 63, it is 100, and when it is 63 to 129, it is 101. ． ． ． ． Has become. The D / A value around 63 is near the signal change point,
The horizontal start value becomes unstable due to the effect of clock jitter. The point where the phase of the sampling clock is stable is the point where the signal does not change, that is, the point where the horizontal start value is stable. In the example of FIG. 4, the D / A value is around 96. Therefore, the CPU continuously changes the D / A value to obtain the optimum sampling phase by obtaining the intermediate value between the D / A value at which the horizontal start value changes and the D / A value at which the horizontal start value changes next. You can ask.

With this configuration, the optimum sampling clock phase can be obtained without using the frame memory.

[0026]

As described above, according to the liquid crystal display device of the present invention, an A / D converter for sampling an input signal with a reproduced dot clock and converting it into a digital signal, and a horizontal synchronizing signal for the input signal. PLL circuit for reproducing a dot clock from a horizontal clock, a horizontal counter for counting the number of dot clocks based on the horizontal synchronizing signal of the input signal, and a horizontal effective screen of the digitized input signal at the start or end or both of them. A horizontal position detecting circuit for detecting the value of the counter, a phase adjusting device for changing the phase of the sampling clock, a CPU for detecting the correlation between the phase of the sampling clock and the value of the horizontal counter, and obtaining an optimum sampling clock phase.
And a liquid crystal driving means for driving a liquid crystal display element by using the horizontal synchronizing signal, the vertical synchronizing signal of the input signal and the reproduced dot clock, so that an optimum sampling clock without jitter can be obtained without using a frame memory. The phase of can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing an internal configuration of a PLL circuit of the device.

FIG. 4 is a diagram showing a relationship between a D / A value and a horizontal start value of the device.

FIG. 5 is a circuit diagram of a conventional liquid crystal display device.

[Explanation of symbols]

1 video signal 2 sync signal 3 A / D converter 4 PLL circuit 5 Horizontal counter 6 Horizontal start position detection circuit 7 Horizontal end position detection circuit 8 CPU 9 LCD drive circuit 10 Liquid crystal display element 11 D / A converter 31 Horizontal sync signal 32 phase comparator 33 DC bias 34 adder 35 loop filter 36 VCO 37 Sampling clock 38 division ratio 39 frequency divider

─────────────────────────────────────────────────── --Continued from the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G09G 3/36 G09G 3/20 623

Claims (2)

(57) [Claims] 1. A dot clock is reproduced from a horizontal synchronizing signal of an input signal, and the dot clock is reproduced corresponding to an input set value.
A PLL circuit having means for changing the serial dot clock phase, and horizontal counter counting the number of dot clock based on the said horizontal synchronizing signal, detecting the value of the horizontal counter when the horizontal effective picture start of the input signal
Output the value of the horizontal counter as the horizontal start value.
A horizontal start position detecting circuit that, the setting value order
Next change, horizontal start value at each relevant set value
First set value at which the horizontal start value changes first
And the second set value at which the horizontal start value changes next
The value is calculated, and the PLL is set using the intermediate value as the set value.
Adjust the phase of the dot clock by inputting into the means
Sampling phase of the liquid crystal display device, characterized by
Adjustment method . 2. The dot clock is reproduced from the horizontal synchronizing signal of the input signal and the dot clock is reproduced in correspondence with the input set value.
A PLL circuit having means for changing the serial dot clock phase, the horizontal counter for counting the number of dot clock, detects the value of the horizontal counter when the horizontal effective picture end of the input signal relative to the horizontal synchronizing signal This
And a water <br/> flat end position detecting circuit for outputting a value of the horizontal counter as the horizontal end value, sequentially changing the setting value
Then, calculate the horizontal end value for each of the set values,
The first set value where the horizontal end value changes first and then the horizontal
Calculate the intermediate value with the second setting value where the end value changes,
The intermediate value is input to the PLL means as the set value.
A sampling phase adjusting method for a liquid crystal display device , characterized in that the phase of the dot clock is adjusted by doing so.