JP2878250B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus capable of mutually operating operands having different sizes, that is, different data bit lengths. The present invention relates to a data processing apparatus capable of performing an operation for operating operands of different sizes under an addressing system in which the most significant bit of data is stored in a small address on a memory and the least significant bit is stored in a large address on a memory. . 2. Description of the Related Art When arranging data on a memory in which an address is assigned to each byte and the bits in the byte are also numbered to indicate the order, the upper side of the data is assigned to the larger address side of the memory. There has been much debate over whether to place it on the smaller address side. A method of arranging the upper side of data at a large address in the memory and arranging the lower side of the data at a small address in the memory is called little endian. The method of arranging the lower side of the memory at a large address of the memory is called big endian. In a recent data processing apparatus, an address of a memory is generally assigned to each byte with 8 bits as 1 byte. However, when dealing with bitmap displays and bit fields with bit lengths that are not integral multiples of bytes, bit addresses that indicate bit positions are also required in addition to byte addresses, and the concept of little endian and big endian is also used for bit addresses. Exists. The byte polarity indicating whether the byte and the bit are little-endian or big-endian need not always match the bit polarity. D. Regarding whether little endian or big endian is better, or which conventional data processing device uses it.
Cohen, ■ On Holy Wars and a Plea forPeace, ■ Comput
er, VOl. 14, NO. 10, Oct. 1981, pp. 48-54. SUMMARY OF THE INVENTION [0005] Little endian,
The big-endian problem exists not only for the address of a byte or bit in memory, but also for the position of a byte or bit in a register. In a data processing device in which both the byte polarity and the bit polarity are big endian, when data having a byte length shorter than the byte length of the register is stored in the register,
FIG. 2 shows an example in which data is stored by shifting to a lower address side, as in the case of storing data on a memory. In this case, the bit address indicating the bit position is the same irrespective of the data size on the register. However, when performing an arithmetic operation such as addition between binary data having different data sizes stored in the two registers, This is problematic because the least significant bits of data are not aligned. In the arithmetic operation, it is necessary to perform the operation by aligning the least significant bit of the data. In this case, the arithmetic operation is performed by shifting the shorter size data rightward to align the larger size data with the least significant bit position. There is a need. If hardware for performing this arithmetic shift is provided in the register input / output unit or the ALU input / output unit, there is a problem that the hardware of the data processing device increases. In addition, there is a problem that the operation speed is reduced by using a machine language instruction or a microprogram. In the MC68000 series microprocessor manufactured by Motorola, USA, this problem is avoided by setting the byte polarity to big endian and the bit polarity to little endian as shown in FIG. However, in this case, since the bit polarity and the byte polarity are different, there is a problem that the load of software design is large because it is necessary to reverse the address calculation order of data when handling a byte string and a bit string. If both byte polarity and bit polarity are set to little endian, the problem of operation between operands of different sizes disappears, but the problem peculiar to little endian when handling BCD numbers and string data remains. Little-endian-specific issues are described in detail in the D. Cohen paper above. Further, when data processing devices having different byte polarities and bit polarities are incorporated in the same system, there is a problem that a coupling bus between the devices becomes complicated. An example of combining data processing devices with different byte and bit polarities is described in H. Kirrmann, ■ Data Format and Bus Compatibil
ity in Multiprocessors ■, IEEE Micro, August 1983,
pp. 32-47. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and arithmetically shifts data having different data lengths stored in a register with both byte polarity and bit polarity kept big endian. It is an object of the present invention to provide a data processing device capable of operating a bit without using an operation instruction to be operated. In the data processing apparatus according to the present invention, an instruction decoded by a decoding mechanism includes a predetermined one of a plurality of bits constituting data stored in a register. There is provided a bit operation instruction having instruction designation information for designating writing of a value, size information indicating the length of data, and a bit number indicating a bit of data to be written with a predetermined value. The register is
Complies with the rule that data of at least three types of lengths of 8 bits, 16 bits, and 32 bits can be stored, and the lower-order bits of the data are stored in higher-order bit positions of registers. And store the data. When the decoding mechanism decodes the bit operation instruction, the bit position determining mechanism outputs a bit access signal based on the size information and the bit number. Based on the bit access signal, the execution mechanism determines that the size information is 8 bits or 16 bits. , 32 bits, a predetermined value is written in the (n + 24) th, (n + 16) th, and nth bit positions of the register. In this way,
Even when handling data of different lengths, the operation of writing a predetermined value to that specific bit number can be performed correctly only by using a bit operation instruction, and multiple instructions including a shift instruction for arithmetically shifting data are executed. No need to use. Embodiments of the present invention will be described below with reference to the drawings. The apparatus of the present invention is described in detail in the title "Data Processing Apparatus" (Japanese Patent Application No. 62-247418) of the invention of the present applicant. First, the data processing apparatus of the present invention employs big endian for both byte polarity and bit polarity of data. As shown in FIG. 1, when data of a byte length smaller than the byte length of the register is arranged on the register, the bit number of the data is shifted on the register so that the least significant bit is changed regardless of the size. Align and store data. When the bit position of the data on the register is indicated, the bit position for the data on the register is set to 8 bits smaller than the bit number 8 based on the data size and the bit number indicated by the instruction. When the size is 16 bits and the bit number is n
+8 when the size is 32 bits and the bit number is n +
At 24, the same register bit position is determined. FIG. 4 is a block diagram showing the overall configuration of the data processing apparatus according to the present invention. In FIG. 4, (1) is an instruction fetch unit for sending an address to the memory (10) through the address bus (8) and fetching an instruction from the memory (10) through the data bus (9). An instruction decoding unit (2) receives an instruction from the instruction fetch unit (1), decodes the instruction, and outputs information necessary for executing the instruction. (3) is stored in the micro-ROM (7) based on information such as the microprogram entry address or general-purpose register number, operand, and data size output from the instruction decode unit (2), and is used to execute the instruction. The micro-program entry address indicating the start address of the program is output to the micro-program counter (6), and the micro-instructions output from the micro-ROM (7) and the instruction decoding unit are sequentially instructed by the micro-program counter (6). An instruction execution control unit that controls the instruction execution unit (5) based on other information output from (2) and executes the instruction. In (4), when the operand required for executing the instruction is in the memory (10), the address is transferred to the address bus.
(8) to fetch the operand through the data bus (9), or when the operand needs to be stored in the memory (10), output its address to the address bus (8) and transfer the operand to the data bus (8). This is an operand access unit that outputs to the bus (9). FIG. 5 is a block diagram showing details of the instruction execution unit (5) shown in FIG. (11) is a register file for storing data as operands. (12), (13), (1
4) and (15) are arithmetic units. An ALU (12) performs an arithmetic operation such as addition of two binary numbers and a logical operation such as a logical product of two bit strings. (16) and (17) are extension circuits for zero-extending or sign-extending the data size to the data size handled by the ALU (12) when data smaller than that of the ALU (12) is input to the ALU. . (1
3) is a barrel shifter that shifts data right or left by a plurality of bits at a time. (14) is a byte order reversing circuit for reversing the byte order of the byte sequence, and (15) is a bit order reversing circuit for reversing the bit order of the bit sequence. (18), (19), (2
(0) is the register file (11) and the arithmetic units (12), (13), (1)
4) and (15) respectively, each S1 bus,
S2 bus and D bus. Register file (11) is stored on bus (1
8), (19), (20), ALU (12) and other arithmetic units (12), (1
3), (14), and (15) are connected in 32-bit parallel. There is a one-to-one correspondence between the bit storage position of the register file (11) and the input / output bit position of the ALU (12). FIG. 6 shows the register file (11) shown in FIG.
FIG. 3 is a block diagram showing a detailed structure of FIG. (21), (22), (23)
Are the register bit positions 0 to 15 and 16
This is a circuit that stores data from 23 to 24 to 31.
Reference numeral (24) denotes a register input control circuit for controlling an input circuit at a necessary data storage position according to the size of data to be input to the register file (11) and the register number of the register to be input and storing data. (25) is the register file (11)
This is a register output control circuit for inputting a register number of a register storing data to be output for each bus from the controller and outputting data in the register to the S1 bus (18) and the S2 bus (19). Note that there are 32 portions (26) surrounded by broken lines in the register file (11) in the register file (11), and they can be distinguished from R0 to R31 in the microprogram of the data processing device of the present invention. FIG. 7 shows the byte order inversion circuit (14) shown in FIG.
FIG. 3 is a block diagram showing a detailed configuration of the embodiment. In this circuit, 4-byte data input from S2 bus (19) is
RBYI, and the data whose byte order is reversed by the wiring that intersects eight at a time is transferred to the BYO register RBY0,
The value of the YO register RBYO is output to the D bus (20). FIG. 8 shows the bit order reversal circuit (15) shown in FIG.
FIG. 3 is a block diagram showing a detailed configuration of the embodiment. In this circuit, 4-byte data input from the S2 bus (19) is
The data is input to the RBII, the data whose bit order is inverted by the crossing wiring is transferred to the BIO register RBI0, and the value of the BIO register RBIO is output to the D bus (20). FIG. 9 is a block diagram showing the configuration of some circuits included in the instruction execution control section (3) of FIG. (27) indicates the number indicating the bit position on the register on the S1 bus based on the size information and the bit number of the operand specified by the instruction.
This is a bit position number output circuit for outputting to (18). Also (2
8) is a circuit for outputting a constant 1 to the S2 bus (19).
Output {1} to the least significant bit of (19) and {0} to all other bits. Hereinafter, the operation of the data processing apparatus of the present invention will be described. Signed addition instruction that adds the 32-bit signed binary number stored in register R0 and the 8-bit signed binary number stored in register R1 and stores it in register R1 as an 8-bit signed binary number (In the data processing device of the present invention, it is expressed as "ADD R0.W R1.B", and the bit pattern of the instruction code is as shown in FIG. 10.) An operation for performing an operation between operands of different sizes will be described. The instruction is fetched from the memory (10) by the instruction fetch unit (1) shown in FIG. 4, decoded by the decode unit (2), and the decoded result is passed to the instruction execution control unit (3).
The instruction execution control unit (3) has two registers R0 and R1.
Using the two register addresses, the size of the operand stored in register R0, and the size of the operand stored in register R1 as parameters, the micro program (7) stores the entry address of the signed addition program routine stored in the micro ROM. Set the counter (6)
Read the microinstruction and execute the signed addition instruction. FIG. 11 is a flowchart showing the execution sequence of a signed addition instruction in the instruction execution control section (3). The two register numbers are input to the register output control circuit (25) independently of the microprogram, and the register R0
The data inside is transferred to ALU (12) through S1 bus (18),
The data in R1 is transferred to ALU (12) through S2 bus (19). At this time, the contents of register R1 are all 32 bits and the S2 bus
(19), the lower 8 bits of the S2 bus (19) are sign-extended by the extension circuit (17) and input to the ALU (12).
In the ALU (12), signed addition of two 32-bit signed binary numbers is performed, and a 32-bit signed binary number is output. At this time, the ALU (12) is also instructed that the register size to store the signed addition result is 8 bits, and whether the addition result can be represented by a binary number within 8 bits, or Various control flags are set according to whether the value is positive, negative or zero. The 32-bit output of the ALU (12) is transferred to the register R1 through the D bus (20). In the 32-bit data transferred by the D bus (20), only the lower 8 bits are stored in bit positions 24 to 31, which are the lower 8 bits, in the register R1 selected by the register input control circuit (24). Is done. Next, the actual operation of the embodiment will be described by taking as an example a bit set instruction for setting {1} to a bit corresponding to bit position 3 of the operand in the register R0. In the data processing apparatus according to the present invention, the bit pattern of the bit set instruction is as shown in FIG.
Also, in the data processing device of the present invention, the bit positions on the register are as shown in FIG. 1, so that this bit set instruction is "BSET # 3 R0" depending on whether the operand size is 1 byte, 2 bytes or 4 bytes. .B, BSET # 11 R0.
H, BSET # 27R0.W ". The execution sequence of the bit set instruction in the instruction execution control section (3) is shown in the flowchart of FIG. In the bit set instruction, the bit position number output circuit (27) in FIG. 14 is used to obtain the number indicating the bit position of the register. The instruction execution control unit (3) inputs the size of the operand and the bit number to the bit position number output circuit (27), and outputs the bit position number to the S2 bus (19). The bit position number output circuit (27) outputs (bit number 3 + 24 = 27) to the S1 bus (18) when the size information is 1 byte, and outputs (bit number 11 + 16 = 27) when the size information is 2 bytes. Output to the S1 bus (18). When the size information is 4 bytes, the bit number 27 is output to the S1 bus (18) as it is. The bit position number output from the bit position number output circuit (27) is transmitted through the S1 bus (18) to the barrel shifter (1).
It is input as shift number designation data in 3). At this time, the constant {1} is input to the barrel shifter (13) as the number to be shifted at the same time through the S2 bus (19). The resulting barrel shifter
From (13), a 32-bit pattern in which only bit number 27 is {1} and all other bits are {0} is output. This bit pattern is stored once in a register R16 which is a working register. Next, the ALU (12) performs a logical OR operation on the contents of the registers R0 and R16. At this time, the extension circuit (17) and the register input control circuit (24) operate in the same manner as in the case of executing the signed addition instruction according to the byte length of the operand in the register R0. Next, the operation of the byte reverse instruction for inverting the byte order of the 32-bit data in the register R0 and transferring it to the register R1 will be described. FIG. 15 shows the instruction code bit pattern of the byte reverse instruction. FIG. 16 is a flowchart showing the execution sequence of the byte reverse instruction in the instruction execution control unit (3). The 32-bit data in the register R0 is sent to the BYI register RBYI of the byte order inversion circuit (14) through the S2 bus (19), and the 32-bit data whose byte order is inverted is transferred from the BYO register RBYO to the D bus (20). Through the register R0. Next, the operation of the bit reverse instruction for inverting the bit order of the 32-bit data in the register R0 and transferring it to the register R1 will be described. FIG. 17 shows the instruction code bit pattern of the bit reverse instruction. FIG. 18 shows a flowchart of the execution sequence of the bit reverse instruction in the instruction execution control unit (3). The 32-bit data in register R0 is
The 32-bit data whose bit order has been inverted is sent from the BIO register RBIO to the register R via the D bus (20).
Entered as 0. In the above embodiment, an example has been described in which the bit position number in the register is obtained by using hardware. However, a microprogram is separately prepared for each byte length of the operand, and the bit number is determined by the microprogram. The bit position may be obtained by correction. Further, in the above embodiment, the operation function between operands of different sizes has been described by taking a signed addition instruction of operands on registers as an example. However, in all other four arithmetic operations of addition, subtraction, multiplication, and division, operands of different sizes are operated in the same manner. You can perform calculations between In the above embodiment, the byte reverse instruction and the bit reverse instruction have been described only for 32-bit data.
(14) Alternatively, if the operation in the bit order reversing circuit (15) is combined with the operation in the barrel shifter (13), the byte reverse instruction and the bit reverse instruction can be executed for data of other sizes by the microprogram. Can be. A similar effect can be obtained by executing these two instructions in a microprogram using only the ALU (12) or barrel shifter (13) and the working register. As described above, in the data processing device of the present invention, the instruction designation information for designating writing of a predetermined value to one of a plurality of bits constituting data stored in a register. And a bit operation instruction having size information indicating the length of the data and a bit number indicating the bit of the data to be written with the predetermined value, the decoding mechanism decodes the bit operation instruction, and the bit position determination mechanism converts the size information and the bit number into the size information and the bit number. When the size information is 8 bits, 16 bits, or 32 bits based on the bit access signal, the execution mechanism outputs a bit access signal based on the bit access signal.
Since a predetermined value is written in the bit positions of Nos. 4), (n + 16), and n, a predetermined value is assigned to the specific bit number by using a bit operation instruction even for data of different lengths. Bit operations to write can be performed correctly. In particular, since a program designer does not need to use an operation instruction for arithmetically shifting data, a data processing device that can easily perform bit operations without burdening software and reduce software development costs can be realized. Becomes possible.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows storage positions and bit numbers of 1-byte, 2-byte and 4-byte data stored in a 4-byte byte register of a data processing device of the present invention. FIG. FIG. 2 shows a data processing device in which both byte polarity and bit polarity are big-endian, when storing data having a byte length shorter than the byte length of a register in a register,
It is a schematic diagram which shows the example stored near the address with a small address. FIG. 3 is a schematic diagram in the case where the byte polarity is big endian and the bit polarity is little endian. FIG. 4 is a block diagram showing the overall configuration of the device of the present invention. FIG. 5 is a block diagram illustrating a configuration of an instruction execution unit. FIG. 6 is a block diagram illustrating a configuration of a register file. FIG. 7 is a block diagram illustrating a configuration of a byte order inversion circuit. FIG. 8 is a block diagram showing a configuration of a bit order inversion circuit. FIG. 9 is a block diagram illustrating a partial configuration of an instruction execution control unit. FIG. 10 is a schematic diagram showing a bit pattern of a signed addition instruction of the device of the present invention. FIG. 11 is a flowchart showing an execution sequence of a signed addition instruction. FIG. 12 is a schematic diagram of a bit pattern of an instruction code. FIG. 13 is a flowchart illustrating an execution sequence of a bit set instruction. FIG. 14 is a circuit diagram showing a configuration of a bit position number output circuit. FIG. 15 is a schematic diagram showing an instruction code bit pattern of a byte reverse instruction. FIG. 16 is a flowchart showing an execution sequence of a byte reverse instruction. FIG. 17 is a schematic diagram showing an instruction code bit pattern of a bit reverse instruction. FIG. 18 is a flowchart illustrating an execution sequence of a bit reverse instruction. [Explanation of Signs] RBYI-BYI register, RBYO-BYO register, RBII-
BII register, RBIO · · BIO register, 1 · · · instruction fetch unit, 2 · · · instruction access unit, 3 · · · instruction execution control unit, 4 · · · operand access unit, 5 · · · instruction execution unit, 6
..Micro program counter, 7..Micro ROM
, 11-register file, 12-ALU, 13-barrel shifter, 14-byte forward / reverse circuit, 15-bit forward / reverse circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-169934 (JP, A) JP-A-62-184530 (JP, A) JP-A-49-97536 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) G06F 9/30-9/355 G06F 9/40-9/42 390 G06F 7/00-7/36

Claims (1)

(57) [Claims] 1.8 bits, 16 bits, and at least 3 bits of 32 bits
A register that can store data of different lengths and stores the data in accordance with the rule that the data is stored in a bit position on the higher number side as the bit of the data becomes lower. An instruction decoding mechanism for respectively decoding a plurality of coded instructions and outputting control information corresponding to each instruction; performing an operation according to the control information from the instruction decoding mechanism; and specifying each of the plurality of instructions And a bit position determining mechanism for outputting a bit access signal for specifying a bit position of the register, wherein one of the plurality of instructions converts data stored in the register. Instruction specifying information for specifying that a predetermined value is to be written to one of a plurality of bits constituting the data; Bit operation instruction having size information and a bit number indicating a bit of the data to be written with the predetermined value, and the bit number indicates n smaller than 8. Outputting the bit access signal based on the size information and the bit number included in the bit operation instruction. The execution mechanism decodes the bit operation instruction and outputs the control information and the bit position from the decoding mechanism. According to the bit access signal output from the determination mechanism, when the size information is 8 bits, the predetermined value is written in the (n + 24) th bit position of the register, and when the size information is 16 bits, The predetermined value is written in the (n + 16) th bit position of the register, and the size information is 32 bits. Time was to write the predetermined value to the bit position of the n-th of the register, the data processing device. 2. A constant generator configured to generate constant data having the same number of bits as the number of bits of the register, wherein the execution mechanism generates the constant according to a shift number determined by a bit access signal output from the bit position determination mechanism. A barrel shifter that shifts constant data output from the device, and performs a logical operation on the shift data output from the barrel shifter and the data stored in the register, and performs a logical operation on a specific bit position of the data stored in the register. The data processing device according to claim 1, further comprising an arithmetic unit that outputs data in which a predetermined value is written.