JP2880249B2 - Communication adapter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system, particularly to a communication system suitable for multi-line communication control.

[Conventional technology]

As communication speeds increase and communication data increases in capacity, communication control methods in information processing devices such as personal computers and workstations also perform all data transmission control and data processing while the system processor controls the line controller. The system has been changed from a system in which a communication adapter is provided, a processor dedicated to communication control processing, a memory, and the like are provided in addition to a line controller in the communication adapter to reduce a load on the communication control processing of the system processor.
For example, in Japanese Patent Application No. 63-181882, "Communication Adapter Control Method and Communication Adapter" filed by the present applicant, a communication processor and a shared memory are provided in the communication adapter. Performed via shared memory. Also, a so-called gateway is realized in which two communication adapters are connected to a system processor to control two different lines and absorb a difference in protocol conversion and transmission speed between the two lines.

[Problems to be solved by the invention]

However, when controlling a plurality of lines using the above-described technology, a communication adapter is required for each line, which not only increases the scale, but also requires a system processor to control each of a plurality of distributed adapters. There is
Multiple management. Further, it is difficult to exchange information between communication processors in different communication adapters. In particular, when connecting to ISDN, three channels, for example, 2B + D, are multiplexed on one line.
Since the D channel is in charge of the call control of the two B channels, it is difficult to share each channel of 2B + D with three adapters. Further, the communication line speed of ISDN is fixed, and it is difficult to communicate with conventional terminals having various transmission speeds via ISDN.

SUMMARY OF THE INVENTION An object of the present invention is to provide a communication control method for controlling a multi-line such as ISDN simply, at high speed, and in accordance with a partner station.

[Means for solving the problem]

In order to achieve the above object, a communication adapter is provided with a plurality of communication ports and a plurality of communication processing units corresponding to the communication paths,
The communication processing units can be operated independently of each other, so that higher-level software that controls the communication adapter can replace the communication control program with the communication processing unit. Is performed.

Also, a plurality of communication protocols are provided in the communication control program, and one of the communication protocols is designated from the host software to perform communication control of the multi-line.

In addition, one of a plurality of communication protocols is automatically selected in a frame received from a communication path to perform multi-line communication control.

In addition, a shared memory accessible from both sides is provided between the communication adapter and the host software, and the communication control program is transferred via the shared memory.

Further, the transmission speed can be changed by the communication processing unit so that the transmission speed can be selected for each communication path from the host software.

[Action]

Since the host software and the communication processing unit operate independently, high-speed communication control can be performed for each communication path, and the communication procedure and transmission speed can be easily changed for each communication path. Further, since one communication control program has a plurality of communication protocols, it is possible to easily switch communication protocols.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of a multi-line communication control system employing the present invention. In FIG. 1, reference numeral 1 denotes a workstation main body.
Is equipped with a communication adapter 3, and the system processor unit 23 controls the communication adapter 3. Provide 2B + D basic interface to communication adapter 3
An ISDN line 371 for connecting to ISDN and a handset 365 for talking are connected. The ISDN line 371 can simultaneously use two B channels and one D channel for voice and data communication. In the present embodiment, the following two types are considered as modes using channels.

(A) Data communication (D channel) + data communication (B channel) + data communication (B channel) (b) Data communication (D channel) + data communication (B channel) + voice communication (B channel) In this case, the handset 365 is not always necessary.

The communication adapter 3 has three types of functions: a data communication function, a voice communication function, and a call control function.

Data communication uses all channels of the D channel, the B1 channel, and the B2 channel, and performs control up to the control of the data link layer of Layer 2 in the seven layer model of the open system interconnection (OSI). In the D channel, for example, CCITT recommendation I.441 (LAPD: Link Access Procedure on the
D-channel) to perform data communication by a packet switching method. In the B1 and B2 channels, for example, HDLC-BA (High Le
vel Data Link Control Procedure Packet switching method using balanced asynchronous balanced mode class) or HDLC-B
A, HDLC-UN (High Level Data Link Control Proc
(Edure unbalanced normal response mode class) Data communication is performed by the circuit switching method. D channel, B1 channel,
The B2 channel can, of course, independently perform data communication. The transmission speed of the D channel is 16 Kbps. B1, B
For two channels, the channel speed is fixed at 64 Kbps, but the data transmission speed can be adjusted. For example, CCIT
Speed matching is performed according to I.461 and I.463 of T Recommendation.

Voice communication is performed by selecting either the B1 channel or the B2 channel. The voice from the handset is converted to 64Kbps digital voice for communication. Sound can be recorded and reproduced by the communication adapter 3. RAMe312 in Fig. 1
Is a memory shared by the system processor unit 23 and the processor inside the communication adapter 3 and has an area for inputting and outputting audio. This is called an audio file. By connecting this audio file to the handset, you can record and play back messages locally. Audio files and IS
If you connect the DN, you can record the voice of the other party and play / send the contents of the audio file. When recording,
ADPCM (Adaptive Differential Pulse Code Modura)
Option) Converts audio from 64Kbps to 32Kbps or 24Kbps
To extend the recording time. During playback, expand
Returns to 64Kbps digital audio. Audio can be communicated simultaneously with data communication if the channel is different.

The call control uses the D channel to perform channel connection for data communication and voice communication. The control method is, for example, CC
Follow the procedures of ITT Recommendations I.441 (LAPD) and I.451.

FIG. 2 shows an example of a network utilization form to which the present embodiment is applied. Workstation (WS) 1,
11, the gateways (GW) 13 and 14 are connected to the ISDN 15 with the communication adapter 3 shown in the embodiment of FIG.
The host computer 12 has a conventional public network interface of CCITT Recommendation X.21, for example. The transmission speed is 9600 bps, which is transmitted via a terminal adapter 10 (for example, a terminal adapter HN-510 series manufactured by Hitachi, Ltd.).
Connected to 5. Host computer 12 and G
W13 and W14 do not have a handset. On the one hand, GW13,14, on the other hand, with WS16,17,18,19, local area network (L
AN), and has a role to transfer data from LAN to ISDN15 and from ISDN15 to LAN. At this time, by storing the packetized data and sending it out, for example,
It absorbs differences in transmission speed between 10Mbps LAN and 64Kbps ISDN15, and absorbs differences in communication procedures between LAN and ISDN15 by protocol conversion.

Each device connected to the ISDN 15 has three channels B1, B2, and D, and can communicate with different parties in any combination. FIG. 2 shows the following three communication modes.

(A) Inter-WS communication (b) Cluster communication (c) Inter-LAN communication In the inter-WS communication of (a), data and voice are simultaneously communicated between WS1 and WS11 using the B1 and B2 channels. Voice is naturally real-time communication.

In the cluster communication of (b), the host computer 12 communicates with the GW.
This is a 1: n communication with a plurality of WSs via 13. At this time, the GW 13 serves as a terminal control device and controls the WSs 16 and 17 operating as terminals.

In the LAN-to-LAN communication, the GW 13 and the GW 14 are logically connected by connecting the GW 13 and the GW 14 via the ISDN network 15.
It is for showing to one LAN. Thus, for example, the WS 17 can communicate with the WS 19 as if it were on the same LAN.

GW13 communicates with GW14 using one of the two channels B1 and B2 using the ISDN transmission rate of 64 Kbps as it is.
The other is to communicate with the computer 12 by putting data of 9600 bps on a channel line speed of 64 Kbps.

In FIG. 2, terminal adapter 10, gateway (G
W) 13 and 14 do not have a handset, but it is possible to attach a handset. In the case where GW13 and GW14 are installed in a remote place with respect to the host computer 12,
For example, it becomes difficult to add a WS connected to the LAN and perform a trial run, or to investigate the cause when a failure occurs. In such a case, if a handset is provided for the terminal adapter 10 and the GWs 13 and 14, the maintenance staff can easily perform the trial run and the investigation of the cause of the fault while talking with each other using the handset.

FIG. 3 is a diagram showing an example of a housing arrangement of WS1;
Here, the workstation 2050/32 manufactured by Hitachi, Ltd. is taken as an example. The main unit 101 has option slots No. 1 to No. 7, and the communication adapter 3 in FIG.
It can be mounted anywhere in the empty slot 106 of o.5.
When mounting, remove the dummy package 111 in that slot and insert it. The system processor unit 23 in FIG.
It comprises a CPU package 105, a basic memory package 109, and an optional memory package mounted in the main memory slot 110.

Next, the configuration of the communication adapter 3 in FIG. 1 will be described. The system processor unit 23 includes a CPU 2 that controls the entire main body 1 and the communication adapter 3, and a main memory 21 that stores programs and data of the CPU 2. The system processor unit 23 and the communication adapter 3 are connected to the system bus 22
Connected by The communication adapter 3 includes sub processor units 32 and 33 for performing B1 or B2 channel data communication, a main processor unit 34 for performing B channel voice communication, D channel data communication, and D channel call control, and D channel data. Performs data link layer level processing for communication and call control
The LAPD processing unit 35, the line drum 37 for multiplexing and demultiplexing the D channel, B1, and B2 channels, the B1 channel, and the B2 channel are connected to the sub processor units 32 and 33 and handsets, and audio compression and
B channel control unit 36 for performing decompression processing, speed matching unit 38, system processor unit 23, main processor unit 34, sub processor unit
It comprises a memory sharing unit 31 for exchanging data while sharing a memory between 32 and 33.

The system processor unit 23 and the memory sharing unit 31 are connected by a system bus 22. The memory share unit 31, the main processor unit 34, the sub-processor unit 32, and the sub-processor unit 33 are connected to the local bus e313 to exchange data. On the local bus a345 of the main processor unit 34,
The line driver 37, the LAPD processing unit 35, the B channel control unit 36, and the speed matching unit 38 are connected, and the main processor unit 34 controls them. 2B + D channel of ISDN line 371 is line driver 3
7 are separated and multiplexed, and the D channel of the channels is L
The B1 and B2 channels are connected to the APD processing unit 35 and the B channel control unit 36. In the B channel control unit 36, the main processor unit 34
According to the instruction, the B1 and B2 channels are transferred to the handset 365, the main processor 34, the speed
Change to 33.

Main processor section 34, sub processor sections 32 and 33, LAPD processing section 3
5 and the system processor unit 23 each have a CPU, a memory, and a bus, and can operate independently.

The main processor unit 34 includes ROMa342, RAMa343, ROMa342, and RAM.
It comprises a CPU a341 for executing the program of a343 and a controller a344, which are connected to a local bus a345. ROMa342 performs self-diagnosis of communication adapter 3 and R
It is a read-only memory that stores programs for loading programs stored in AMa343 from RAMe312, and has a capacity of 32 Kbytes. When the power of the communication adapter 3 is turned on, the CPUa341 executes the program from the beginning of the ROMa342. The RAMa 343 is a readable / writable memory for storing programs for processing voice communication and call control procedures, and has a capacity of 128 Kbytes. Controller a344
Performs path control between the local bus e313 and the local bus a345 and access control when the CPUa341 accesses the ROMa342 and the RAMa343. CPUa341 that executes ROMa342 and RAMa343
For example, an HD64180S 8-bit microcomputer manufactured by Hitachi, which operates at 10 MHz is used.

The sub processor unit 32 is a subordinate processor that operates under the main processor unit. The sub processor unit 32 is a RAMb 32
2, CPUb321 for executing the program of RAMb322, controller b324 and line 32 connected to B1 or B2 channel
6 includes a serial controller b323 for transmitting and receiving data, and these are connected to a local bus b325.
RAMb322 is a H-channel data link control procedure.
It is a read / write memory that stores programs for processing DLC-BA and HDLC-UN, and has a capacity of 32 Kbytes. The controller b324 controls a path between the local bus e313 and the local bus b325, an access control when the CPUb321 accesses the RAMb322, and a command handshake control for the main processor unit 34 to instruct the subprocessor 32 to operate or receive a report. I do. CPUb3 running RAMb322
21 and the serial controller b323 are, for example, a 1-chip 8-bit microcomputer manufactured by Hitachi, operating at 10 MHz, HD641
80S shall be used. The sub processor unit 32 has no ROM. Therefore, the main processor unit 34 downloads the program to the RAMb322 via the controller b324,
After that, the CPUb 321 is started.

The sub processor unit 33 is a subordinate processor that operates under the main processor unit. The sub processor unit 33 is a RAMc 33
2, the CPU 33 that executes the program of the RAMc 332, the controller c334, and the line 33 connected to the B1 or B2 channel
6 includes a serial controller c333 for transmitting and receiving data, and these are connected to a local bus c335.
RAMc 332 is a H-channel data link control procedure.
It is a read / write memory that stores programs for processing DLC-BA and HDLC-UN, and has a capacity of 32 Kbytes. The controller c334 controls a path between the local bus e313 and the local bus c335, an access control when the CPU c331 accesses the RAMc332, and a command handshake for the main processor unit 34 to instruct the sub processor unit 33 to operate or receive a report. Perform control. CPU that executes RAMc332
The c331 and the serial controller c333 are, for example, a one-chip 8-bit microcomputer, HD6, operating at 10 MHz.
4180S shall be used. The sub processor unit 33 has no ROM. Therefore, the main processor unit 34
Then, the program is downloaded to the RAMc332 via the CPU, and then the CPUc331 is started.

The LAPD processing unit 35 operates under the main processor unit 34.
This is a PD dedicated processing unit. LAPD processing unit 35 is ROMd352, ROMd35
2 is comprised of a CPU d351 for executing the program 2, a serial controller d353 for transmitting and receiving data to and from the D channel line 372, and a controller d354.
Connected to 55. The ROMd 352 is a read-only memory that stores a program for processing the LAPD, which is a data link control procedure for the D channel. Controller d354
The path control between the local bus a345 and the local bus d355 is performed. The LAPD processing unit 35 includes, for example, μPD72305 manufactured by NEC.
Shall be used.

The B channel control unit 36 includes a driver 364 and a line switching circuit for connecting to the ADPCM 361, the CODEC 363, and the handset 365.
362, and is controlled by the main processor unit 34 through the local bus a345. ADPCM361, B1, B2 of ISDN line 371
The 64Kbps PCM audio from the channel or the handset 365 is compressed to 32Kbps or 24Kbps and recorded on the RAMe312, or the compressed audio from the RAMe312 is expanded to 64Kbps POM audio, and
A compression / decompression circuit for sending to the 1, B2 channel or the handset 365. The CODEC 363 is a digital / analog conversion circuit that converts between 64 Kbps PCM audio and analog audio. The line switching circuit 362 connects the B1 channel 373 and the B2 channel 374 to the line 327, the line 337 or the ADPCM361 or the CODE.
It is a line switching circuit for connecting to C363 or directly connecting ADPCM361 and CODEC363. For the ADPCM361, for example, the μPD77C30 and CODEC363 manufactured by NEC use HD44278 manufactured by Hitachi, Ltd.

The speed matching unit 38 is controlled by the CPU a341 through the local bus a345, and performs speed matching between the line 327 and the line 326, and between the line 337 and the line 336.

The line driver 37 is connected to the CPUa34 through the local bus a345.
The D channel 372, the B1 channel 373, and the B2 channel 374 are separated from the multiplexed ISDN line 371 controlled and multiplexed by 1. For example, μPD98201GF manufactured by NEC Corporation is used.

The memory sharing unit 31 includes a RAM e312 and a controller e311. RAMe312 is connected to system bus 22 and local bus e
It is a read / write memory that can be accessed from both the 313 and has a capacity of 512K bytes. The controller e311 sends the RAMe from the system bus 22 and the local bus e313.
Memory contention arbitration when simultaneously accessing memory 312, main processor section 34, sub processor section 32, sub processor
Bus contention arbitration for the use request of the local bus e313 from e33, and command handshake control for the system processor unit 23 to instruct the main processor unit 34 to operate or receive a report are performed.

FIG. 4 shows the memory storage state of the RAMe 312. Start up communication adapter 3 for CPUa341, CPUb
This is performed using the transmission / reception buffer area of the CPU 321 and the CPU c331. The system processor unit 23 is located in the transmission / reception buffer area shown in FIG.
The CPUa341 program is inserted, and the CPUa341 is instructed to load a program. Loading is performed by the program in the ROMa 342, and after loading the corresponding program into the RAMa 343, the storage state shown in FIG. 4 is established.

Areas used by the CPUa341 include initialization blocks, transmission buffers and reception buffers used for D-channel data communication,
There is a voice storage area used for voice communication. Areas used by the CPU b 321 include an initialization block, a transmission buffer and a reception buffer used for B-channel data communication.

The areas used by the CPUc331 include the initialization block,
There is a transmission buffer and a reception buffer used for B channel data communication. The initial setting block is an area used to determine operating conditions between the system processor unit 23 and the communication adapter 3 at first. For example, the maximum transmission / reception data length, timeout value,
There are the position and size of the transmission buffer and reception buffer set by the adapter. The communication control program A and the communication control program B are programs executed by the CPUs b321 and c331, and are resident in the RAMe 312. Main processor 34
The communication control program can be freely exchanged by downloading to the sub-processor unit 32 or the sub-processor unit 33 as necessary.

The fault logging area stores communication errors and hardware errors occurring in the communication adapter 3 and is commonly used by the CPUa341, CPUb321, and CPUc331.

FIG. 5 shows the memory space of the four local buses 325, 335, 313, 345 inside the communication adapter 3 of FIG. 1, which is the CP connected to each local bus.
It can also be said to represent the memory space position of the hardware resource as viewed from U. The bold line in the figure indicates the location of the actual local bus, and the other local bus can see
The mapped position is as shown in the figure.

The local bus b325 has a memory space of 1 Mbyte,
The program is stored from the lowest part of the memory space 32
K bytes of RAMb322 and controller b324 are allocated, and RAMe321 is allocated at the top of the memory space. Sub-processor 32
Is a subordinate processor that operates under the main processor unit 34, so that the sub processor unit 32
And the hardware resources of the main processor unit 34 are not visible.

The local bus c335 has a memory space of 1 MB,
The program is stored from the lowest part of the memory space 32
A K byte RAMc332 and a controller c334 are allocated, and a RAMe312 is allocated at the top of the memory space. Sub-processor 33
Is a subordinate processor that operates under the main processor unit 34, so that the sub processor unit 33
And the hardware resources of the main processor unit 34 are not visible.

The local bus e313 has a space of 1 Mbyte, and allocates the controller e311 to the lowest part of the memory space and the RAMe312 to the highest part of the memory space. Also, RAMc33 which is a hardware resource of the local bus b325 and the local bus c335
Second, to make the controller c334, the RAMb322, and the controller b324 accessible from the local bus a345,
It is once mapped in the memory space of the local bus e313 as shown. The RAMb322 and the controller b324 have different memory spaces between the local bus b325 and the local bus e313.
This address conversion is performed by the controller b324. In addition, the controller c334 performs address conversion for the RAM c332 and the controller c334.

The local bus a345 has a memory space of 1 Mbyte,
ROMa342, RAMa343, controller a344, controller d345, line driver 37, ADPCM361, CO
DEC 363, controller e311, controller c334, controller b324, RAMc332, RAMb322, and RAMe312 are allocated.
Controller e311, RAMc332, Controller a344, RAMb322,
Controller b324 has local bus e313 and local bus a3
Although the memory space differs from that of the 45, this address conversion is performed by the controller a344.

FIG. 6 is a block diagram showing a configuration of the controller e311 in FIG. The controller e311 is connected to the system bus 22
, A local bus e controller 3113 for controlling the local bus e313, a RAM controller 3112 for arbitrating memory contention when the RAM e312 is simultaneously accessed from the system bus 22 and the local bus e313, and a start flag 31
15, Startup register 3116, Report flag 3118, Report register 311
7 and a local bus e contention arbitration unit 3114. The start flag 3115 and the start register 3116 are stored in the system processor unit 2
A flag indicating whether or not there is an operation instruction from 3 to the main processor unit 34, and a register for storing operation instruction information.A report flag 3118 and a report register 3117 are flags indicating a report from the main processor unit 34 to the system processor unit 23. , A register for storing report information. Local bus e contention arbitration unit
A bus access competition arbitration unit 3114 performs bus access competition for using the local bus e313 by the main processor unit 34, the sub processor unit 32, and the sub processor unit 33.

The system bus 22 and the local bus e313 are independent asynchronous buses and want to freely access the RAMe312 without being aware of each other. Therefore, the RAM control unit 3112
The access right to e312 is granted so that when one bus is accessing RAM e312, the other bus has access.

Next, an operation instruction from the system processor unit 23 to the main processor unit 34 will be described with reference to FIG.
The CPU 2 of the system processor unit 23 sets the transmission data in the RAMe 312, sets the transmission instruction operation information in the activation register 3116, and then sets the activation flag 3115. As a result, an interrupt occurs in the CPUa 341 of the main processor unit 34 via the local bus e313. In CPUa341, this interrupt causes C
Knows that operation has started from PU2. After that, CPUa3
41 saves the contents of the activation register 3116 in the RAMa 343, resets the activation flag 3115, and starts data transmission according to the operation instruction. The start flag 3115 can be read from the CPU 2, and the CPU 2 knows that the main processor unit 34 can accept the next operation instruction by resetting the start flag 3115.

This means that the main processor unit 34 receives an operation instruction from the CPU 2,
This is an interface that enables continuous acceptance without loss.

This process is executed promptly as an interrupt process asynchronously with the data communication.

Next, the receiving operation will be described. The CPUa341 instructs the LAPD processing unit 35 to store the received data in the RAMe312. The LAPD processing unit 35 receives the data according to the instruction of the CPUa341, and terminates the receiving operation.
To notify that there was an interruption. CPUa341 is L
Going to the termination state of the APD processing unit 35 and confirming that the reception has been normally performed, the reception report information is set in the report register 3117 and the report flag 3118 is set. As a result, an interrupt occurs to CPU2, and CPU2
The report information is read and the report flag 3118 is reset.
The CPUa 341 knows that the report from the main processor unit 34 can be accepted by the CPU 2 by resetting the report flag 3118.

This is an interface for enabling the CPU 2 to continuously receive the report from the CPUa341 without losing it.

The start register 3116 is a register readable / writable from the CPU 2, and the report register 3117 is a register readable / writable from the CPUa341. In both cases, reading is enabled because the CPU on the writing side performs a failure check on the register.

Next, an outline of the operation of the local bus e contention arbitration unit 3114 will be described. Bus use request signal (REQ) and use permission signal (ACK)
Are a signal requesting the main processor unit 34, the sub processor unit 32, and the sub processor unit 33 to use the local bus e313, and a signal permitting use of the local bus e313. (ADR) is 20 address signals representing a 1-Mbyte space, (DATA) is an 8-bit data signal, (AE) is an address enable signal indicating that (ADR) is enabled, (R / W) Is a read / write signal indicating the read / write direction, (RD
Y) is a ready signal for notifying that (DATA) has become valid, and these signals are common to the main processor unit 34, the sub processor unit 32, and the sub processor unit 33.

FIG. 7 shows an example of a time chart when the main processor 34 reads out and writes the RAMe 312. The use request signal (REQ
When a) is turned on, the local bus e contention arbitration unit 3114 checks the bus use status, waits for use termination if the local bus e313 is in use, turns on the use permission signal (ACKa), and turns on the main processor. The right to use the bus is given to the unit 34. In the main processor unit 34, when (ACKa) is turned on, (R /
W) Set the signal in the reading direction, output the address of the RAMe 312 to be read out to (ADR), and turn on (AE). The local bus e control unit 3113 controls the (AD) of the local bus e313.
R) constantly monitors whether or not the controller e311 or RAMe312 has been accessed. Now, (AE), (AD
When it is found from (R) and (R / W) that a read request has been made to the RAMe 312, the local bus e control unit 3113 instructs the RAMe control unit 3112 to read data from the RAMe 312. When the data is read, the local bus e control unit 3113
This is output as a (DATA) signal, and the (RDY) signal is turned on for a predetermined period. In the main processor unit 34, at the timing when the (RDY) signal is turned on, (DDY)
ATA). As for the termination method, the local bus e contention arbitration unit 3114 turns off (ACKa) when (RDY) is turned off from on, so that the main processor unit 34 (REQa), (R / W) , (AD
Turn off R) and (AE) immediately. (DATA) turns off at the timing when (RDY) turns off. After (RDY) is turned off, the local bus e313 is released after a specified time,
The next use request can be accepted.

A method of writing data from the main processor unit 34 to the RAMe 312 has the same procedure. When the use request signal (REQa) of the local bus e313 is turned on from the main processor unit 34, the local bus e contention arbitration unit 3114 checks the bus use status, and waits for the end of use if the local bus e313 is in use. Then, the use permission signal (ACKa) is turned on to give the bus right to the main processor unit 34. In the main processor section 34,
When (ACKa) is turned on, the (R / W) signal is set in the writing direction, and the address data of the RAMe 312 to be written is set to (AD
R), output to (DATA) and turn on (AE). The local bus e control unit 3113 constantly monitors whether (ADR) of the local bus e313 has accessed the controller e311 or the RAM e312. Now, (AE), (ADR)
And (R / W) indicate that a write request has been issued to the RAMe 312.
Instruct 3112 to write data to RAMe 312. In the local bus e control unit 3113, while data is being written (RD
Y) Turn on the signal. Termination method is local bus e
The contention arbitration unit 3114 turns off (ACKa) when (RDY) is turned off from on, and thereby the main processor unit 34
Then, (REQa), (R / W), (ADR) and (AE) are immediately turned off. (DATA) turns off at the timing when (RDY) turns off. After (RDY) is turned off, the local bus e313 is opened at a specified time, and the next use request can be accepted.

The controller e311 shown in FIG.
RAMe312 has a position designation function and a slot identification function.

The adapter identification function is such that a plurality of identical adapters can be mounted on one workstation, or can be used in combination with different adapters. An identification code is assigned to the adapter itself in advance, and this can be read from the system processor unit 23. In FIG. 6, when the controller e311 is mounted on the communication adapter 3, an adapter ID signal 3119 is input from the adapter board to the controller e311. When the CPU 2 issues a request to read an adapter ID through the system bus 22, the system bus control unit 3111
The signal is sent to CPU2 as it is. In this embodiment, the adapter ID
For example, the binary "1011" is used.

The RAMe position designation function uses the RAMe312
Is capable of dynamically locating an address seen from the system processor unit 23. A RAMe pointer is provided in the system bus control unit 3111 shown in FIG. The RAMe pointer is a register indicating the head position of the RAMe 312 viewed from the system bus 22, and is set first by the system processor unit 23. After setting, the system bus controller 31
At 11, the address of the system bus 22 is compared with the RAMe pointer, and the RAMe pointer is
A read / write request to 312 is made.

The slot identification function is such that the communication adapter 3 can be inserted into a plurality of slots prepared in one workstation regardless of the slot. In FIG. 6, each slot is provided with a unique slot number 221 in addition to the signal of the system bus 22. The system bus control unit 3111 inputs the slot number 221 and changes the addresses of various registers viewed from the system processor unit 23 according to the number. The registers visible from the system processor unit 23 include an adapter ID, a RAMe pointer, a start flag 3115, a start register 3116, a report register 3117, and a report flag 3118 in FIG. For example, as shown in FIG. 8, the slot number 0 is "F3" in hexadecimal for the system bus 22 having a memory space of 16 Mbytes.
0000-F31FFF ", and every 8K bytes thereafter.

FIG. 9 is a block diagram showing the configuration of the controller b324 in FIG. The controller b324 is connected to the local bus e3
Local bus control unit 3241 that controls 13 Local bus b32
5 local bus b control unit 3247, start flag 324
3, start register 3244, report flag 3246, report register 3245
And an address conversion unit 3242. The start flag 3243 and the start register 3244 are flags that indicate the presence or absence of an operation instruction from the main processor unit 34 to the sub-processor unit 32, and registers that store operation instruction information. The report flag 3246 and the report register 3245 are the sub-processor units. This is a register that stores a flag indicating report from the 32 to the main processor unit 34 and report information.

The address conversion unit 3242 transfers the RAMb322 to the local bus e313.
When accessing from the local bus b3 shown in FIG.
Performs address translation to 25. Since only access from the local bus e313 to the local bus 325 is permitted, the arrow is unidirectional.

Next, an operation instruction from the main processor unit 34 to the sub-processor unit 32 will be described with reference to FIG. 9, taking transmission as an example. The CPUa 341 of the main processor unit 34 sets the transmission data in the RAMe 312 and sets the transmission instruction operation information in the activation register 3244, and then sets the activation flag 3243. This allows the local bus
An interrupt is generated in the CPU b321 of the sub processor unit 32 via b325. The CPUb321 knows that the operation is started from the CPUa341 by this interrupt. After that, the CPUb 321 saves the contents of the start register 3244 in the RAMb 322, resets the start flag 3243, and starts data transmission according to the operation instruction contents. The activation flag 3243 can be read from the CPUa341, and the CPUa341 knows that the sub-processor unit 32 can accept the next operation instruction by resetting the activation flag 3243.

This is an interface for enabling the sub-processor unit 32 to continuously accept the operation instruction from the CPUa 341 without losing it.

This process is executed promptly as an interrupt process asynchronously with the data communication.

Next, the receiving operation will be described. The CPU b321 instructs the serial controller b323 to store the received data in the ARMe 312. Serial controller b323
When receiving the data according to the instruction of the CPUb321 and ending the receiving operation, the CPUb321 notifies the CPUb321 of the reception by an interrupt. When checking that the serial controller b323 has been properly received by checking the termination state of the serial controller b323, the CPU b321 sets the reception report information in the report register 3245 and sets the report flag 3246. This causes an interrupt to the CPUa341, and the CPUa341 reads the report information of the report register 3245 and resets the report flag 3246. CPUb321
Knows that the report flag 3246 has been reset, so that the CPUa 341 can accept the next report from the sub-processor unit 32.

This is an interface for enabling the CPUa341 to continuously receive the report from the CPUb321 without losing it.

The start register 3244 is a register readable / writable from the CPUa341, and the report register 3245 is a register readable / writable from the CPUb321. In both cases, reading is enabled because the CPU on the writing side performs a failure check on the register.

Signal 3248 is a controller ID for identifying controller b324 and controller c334. Controller b324
And the controller c334 are the same circuit, and the controller ID is
The two are identified by 3248. Local bus e control unit 3241
Then, it is determined whether a write / read request has been made from the local bus e313 to the sub-processor unit 32 using the controller ID 3248. The address conversion unit 3242 performs an address conversion as shown in FIG. 5 using the controller ID 3248. Note that the controller ID 3248 can also be read by the program of the sub processor unit 32 through the local bus b control unit 3247.

FIG. 10 is a block diagram showing a configuration of the controller c334 in FIG. The controller c334 is connected to the local bus e3
Local bus e control unit 3341 that controls 13 Local bus c
Local bus c control unit 3347 for controlling 335, start flag 33
43, start register 3344, report flag 3346, report register 334
5, comprising an address conversion unit 3342. The start flag 3343 and the start register 3344 are transmitted from the main processor unit 34 to the sub processor unit.
This register stores a flag indicating the presence or absence of an operation instruction to 33, and operation instruction information.
A register 345 stores a flag indicating a report from the sub processor unit 33 to the main processor unit 34 and report information.

The address conversion unit 3342 transfers the RAMc 332 to the local bus e313.
When accessing from the local bus c3 shown in FIG.
Performs address translation to 35. Since only access from the local bus e313 to the local bus c335 is permitted, the arrow is unidirectional.

Next, an operation instruction from the main processor section 34 to the sub-processor section 33 will be described with reference to FIG. The CPUa 341 of the main processor 34 sets transmission data in the RAMe 312 and sets transmission instruction operation information in the activation register 3344, and then sets the activation flag 3343. This allows the local bus
An interrupt is generated in the CPU c331 of the sub processor unit 33 via c335. The CPUc331 knows that the operation has been started from the CPUa341 by this interrupt. Thereafter, the CPU c331 saves the contents of the activation register 3344 in the RAMc332, resets the activation flag 3343, and starts data transmission according to the operation instruction. The activation flag 3343 can be read from the CPUa341, and the CPUa341 knows that the sub-processor 33 can accept the next operation instruction by resetting the activation flag 3343.

This is an interface for enabling the sub-processor unit 33 to continuously accept the operation instruction from the CPUa 341 without losing it.

This process is executed promptly as an interrupt process asynchronously with the data communication.

Next, the receiving operation will be described. The CPU c331 instructs the serial controller c333 to store the received data in the RAMe312. Serial controller c333
After receiving the data according to the instruction of the CPU c331 and terminating the receiving operation, the CPU c331 notifies the CPU c331 of the reception by an interrupt. When checking that the serial controller c333 has been properly received by checking the termination state of the serial controller c333, the CPU c331 sets the reception report information in the report register 3345 and sets the report flag 3346. This causes an interrupt to the CPUa341, and the CPUa341 reads the report information of the report register 3345 and resets the report flag 3346. CPUc331
Knows that the report flag 3346 has been reset, so that the CPUa 341 can accept the next report from the sub-processor unit 33.

This is an interface for enabling the CPUa341 to continuously receive the report from the CPUc331 without losing it.

The start register 3344 is a register readable / writable from the CPUa341, and the report register 3345 is a register readable / writable from the CPUc331. In both cases, reading is enabled because the CPU on the writing side performs a failure check on the register.

Signal 3348 is a controller ID for identifying controller b324 and controller c334. Controller b324
And the controller c334 are the same circuit, and the controller ID is
The two are identified by 3348. Local bus e controller 3341
Then, it is determined whether a write / read request has been received from the local bus e313 to the sub-processor unit 33 using the controller ID 3348. The address conversion unit 3342 performs an address conversion as shown in FIG. 5 using the controller ID 3348. Note that the controller ID 3348 can be read by a program of the sub processor unit 33 through the local bus c control unit 33.

FIG. 11 is a block diagram showing a configuration of the controller a344 in FIG. Controller a344 is connected to local bus e3
Local bus e control unit 3441 that controls 13 Local bus a
It comprises a local bus a control unit 3443 for controlling the 345, an address conversion unit 3442, and an interrupt control unit 3444. Address converter 3
Reference numeral 442 performs address conversion to the local bus e313 shown in FIG. 5 when the CPU a341 accesses the controllers e311, RAMc332, controller c334, RAMb322, and controller b324. Since the access is unidirectional from the CPUa341, the arrow is unidirectional. The interrupt control unit 3444 includes an interrupt signal INTe from the start flag 3115 in the controller e311 and an interrupt signal from the start flag 3243 in the controller b324.
Six interrupts, INTb, an interrupt signal INTC from the start flag 3343 in the controller c334, a reception end interrupt signal from the CPU d351, an abnormality notification interrupt signal from the line driver 37, and an ADPCM end interrupt signal from the DMA control unit incorporated in the CPUa341 Control. The ADPCM end interrupt in the interrupt signal is used for audio registration and playback.
Use a combination of the built-in DMA controller and ADPCM361. The CPUa341 sets the registration / playback time in the DMA control unit in the number of bytes, and activates the DMA control unit and the ADPCM361. The DMA control unit transfers the compressed sound from the ADPCM 361 to the RAMe 312 during recording, and transfers the compressed sound from the RAMe 312 to the ADPCM 361 during reproduction. In any case, ADP is sent to CPUa341 when transfer is completed.
Generates CM end interrupt signal. This makes it possible to automatically input and output voice without using a program.

The six interrupt signals are logically ORed by the interrupt controller 3444, and when any of the signals is turned on, the local bus
An interrupt is generated to CPUa341 via a345. Upon receiving the interrupt, the CPUa341 reads the interrupt factor from the interrupt control unit 3444 through the local bus a control unit 3443,
Performs processing for the interrupt that has occurred. When a plurality of interrupts occur at the same time, the CPUa341 assigns a priority, and masks the low-priority interrupt by the mask register of the interrupt control unit 3444 so as to wait.

FIG. 12 is a block diagram showing a configuration of the line switching circuit 362 in FIG. The line switching circuit 362 includes the registers 3621 and B1
It comprises a channel selection circuit 3622 and a B2 channel selection circuit 3623. The register 3621 is a register for storing B1 channel and B2 channel switching information, and is used to store the CPUa via the local bus a345.
Set from 341. The register 3621 is an 8-bit register, and the register information is input to the B1 channel selection circuit 3622 and the B2 channel selection circuit 3623 in 4-bit units. The B1 channel selection circuit 3622 connects the B1 channel 373 separated by the line driver 37 to one or more of the line 326 of the serial controller b323, the line 336 of the serial controller c333, the CODEC 363, and the ADPCM 361 according to the contents of the register 3621. I do. Similarly, the B2 channel selection circuit 3623 separates the B2 channel 374 separated by the line driver 37.
To the lines 327 and 33 according to the contents of the register 3621.
7, Connect to one or more of CODEC363 and ADPCM361. The lines connected by the B1 channel selection circuit 3622 and the lines connected by the B2 channel selection circuit 3623 are respectively ORed. The B1 or B2 channel can be connected to the handset 365 and simultaneously recorded to the RAMe 312. In this case, the register 3621 is binary “11000000” or “0000110”.
0 "may be set. When recording / reproducing locally with the handset 365 and the RAMe 312," 11000000 "or" 00001100 "is set to the register 3621 in the same manner as described above, and the line driver 37 is set. It may be instructed to open the B1 channel 373 or the B2 channel 374 and disconnect from the ISDN line 371.

FIG. 19 is a block diagram showing a configuration of the speed matching unit 38 of FIG. The speed matching unit 38 includes a ROM 381 and a matching processing unit 388. The matching processing unit 388 includes a ROM access control unit 382, an upper interface control unit 383, a transmission speed conversion unit A384 that performs speed matching between the line 337 and the line 336, and a reception unit. It comprises a speed conversion unit A385, a transmission speed conversion unit B386 and a reception speed conversion unit B387 that perform speed matching between the lines 327 and 326. Here, the flow of data from this communication adapter in the ISDN direction is called transmission, and the reverse direction is called reception.

Next, an outline of the speed matching method of FIG. 19 will be described. Speed matching is performed by a conversion procedure conforming to the speed matching specifications specified in CCITT Recommendations I.463 and I.461. The target of speed matching is
It is transmission / reception data of the B1 channel and the B2 channel, and performs speed conversion independently. 600bps, 1200bps for conversion speed
Are instructed from the main processor 34 in FIG. 1 to the speed converters 384 to 387 via the local bus a345. Speed conversion is performed in two stages, conversion 1 and conversion 2. However, conversion 1 is not performed at 32 Kbps or more. In the conversion 1, conversion is performed between ISDN 64Kbps serial data and intermediate speed data. The transfer speed of the intermediate speed data is finally matched and the
It is determined by the matching speed of the speed matching serial data which becomes 2,33 data. For example, if the matching speed, or conversion speed, is
In the case of 4800bps, the intermediate speed becomes 8Kbps. This is 64Kbps
It is realized by thinning out ISDN serial data to 1/8. In the conversion 2, the intermediate speed data converted in the conversion 1 and the speed matching serial data are converted. Conversion follows the conversion format stored in the ROM 381. The conversion format differs for each matching speed. For example, in the case of 4800 bps, the conversion format is as shown in FIG. The intermediate speed data is arranged in the order of bit number 1 of octet number 0 to bit number 2 of octet number 0 bit number... Octet number 0 bit number 8... Octet number 9 bit number 8, and 80 bits are converted as one frame. In the frame structure shown in FIG. 20, 17 bits of octet number 0 (bit values are all 0) and bit number 1 (bit value 1) of octet numbers 1 to 9 are frame synchronization bits. Is recognized as a frame when a bit pattern such as Fig. 20
E ₁ to E ₇ bits are bits for checking the matching speed. The D bit in FIG. 20 is serial data whose speed has been matched, and is output in the order of D ₁ , D ₂ ... D ₄₈ . That is, while the transmission speed of ISDN is 64 Kbps, 8 Kbps of 1/8 at the intermediate speed
Is decelerated, which D ₁ to D from the frame 80 bits
Decimation of ₄₈ to 48 bits eventually results in a speed of 4800 bps. Eight bits of the S bit and the X bit in FIG. 20 are status bits used for transmitting line control information. For example, when communicating terminal having a CCITT Recommendation V.24 interface to the other, S ₁ bit, for transmission V.24
It becomes a data set ready signal of the circuit 107, and becomes a data terminal ready signal of the V • 24 circuit 108 for reception. This status bit can be processed by the sub-processor units 32 and 33 together with the speed matching serial data. In this case, however, the processing is performed by the main processor unit 34 that controls the communication adapter 3. The transmission status bits of the B1 channel and the B2 channel are both sent from the main processor unit 34 to the speed matching unit 38 via the local bus a345, and the reception status bits of the B1 channel and the B2 channel received by the speed matching unit 38 are inverted. Then, it is sent to the main processor section 34 via the local bus a345.

Next, a specific method of speed matching will be described with reference to FIG.

The two transmission rate converters 384 and 386 have the same configuration and
The two receiving speed converters 385 and 387 have the same configuration. Also,
The transmission method is the same as that of the transmission speed conversion unit and the reception speed conversion unit except that the data direction is reversed. Here, the reception speed conversion unit A385 will be described as a representative. Receiving speed converter
The A385 has a speed register, a status register, a first converter, a second converter, and a ROM address generator. The speed register is a register for storing the conversion speed, and the main processor unit 34 sets a speed value via the upper interface control unit 383. The status register is a register for storing the status bits extracted from the received frame, and this value is reported to the main processor unit 34 via the upper interface control unit 383 as necessary. The first converter creates intermediate speed data while thinning out the received signal from the line 337 according to the value of the speed register, and outputs this to the second converter. Second
The conversion unit creates a frame from the intermediate data in accordance with the value of the speed register, and sequentially sends an octet number and a bit number to the ROM address generation unit in order to process each bit in the frame according to the contents of the ROM 381. The ROM address generator determines the ROM address based on the speed information from the speed register and the octet number and bit number from the second converter, and sends this to the ROM access controller 382. The ROM access control unit 382 reads the information of the ROM address position from the ROM 381. The read ROM information is passed to the second conversion unit through the ROM address generation unit. The second conversion unit is a ROM
The status bit is output to the status register and the data bit is output to the line 336 according to the information.

The upper interface controller 383 in FIG. 19 communicates with the main processor 34 and the speed converters 384 to 3 via the local bus a345.
Controls the transfer of data to and from 87. The data from the main processor unit 34 includes speed information and reception status information, and the main processor unit 34 transmits the speed information to one of the speed registers of the four speed conversion units 384 to 387 as necessary, and transmits the transmission status information. The data is sent to one of the status registers of the transmission speed conversion units A384 and B386. Main processor
The data to 34 includes reception status information, and the main processor unit 34 controls the reception speed conversion units A385 and B387 as necessary.
Read from any of the status registers.

The ROM access control unit 382 reads the ROM in response to requests from the four speed conversion units 384 to 387. The transmission signal and the reception signal of the line 337 and the transmission signal and the reception signal of the line 327 are all synchronized at a bit timing of 64 Kbps,
The four speed converters also operate at this bit timing.
Therefore, the RO from the speed conversion unit to the ROM access control unit 382
An M access request also occurs at the same time.

On the other hand, the read position of the ROM has four speed conversion units 384 to 38.
7 different each. Therefore, the ROM access control unit reads the ROM 381 in a time-division manner and sends it to the speed conversion unit when the four ROM data are completed.

The ROM 381 stores the processing contents of each bit in the frame structure shown in FIG. ROM in Figure 21
An example of the content is shown. The ROM has a capacity of 2 Kbytes, which is divided into four for the speed converter, and further divided into four according to the conversion speed. This unit area becomes one frame structure data. The reason why two or more conversion speeds are written in one area is that the frames have the same structure except for the intermediate speed. One area has a capacity of 16 octets × 8 bits. The data describes the processing contents of one bit in one byte unit. For example, for transmission data, speed matching data, transmission status data,
Either “0” or “1” fixed data is selected, and for received data, either speed matching data or reception status data is selected and described.

As described above, since the speed conversion is performed using the ROM, the frame structure can be easily changed only by converting the ROM. Further, in the example of FIG. 21, the conversion rule data is provided for each speed conversion unit, but it is also possible to use one data corresponding to the conversion speed.
Capacity can be kept small.

Also, the transmission rate of the received data can be known by determining the E bit after the frame rate as shown in FIG. 20 is created in the reception rate conversion unit. By operating the speed conversion unit at the recognized transmission speed, it becomes possible to automatically perform speed matching without an instruction from the main processor unit 34.

FIG. 13 is a diagram showing an example of mounting the communication adapter 3 of FIG. The communication adapter 3 is housed on a board 50 having a size of 335 mm × 100 mm. In the figure, Xta11 is a 19.6608 MHz crystal oscillator, and the waveform is shaped by the controller e311 and the CPUa341,
Output to three CPUs CPUb321 and CPUc331. Xta12 is 16.38
This is a 4MHz crystal oscillator. The waveform is shaped by the controller a344, divided by 2, and the 8.192MHz clock is sent to the ADPCM361 and CPUd.
Output to 351. Note that the one-chip CPU d 351 is
Are all contained on one chip. Xta13 is 12.288M
Hz crystal oscillator, which is directly connected to the line driver 37. Horizontal or vertical rectangular components are module-type pull-up resistors for driving circuits. The relay operates when the communication adapter 3 is not energized.
For disconnecting the ISDN line 371 from the network. The two pulse transformers are used to cut the DC components of the transmission signal and the reception signal and to perform AC coupling. Anonymous IC
Is a multiplexer circuit for supplying a part of the address signals of the system bus 22 and the local bus e313 to the RAM e312, and a circuit for directly connecting a part of the address signals of the local bus e313 and the local bus a345. The communication adapter 3 includes a line connector 52 for connecting an ISDN line 371, a handset connector 53 for connecting a handset 365, and a main body connector 51 for connecting to the workstation 1 main body. When the communication adapter 3 is inserted into the empty slot of the workstation 1, the communication adapter 3 is electrically and logically connected to the system processor unit by the connector of the main body.
Connect with 23.

FIG. 14 is a flowchart showing an operation example when the communication adapter 3 starts up. When the power of the communication adapter 3 is turned on, the CPUa 341 of the main processor 34 executes the program of the ROMa 342 from address 0. On the other hand, when the power is turned on, the controller b324 and the controller c334 continue to issue resets to the local bus b325 and the local bus c335.
Both CPUb321 and CPUc331 are in a stopped state. CPUa341
Performs a read / write check on all memories and registers accessible from the CPU a341 in step A1, reports a check result to the CPU 2 through the controller e311 in step A2, and waits for activation from the CPU 2 in step A3. When a program loading operation instruction is received from the CPU 2, the CPU a341 proceeds from the RAMe 312 to the RAMa 343 in step A4.
When the loading is completed, in step A5, a loading completion report is returned to the CPU 2 and the program jumps to the loaded RAMa343 program. In the program of RAMa343, in step A6, CPUa341
Then, an interrupt to the server is made ready to be accepted, and in step A7, an interrupt waiting state is set.

FIG. 15A is a flowchart of an interrupt process from the CPU 2. All startup of CPUa341 from CPU2 is interrupt INT
Receive with e. When the CPUa341 receives the “CPUb program loading” activation from the CPU2, the specified communication control program A or B is transferred from the RAMe312 to the RAMb322 in step B1, and after the transfer is completed, the local bus b325 is transferred to the controller b324 in step B2. Instruct to cancel reset. As a result, the CPUb 321 executes the program in the RAM b 332 from address 0. When loading is completed and CPUb321 is started, the CPU
In step B3, a341 reports to the CPU2 that the program loading has been completed, returns to step A7 after exiting the interrupt processing, and waits for the next interrupt.

CPUa341 “CPUc program loading” from CPU2
Upon receiving the activation, in step B5, the designated communication control program A or B is transferred from the RAMe 312 to the RAM c332, and after the transfer is completed, in step B6, the controller c334 is instructed to release the reset of the local bus c335. This allows the CP
Uc331 executes the program of RAMc332 from address 0. When loading is finished and CPUc331 is started, CPUa341
At step B7, the CPU 2 is notified of the end of the program loading, and the process returns to step A7 after exiting the interrupt processing, and waits for the next interrupt.

As described above, the sub processor unit 32 and the sub processor unit
At 33, either the communication control program A or B on the RAMe 312 can be executed. Fig. 16 shows the loading. In the present embodiment, the method of copying the communication control program from the RAMe 312 to the RAMb322 or RAMc332 is adopted.
Can be executed by the two sub-processor units 32 and 33, respectively. For example, one communication control program A can be executed by both the two sub-processor units 32 and 33.

When the CPUa341 receives the “CPUb transmission” activation from the CPU2, the CPUa341 activates the “transmission” activation to the sub processor unit 32 in step B4.
After exiting the interrupt processing, the process returns to step A7 and waits for the next interrupt. The transmission data is stored in the CPUb transmission buffer of the RAMe 312. The transmission end report to the CPU 2 is made in the INTb interrupt processing.

When the CPUa341 receives the “CPUc transmission” activation from the CPU2, the CPUa341 activates the “transmission” activation to the sub-processor unit 33 in step B8.
After exiting the interrupt processing, the process returns to step A7 and waits for the next interrupt. The transmission data is stored in the CPUc transmission buffer of the RAMe 312. The transmission end report to the CPU 2 is made in the INTc interrupt processing.

When the CPUa341 receives the "call setting" activation from the CPU2, the call control processing is performed in accordance with CCITT recommendation I.451 in step B9, and in step B10, the "call setting" activation is performed on the LAPD processing unit 35 to exit the interrupt processing. Return to the original step A7,
Wait for the next interrupt. Detailed information for call setup can be found in RAMe
312 are stored in the CPUa transmission buffer. The call setting completion report to the CPU 2 is made in the INTd interrupt processing.

When the CPUa341 receives the "D channel packet transmission" activation from the CPU2, the CPUa341 activates the "packet transmission" to the LAPD processing unit 35 in step B11, returns to step A7 after exiting the interrupt processing, and waits for the next interruption. . The transmission data is RA
It is stored in the transmission buffer for CPU3a of Me312. The D-channel packet transmission completion report to the CPU 2 is made in the INTd interrupt processing.

When the CPUa341 receives the "rotation driver" startup from the CPU2, it instructs the line driver 37 to activate the ISDN line in step B12, and in step B13, reports the completion of the line driver startup to the CPU2, and executes the interrupt processing. The process returns to the original step A7 and waits for the next interrupt. In the line driver 37, the IS
Enable the DN line.

When the CPUa341 receives the "CODEC" activation from the CPU2, the operation mode is set in the CODEC363 in step B14, and the operation mode is set in step B1.
Then, a completion report is sent to the CPU 2 and the process returns to the original step A7 after exiting the interrupt processing, and waits for the next interrupt. The operation mode information for the CODEC 363 is stored in the CPUa initialization block of the RAMe 312.

When the CPUa341 receives the “ADPCM” activation from the CPU2, in step B16, the operation mode is set in the ADPCM361 and the DAM control unit built in the CPUa341, and the process exits from the interrupt processing.
Return to A7 and wait for the next interrupt. The operation mode information is CP
Start register in controller e311 when U2 starts
Store in 3116. The ADPCM completion report to the CPU 2 is made in the interrupt processing from the DMA control unit built in the CPUa341.

When the CPUa341 receives the "line switching" activation from the CPU2, it sets the switching information in the line switching circuit 362 in step B17, reports the completion to the CPU2 in step B18, and goes to the original step A7 after exiting the interrupt processing. Return and wait for the next interrupt.
The line switching information is passed by the activation register 3116 of the RAMe 312.

Steps B19, B20, and B21 are processing for the speed matching unit 38. In response to an instruction from the CPU 2, the CPUa341 sets the conversion speed information in step B19 and the transmission status information in step B20 to the speed matching unit 38. The information to be set is passed by the activation register 3116 of the RAMe 312. In step B21, the speed matching unit 38
Reads the reception status information from the
To CPU2. The process returns to step A7 at the end of the process, and waits for the next interrupt.

FIG. 15 (b) is a flowchart of an interrupt process from the sub processor unit 32.

When CPUa341 receives “transmission complete” activation from CPUb321,
In step C1, the CPU notifies the CPU 2 of the completion of transmission, returns to step A7 after exiting the interrupt processing, and waits for the next interrupt.

When the CPUa341 receives the "reception" report from the CPUb321, it reports to the CPU2 in step C2 that there is a reception, returns to step A7 after exiting the interrupt processing, and waits for the next interrupt. The reception data is stored in the CPUb reception buffer of the RAMe312. The detailed reception information such as the data position and the data length is stored in the report register 3245 of the controller b324, which is copied to the report register 3117 of the controller e311 and notified to the CPU 2.

FIG. 15 (c) is a flowchart of an interrupt process from the sub processor unit 33.

When the CPUa341 receives the "transmission complete" activation from the CPUc, it reports the completion of transmission to the CPU2 in step D1, returns to step A7 after exiting the interrupt processing, and waits for the next interrupt.

When the CPUa341 receives the "reception" report from the CPUc331, in step D2, it reports that the reception has been made to the CPU2, returns to step A7 after exiting the interrupt processing, and waits for the next interrupt. The reception data is stored in the reception buffer for CPUc of the RAMe312. The reception detailed information such as the data position and the data length is stored in the report register 3345 of the controller c334, and is copied to the report register 3117 of the controller e311 and notified to the CPU 2.

FIG. 15D is a flowchart of an interrupt process from the LAPD processing unit 35.

When the CPUa341 receives the "packet transmission completion" report from the LAPD processing unit 35, it reports the completion of the D-channel packet transmission to the CPU2 in step E1, returns to step A7 after exiting the interrupt processing, and returns to the next interrupt. Wait for.

When the CPUa341 receives the "reception" report from the LAPD processing unit 35, it reports the reception to the CPU2 in step E2, returns to step A7 after exiting the interrupt processing, and waits for the next interrupt. The received data is stored in the CPUa reception buffer of the RAMe312. The reception detailed information such as the data position and the data length is notified to the CPU 2 using the report register 3117 of the controller e311.

When the CPUa341 receives the "call setting completion" report from the LAPD processing unit 34, it reports the call setting completion to the CPU2 in step E3, returns to step A7 after exiting the interrupt processing, and waits for the next interrupt. .

When the CPUa 341 receives the report of the “call” from the LAPD processing unit 35, it performs a call control process in step E4 in accordance with CCITT recommendation I.451, and reports in step E5 that the CPU 2 has received a call, After exiting the process, return to the original step A7,
Wait for the next interrupt. The detailed information of the incoming call is the RAMe312 CPU
It is stored in the receiving buffer for a.

FIG. 15 (e) is a flowchart of an interrupt process from the line driver 37. The line driver 37 generates an interrupt when the ISDN line becomes inactive or loses synchronization. When the CPUa341 receives an interrupt from the line driver 37, in step F1, the content of the line fault is logged in the fault logging area of the RAMe312, and in step F2, the CPU2 reports that the line has a fault and exits the interrupt processing. Return to step A7 and wait for the next interrupt.

FIG. 15 (f) is a flowchart of an interrupt process from the DMA control unit built in the CPUa341. CPUa341 is DM built in CPUa341
A When an interrupt is received from the control unit, the CPU 2
To report that the ADPCM operation has ended, return to step A7 after exiting the interrupt processing, and wait for the next interrupt.

 Next, the operation of the CPUb321 and CPUc331 will be described.

CPUb321 and CPUc331 execute the same program. FIG. 17 shows an example of the structure of the communication control program. The program has two protocols, HDLC-BA and HDLC-UN, and selects one of them for use. The selection may be automatically made based on an instruction from the system processor unit 23 and a received frame coming from the line.

FIG. 18 shows an operation flowchart of the communication control program. Here, the CPUb321 is taken as an example, and activation from the CPUa341 is performed by flag sensing without using an interrupt. First, in step H1, the serial controller b323 is initialized to prepare for reception, and in step H2
Then, it is checked whether or not “protocol selection” is activated from the CPUa 341. If there is activation, in step H3, either the designated HDLC-BA or HDLC-UN is selected, and in step H4, a selection completion report is returned to the CPUa341, and step H5
Then, branch to either BA or UN. When branching to BA in step H5, it is checked in step H6 whether or not "transmission" has been activated by the CPUa341. If there is activation, in step H7, transmission processing by HDLC-BA is performed, and in step H8
Then, a transmission completion report is sent to the CPUa341, and the process returns to step H6. If there is no activation from the CPU a341 in step H6, the reception state is checked in step H9, and if data is received from the line, reception processing by HDLC-BA is performed in step H10, and in step H11, the CPUa341 And the process returns to step H6. If there is no reception in step H9, the process returns to step H6.

If branching to UN at step H5 in FIG. 18,
The transmission / reception processing is performed in the flow from step H12 to step H17.
Since this is the same as step H11, the description is omitted here.

In step H2 of FIG. 18, when there is no activation from the CPUa341, the reception state is checked in step H18, and when there is data from the line, in step H19, HDLC-BA, HDLC-UN
Is selected, and the process branches at step H20.
As for the selection method, the control field in the received frame is checked, and the asynchronous balanced mode (SARM: binary “11111100” or 2
Hex "11110100", HDLC-BA, normal response mode (SN
RM: Binary "11001001" or binary "11000001") for HDL
C-UN.

Since the operation of the CPU d351 uses the μPD72305 of NEC, the description is omitted here.

In the above embodiment, a ROM is not used for the sub-processor units 32 and 33, but a ROM can be added with the configuration of the embodiment.

In the embodiment of FIG. 1, the sub-processor unit 32 and the sub-processor unit 33 have a RAMb322 and a RAMc332, respectively, and the method of downloading a program from the main processor unit 34 to the RAM is adopted. If you use a ROM in which a program for the transmission control procedure is written,
Eliminates the need to download programs.

If the whole of the sub-processor unit 32 and the sub-processor unit 33 is rewritten to a one-chip microcomputer, or if the speed matching unit 38 is added to a one-chip microcomputer, the package shown in FIG. At this time, as in the present embodiment, the program may be downloaded to the RAMb 322 or RAMc 332, or a ROM in which the above-described program is previously written may be used instead of the RAM.

In the embodiment shown in FIG. 1, since the sub-processor units 32 and 33 do not have a ROM, they are stopped in a reset state when the power is turned on, and cannot be operated until the main processor unit 34 downloads the program. Absent. Therefore, the ROMa 342 in the main processor unit 34 is made usable from the sub processor units 32 and 33. First, the memory space of the ROMa 342 is divided into three. Specifically, the ROMa in the local bus a memory space of FIG. 5 is divided into three, and two of them are mapped to the lowest part of the local bus b memory space and the local bus c memory space, and RAMb, RAMc Is located above it. This corresponds to the address conversion unit 3342 of the controller b324 in FIG. 9, the address conversion unit 3342 of the controller c334 in FIG.
FIG. 11 The controller changes the address mapping contents of the address conversion unit 3442 of the controller a344 so as to permit access to the hardware resources of the main processor unit 34 from the sub-processor units 32 and 33 prohibited in this embodiment. b32
4. Modify the controller c334 and controller a344. In this way, the sub-processor units 32 and 33 can run the program in the ROMa 342 at the same time as the power is turned on, and can self-diagnose or load the program into the RAM by themselves. Further, even if hardware including the ROM fails, failure analysis can be performed using the ROM.

In the embodiment of FIG. 1, the LAPD processing unit 35 is removed.
Control of multiple lines other than ISDN becomes possible, and control of multiple lines becomes possible by adding a sub-processor unit.

In the embodiment of FIG. 1, two lines can be directly connected and controlled by removing the LAPD processing unit 35 and the line driver 37, and the control of a plurality of lines can be performed by adding a sub-processor unit. It becomes possible with a communication adapter. For example, GW in FIG.
13 and 14, if the communication control on the LAN side is processed by the sub-processor unit of FIG.
Since the data can be directly transmitted to the ISDN via the AMe312, the load on the system processor is reduced, and the throughput is improved because there is no data movement.

In FIG. 1, the local bus b325 and the local bus c335 can be made into one bus, and the controller b324 and the controller c334 can be integrated into one. In this case, CP on one bus
Since two U's operate, the performance is slightly degraded as compared with the embodiment of FIG. 1. For example, if the processing program of HDLC-BA is loaded in RAMb322 and the processing program of HDLC-UN is loaded in RAMc332 in advance, HDLC-BA and HDLC-UN 2
CPUs can be run at the same time.
One HDLC-BA program of AMb322 can be shared and used by two CPUs. By doing so, it is not necessary to download the program from the RAMe 312 every time the transmission control procedure is changed, and the sub-processor program does not need to be resident in the RAMe 312.

〔The invention's effect〕

As described above, according to the present invention, since a plurality of communication control programs operate independently, high-speed communication can be realized by a different communication procedure for each communication path. At this time, the data transmission speed can be adjusted according to the partner station. Further, since one communication control program has a plurality of communication protocols, protocol conversion can be performed quickly and easily.

[Brief description of the drawings]

FIG. 1 is a block diagram of a workstation showing an embodiment of the present invention, FIG. 2 is a diagram of a network using this embodiment, FIG. 3 is a layout diagram of a workstation housing, and FIG. The figure showing the storage state of the memory, the fifth
The figure shows the memory space of the local bus, FIG. 6, FIG. 9, FIG. 10, FIG. 11, FIG. 12, FIG. 19 is the detailed block diagram of the representative block of FIG. Is a time chart of the local bus, FIG. 8 is a memory map corresponding to the slot,
FIG. 13 is a mounting diagram of a communication adapter, FIGS. 14 and 15 are flowcharts showing an example of the operation of the communication adapter, FIG. 16 is a diagram showing an example of loading a communication control program, and FIG. FIG. 18 is a configuration diagram, FIG. 18 is an operation flowchart of a communication control program, FIG. 20 is a structural diagram of a frame used for speed matching, and FIG. 21 is a diagram showing the contents of a speed matching ROM. 1 ... workstation, 23 ... system processor section, 3 ... communication adapter, 34 ... main processor section, 32,33 ... sub-processor section, 35 ... LAPD processing section, 36 ... B channel control section, 37: Line driver 38: Speed matching unit

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yoshimasa Hiramatsu 1st Horiyamashita, Hadano-shi, Kanagawa Hitachi, Ltd. Kanagawa Plant (56) References JP-A-2-244940 (JP, A) JP-A-1 -1226044 (JP, A) JP-A-63-88937 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 29/06

Claims (3)

(57) [Claims] 1. A communication adapter connected to a multi-line including a plurality of communication paths and controlling communication of the multi-line, wherein each of the plurality of communication adapters is operable independently to control communication for each communication path. A communication processing unit, and a memory for holding a plurality of communication control programs executed by the communication processing unit to perform communication control according to a communication protocol, wherein each of the plurality of communication processing units is downloaded from the memory. Communication control program specified in the plurality of communication control programs for each of the plurality of communication processing units in accordance with an instruction from a host system. Downloading a program from the memory to the writable memory of each communication processing unit, Communication adapter characterized by connecting the communication processing unit that executes a communication control program based on a communication protocol to respond. 2. The communication adapter according to claim 1, further comprising means for controlling a transmission speed of said communication path according to a transmission speed of a transmission partner. 3. The communication adapter according to claim 1, further comprising means for multiplexing the plurality of communication paths into the multi-line.