JP2882382B2 - Control method of buffer memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for controlling a buffer memory, and more particularly to a method for controlling a buffer memory using a burst memory for storing cells of an asynchronous transfer mode (ATM) switch.

[0002]

2. Description of the Related Art In an ATM exchange, information such as voice which is strict in delay and information which is strict in discard such as data are transmitted as cells in a centralized manner. Further, as a buffer memory for accumulating cells, a large-capacity, high-speed memory device is required in order to configure a logical queue according to a delay class and a discard class peculiar to an ATM cell. Therefore, conventionally, a method is known in which a static random access memory (SRAM) is used as the above-mentioned buffer memory, and the buffer memory is controlled based on delay class and discard class information added to the cell. (For example, JP-A-4-207543).

FIG. 4 is a block diagram showing an example of a conventional buffer memory control method. Disposal means 1 for each disposal class
Each area 2-1 in the buffer memory corresponding to 1-1-n
To 2-n. Further, each of the areas 2-1 to 2-n in the buffer memory is used by physically dividing one buffer memory into n discard classes logically,
Each region is further divided into m according to the delay class, and constitutes a logical queue for each quality class CL (m, n) corresponding to the discard characteristic added to the input cell and the delay characteristic. I have.

The discarding means 1-1 to 1-n determine whether to discard the input cell according to an instruction from the discard control unit 4. The delay control unit 5 controls the selector 6 based on a predetermined delay characteristic. The selector 6 selects and outputs one of the output cells in each of the areas 2-1 to 2-n in the buffer memory.

Next, the operation of this conventional buffer memory control method will be described. A cell input from an input HW (highway) is discarded according to a discard class by discarding means 1-1.
To 1-n. The quality class CL (m, n) according to the discard characteristic and the delay characteristic is added to this input cell. Here, m is a delay class representing the delay quality, the smaller the value, the higher the priority (smaller the delay), and n is the discard class representing the discard quality, and the smaller the value, the higher the priority (the less the discard). It is shown that.

The above-mentioned input cells are supplied to buffer amount measuring means 3-1 to 3-n provided corresponding thereto through respective areas 2-1 to 2-n of a buffer memory, which will be described later. The memory usage is measured. Discard control unit 4
Detects the used amount of each buffer memory from the buffer amount measuring means 3-1 to 3-n to detect the used amount of the entire buffer memory. Also, when writing to the logical queue, the discarding control unit 4 compares the threshold value with a preset threshold value independently for each discarding quality class corresponding to the usage amount of the entire buffer memory. The control of the discarding units 1-1 to 1-n is performed in such a manner.

If not discarded, the input cell is stored in one of the areas 2-1 to 2-n of the corresponding buffer memory. The delay control unit 5 controls each of the areas 2-1 to 2-1 of the buffer memory.
The selector 6 is controlled so as to give priority to the high-priority class among the areas divided into the delay classes (1 to m) in 2-n, and priority control of the reading order is performed in accordance with the delay class. Thus, each area 2-1 to buffer memory
2-n, input cells are stored for each class, and the discard class of the cells to be discarded is changed according to the total usage of the buffer memory at that time, thereby protecting the cells having a high discard class and protecting the delay class. Higher cells are read with priority.

[0008]

However, in the above-described conventional method of controlling a buffer memory, the buffer memory 2-
1 to 2-n are composed of a burst memory, and their access time depends on the state of a cache incorporated in the burst memory, so that a fixed process is performed within a predetermined time like a buffer memory. In applications that need to be used, the design must be made based on the worst value of the access time, and there is a problem that the performance of the burst memory cannot be fully utilized.

The present invention has been made in view of the above points,
An object of the present invention is to provide a buffer memory control method that can improve transmission efficiency when a burst memory is applied to a buffer memory.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method for controlling a buffer memory, which stores and reads input cells after hitting a cache inside the buffer memory. When a write request of an input cell to any of the plurality of logical queues and a read request of a storage cell of any of the plurality of logical queues are simultaneously made, the plurality of logical queues
After reading the storage cell from one of the logical queues ,
To bypass the sky-out bank queue, the cell that the read-out
It is characterized in that an input cell is written in an empty bank .

Further, the present invention extracts a delay class and a discard class from at least an input cell to which information of the delay class and the discard class is added, and extracts a plurality of logical queues of a buffer memory composed of a bursty memory. Compare the current cell accumulation amount of the logical queue group of the corresponding delay class from the extracted delay class information with the discard threshold set in advance for each discard class.If the discard threshold is exceeded, discard the input cell. If the current cell storage amount is equal to or less than the discard threshold, the input cells are stored in the logical queue corresponding to the extracted discard class, and at the time of reading, the storage amount of each delay class is set to the priority set in advance for each delay class. In addition, buffer memory control that performs priority control of the reading order and moves the bank address pointer to the queue of an empty bank when cell reading is completed A method, when a write request and a read request of the storage cells of the cell was at the same time, after which began to read the storage cell, bypassing the sky-out bank queue, its
And writing an input cell into an empty bank of the read cell .

Further, the present invention manages a bank address used when accessing the buffer memory, thereby enabling a logical queue corresponding to a discard class in the buffer memory, a logical queue of empty banks, Using a bank management table for managing the storage amount of the logical queue, writing and reading control to the logical queue of the buffer memory are performed, and when a cell write request and a storage cell read request are simultaneously made, the storage cell Is read, and the input cells are written to the read bank without going through the logical queue of the empty bank.

[0013] In the present invention, as shown in the principle diagram of Figure 2, a plurality of logical queues 30 ₁ to the buffer memory 13
30 has a logical queue group 31 consisting of _k, and write requests of the input cell to one of a plurality of logical queues 30 ₁ to 30 _k, when a read request of the storage cell was at the same time, the cell reads storage cell For example, the logical queue 30
₁ and the logical queue 30 ₁ of the read cell.
Is bypassed as indicated by 82, and the input cells are written into the bank by the cell writing unit 12.

That is, a control unit for controlling writing and reading of the buffer memory 13, logical queues 30 ₁ to 30 _k in the buffer memory 13 according to the discard class,
The logical queue 81 of the empty bank and the bank management table 18 for managing the storage amount of each logical queue control writing and reading to and from the logical queue group 31 in the buffer memory 13 and write and store cells. When there is a cell read request at the same time, the storage cell is read from the bank of the logical queue by the cell read unit 14, and then bypassed as indicated by 82 without passing through the logical queue 81 of the empty bank. The input cell is written by the cell writing unit 12 into the read bank.

Therefore, in the present invention, cell reading and input cell writing can be performed in the same bank by the bypass 82, so that the operation of hitting the cache of the burst memory constituting the buffer memory 13 can be omitted once. .

[0016]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, the control information extraction unit 11 has an input AT
The information of the delay class indicating the delay quality and the discard class indicating the discard quality added to the M cell is extracted, and the extracted information is transmitted to the control unit 16. The cell writing unit 12 writes the cells that have passed through the control information extraction unit 11 into the bank indicated by the control unit 16 according to a request from the control unit 16.

The buffer memory 13 is a memory for storing ATM cells and is constituted by a burst memory, and can be accessed on a bank basis. One bank can store data for one cell. Buffer memory 1
3, and as shown in FIG. 2, the logical queue group composed of a plurality of logical queues 30 ₁ to 30 _k in response to the discard class 31
have. Although not shown in FIG. 2, the buffer memory 13 has a number of logical queue groups according to the delay class. Further, in FIG. 2, each logical queue 30 ₁ -
Each ellipse in 30 _k indicates one cell stored in one bank.

In FIG. 2, signals are output from the cell reading section 14 to the control section and the bank management table 18 for convenience of explanation, but they are not actually present. FIG. 2 shows that the bank address pointer of the empty bank queue 81 moves between the queues when writing or reading a cell by reading. 1 reads a cell from a bank indicated by the control unit 16 in response to a request from the control unit 16.

The bank management table 15 is used by the control unit 16 as a memory for managing a bank address used when accessing the buffer memory 13.
A logical queue corresponding to a discard class of the ATM cell, a logical queue of an empty bank, and a storage amount of each queue are managed.

The control unit 16 has means for calculating the accumulation amount of each queue managed by the bank management table 15, and stores an input cell to one of a plurality of logical queues in the buffer memory 13 as a cell writing unit. 12, and controls the cell reading unit 14 to read the storage cells from any of the plurality of logical queues in the buffer memory 13.

Next, the writing operation of this embodiment will be described. The input cell to which at least the information of the delay class and the discard class is added is a control information extracting unit 1
1, the delay class and discard class information is extracted and input to the control unit 16, while the cell writing unit 12
Is input to The control unit 16 controls the cell writing unit 12 to store the input cells in the logical queues according to the input discard class in the logical queues according to the input delay class among the logical queues in the buffer memory 13.

At this time, the control unit 16 controls the control information extraction unit 1
Compare the current cell storage amount of the logical queue group of the corresponding delay class with the discard threshold set in advance for each discard class from the information of the delay class of the input cell obtained from 1 and input the discard threshold if the discard threshold is exceeded. Discard the cell. On the other hand, if the current cell storage amount is equal to or smaller than the discard threshold, the bank management table 1
5 is accessed to obtain a bank address pointer of an empty bank of the selected logical queue, and a cell write request is issued to the cell write unit 12 to be written. Cell buffer memory 1
When the writing to 3 is completed, since the bank contains cells, the bank address pointer is moved to the logic queue of the delay class corresponding to the cell in which the writing has been performed.

Next, the operation of this embodiment at the time of reading will be described. The control unit 16 controls the bank management table 15
From the accumulated amount of each queue (specifically, the difference between the read pointer and the write pointer provided for each logical queue in the control unit 16) managed by the buffer memory 13
It is determined whether or not cells are stored.If it is determined that cells are stored, priority control of the reading order is performed in consideration of the storage amount of each delay class in addition to the priority set in advance for each delay class. Do.

In order to check the bank address at the head of the queue selected by the priority control, the control unit 16 accesses the bank management table 15 to obtain a bank address pointer, and issues a cell read request to the cell read unit 14. put out. When the cell reading is completed, the bank becomes empty, and the bank address pointer is moved to the queue of the empty bank.

The above operation is performed when either a write request or a read request for a cell is made. In the control unit 16 and the bank management table 18 shown in FIG. Means that the bank address pointer of the empty bank queue 81 is a cell write,
It moves between the queues at the time of reading. However, when a cell write request and a cell read request are made at the same time, in this embodiment, processing is performed with the empty bank queue 81 being unused by the bypass 82. That is, the cell is read first, and the cell is written to the vacant bank address.

Next, an access operation of the buffer memory 13 will be described with reference to FIG. As described above, the buffer memory 13 is constituted by a burst memory. The burst memory has an internal cache, and all data exchange with the outside is performed through this cache. If the cache hits, it can be accessed immediately, but if it does not hit, it cannot be accessed until after the hit. This operation for hitting is called a preliminary operation, and is indicated by 21 in FIG.

FIG. 3A schematically shows a read access to the buffer memory 13. Since the buffer memory 13 basically does not perform the operation of reading the same cell many times, it is unlikely that the cache has already hit when reading the cell. Therefore, when reading a cell, as shown in FIG.
, The preliminary operation 21 is always required.

FIG. 3B schematically shows write access to the buffer memory 13. Because there is no guarantee that the data will be written to the same address as the previous access,
After performing the preliminary operation 21, the write operation 23 is performed.

FIG. 3C schematically shows an access in which reading and writing are simultaneously performed to the buffer memory 13 by the conventional technique. After the preliminary operation 21, a cell read operation 22 is performed first, and then, after the preliminary operation 21, a cell write operation 23 is performed. Therefore, the time required for the access is simply the sum of the access times shown in FIGS. 3A and 3B.

FIG. 3D schematically shows an access in which reading and writing to the buffer memory 13 are simultaneously performed according to the embodiment of the present invention. The point that the cell read operation 22 is performed following the preliminary operation 21 is the same as in the related art.
In the embodiment of the present invention, as described above, when a cell write request and a cell read request are made at the same time, the cell is written to the bank of the read cell. Since there is a hit, the preliminary operation immediately before cell writing can be omitted, and the cell writing operation 23 is immediately performed. Therefore,
The time required for the access in this case can be shorter than the conventional access time shown in FIG.

Therefore, the bursty memory controlled by the method of the present invention is suitable for use as a buffer memory for storing cells of an ATM switch, and since the access time conventionally changes depending on the state of the cache, it is correspondingly used. Although the access pattern had to be changed, the circuit was complicated and expensive, but in this embodiment, FIG.
By periodically performing the accesses (A), (B) and (D), the circuit can be simplified and the cost can be reduced.

Although the present invention is not limited to the above embodiment, one bank is described as having a size capable of storing data for one cell, but the size of the bank is not limited. However, if the amount of data that can be transferred at a time by the burst memory is limited, this determines the upper limit of the size of the bank.

[0034]

As described above, according to the present invention,
By sequentially performing cell reading and input cell writing to the same bank by bypassing the empty bank queue, the operation of hitting the cache of the bursty memory constituting the buffer memory can be omitted once. In comparison, the maximum access time of the buffer memory can be shortened, so that the burst memory can be easily applied to the buffer memory for storing cells of the ATM switch.

Further, conventionally, since the access time of the burst memory changes depending on the state of the cache, it is necessary to change the access pattern accordingly, and the circuit is complicated. The circuit can be simplified by periodically performing the read and the access for reading the cell first and writing the cell to the bank, so that the circuit scale can be made smaller than before.

Further, according to the present invention, the disadvantage (complication of the circuit and good access time) due to the change of the access time due to the state of the cache of the large capacity and low cost burst memory is improved. A large-capacity, low-cost buffer memory can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram illustrating the principle of the present invention.

FIG. 3 is an explanatory diagram of an access operation of the buffer memory of FIG. 1 and the like.

FIG. 4 is a configuration diagram of a conventional example.

[Explanation of symbols]

Reference Signs List 11 control information extracting unit 12 cell writing unit 13 buffer memory 14 cell reading unit 15 bank management table 16 control unit 18 control unit and management table 30 ₁ to 30 _k logical queue 31 logical queue group 81 empty bank queue 82 bypass

Claims (3)

(57) [Claims] 1. A buffer memory control method in which input cells are stored and read after hitting a cache included in the buffer memory, wherein a request to write an input cell to any one of a plurality of logical queues of the buffer memory is provided. And at the same time a read request for any one of the storage cells of the plurality of logical queues is made, after reading the storage cell from one of the plurality of logical queues, , bypassing the air-out bank queue control method for a buffer memory and writes the input cell in the empty bank of the readout cell. 2. A delay class and a discard class are extracted from an input cell to which at least information of the delay class and the discard class are added, and the extracted delay is extracted from a plurality of logical queues of a buffer memory composed of a bursty memory. The current cell storage amount of the logical queue group of the corresponding delay class is compared with the discard threshold set in advance for each discard class from the class information, and when the discard threshold is exceeded, the input cell is discarded. If the cell storage amount of the delay class is equal to or less than the discard threshold, the input cell is stored in a logical queue corresponding to the extracted discard class. At the time of reading, the storage amount of each delay class is set to the priority set in advance for each of the delay classes. Control of the buffer memory that performs priority control of the read order and moves the bank address pointer to the queue of the empty bank when the cell read is completed. A method, when a read request of the write requests to the storage cell of the cell had at the same time, after the out read the storage cell, bypassing the air-out bank queue empty bar of the readout cell
A method of controlling the buffer memory , wherein the input cell is written to the link . 3. A logical queue according to the discard class in the buffer memory and a logical queue of empty banks in the buffer memory by managing a bank address used when accessing the buffer memory. Using the bank management table that manages the storage amount of the logical queue, writing and reading control to the logical queue of the buffer memory are performed, and when the cell write request and the storage cell read request are simultaneously performed, 3. The method according to claim 2, wherein after reading the storage cell, the input cell is written to the read bank without going through the logical queue of the empty bank.