JP2883767B2 - Non-volatile memory control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention speeds up recovery after an accident such as a power failure or a power failure in a peripheral device of a computer, for example, a magnetic tape device, a magnetic disk device, or the like. Therefore, the present invention relates to a control circuit for a non-volatile memory (non-volatile S-RAM) for storing data on the state of the apparatus when the apparatus is in the operating state.

2. Description of the Related Art In recent years, peripheral devices of electronic computers have been required to be promptly restored when the devices are down due to the non-stop operation of electronic computer systems. In addition, with the unmanned operation, it is required to recover without human intervention.

For this reason, when the apparatus is in an operating state, the apparatus itself recognizes the state of the apparatus, and a non-volatile memory, such as NOVRAM, is used so that the apparatus can be quickly recovered from an accident such as a power failure.
(Non-volatile S-RAM) is provided, but it is necessary to control data recall and store normally under any conditions such as power-on, power-off, power failure, and instantaneous interruption.

[0004]

4 to 7 show a conventional example. In FIGS. 4 to 7, 1 is an S-RAM memory array, 2 is an EEPROM memory array, 3 is an address control circuit, and 4 is Control circuit, 5 is a data control circuit, 7 is a magnetic tape device,
8 is a control circuit, 9 is a NOVRAM, 10 is a voltage adjusting unit,
11 is a voltage monitor, 12 is a reset circuit, 13 is a clock circuit, 14 is a display control circuit, 15 is an operation panel (operation panel), 16 is a head (read / write head), 17 is a write control circuit, and 18 is a ROM. , 19 are registers, 20 is a servo control circuit, 21 is a read control circuit, 22 is a motor drive circuit, 23 is a detection circuit, 24 is a motor, 25 is a sensor, 26 is an interface control circuit, FF1 and FF2 are flip-flops, OR1 Indicates an OR circuit, NOT1 indicates a NOT circuit, and NAND1 indicates a NAND circuit.

Conventionally, in the case of a peripheral device of a computer, when an accident such as a power cut or a power failure occurs, in order to quickly recover the device, when the device is in an operating state, the device itself is used.
It is necessary to recognize the state of the device, and the peripheral device is provided with a nonvolatile memory.

As a non-volatile memory for storing such device state data, a NOVRAM (Non Volat) is used.
ile Static Random Access
Memory (non-volatile S-RAM) element has been used.

First, referring to FIG.
The element will be described. This NOVRAM element has an S-
RAM (Static Random Access)
Memory) memory array 1 and an EEPROM (El
electrically erasable and P
programmable Read Only Mem
(ory: EEPROM) A memory array 2, an address control circuit 3, a control circuit 4, and a data control circuit 5.

The control circuit 4 receives a write signal and a read signal from the outside, and also receives a store signal and a recall signal, and performs various controls in the device. The address control circuit 3 controls the address of the memory array, and the data control circuit 5 controls the reading / writing of data from / to the memory array.

In such a NOVRAM, data written to the S-RAM memory array 1 can be instantaneously stored in the EEPROM memory array 2 by a store signal in response to an address signal, a data signal, and a write signal.

On the contrary, the EEPROM memory array 2
The data stored in the S
-Can be extracted to the RAM memory array 1. The store signal and the recall signal are single pulse signals, and the store operation and the recall operation can be controlled as described above.

Next, an example in which a NOVRAM is used for a magnetic tape device will be described with reference to FIG. FIG. 5 is a schematic block diagram of the magnetic tape device. This magnetic tape device is composed of a mechanism section and its control section. The control unit includes an interface control circuit 26, a servo control circuit 2
0, a write control circuit 17, a read control circuit 21, a display control circuit 14, and the like.

[0012] The control unit is provided with a NOVRAM 9 as described above as a countermeasure in the event of an accident such as a power failure.
And its peripheral circuits. The interface control circuit 26 is connected to a higher-level controller of the magnetic tape device, exchanges read / write commands, data, and the like, or communicates with the servo control circuit 20, the write control circuit 17, the display control circuit 14, and the like. , Respectively, for exchanging data.

The servo control circuit 20 uses a data from the interface control circuit 26 to
, The drive of the motor 24 of the above-mentioned mechanism is controlled. In this case, the detection circuit 23 detects the positional relationship of the mechanical unit via the sensor 25, and takes the detected information into the servo control circuit 20 to perform servo control.

The display control circuit 14 performs display based on the data from the interface control circuit 26 to call attention to the operator. The read control circuit 21 reads data recorded on the magnetic tape recording medium via the head 16. The write control circuit 17 records the data on the magnetic tape recording medium via the head 16 according to the data from the interface control circuit 26.

Next, the NOVRAM 9 and its peripheral circuits will be described. The NOVRAM 9 is used to determine the running distance of the tape, which is necessary to recognize the state of the magnetic tape device itself.
It is a memory for storing information such as rewinding, connection status with a higher-level controller (online / offline), and operation position of a mechanical unit. These information are stored in an S-controller by an interface control circuit 26 and a servo control circuit 20. RAM
The data is written to the memory array 1 and updated.

The voltage monitoring section 11 monitors whether or not the supplied arbitrary voltage is equal to or higher than a predetermined limit level. The reset circuit 12 is a circuit that resets all the circuit units when it is notified from the voltage monitoring unit 11 that the minimum operating voltage of the circuit has been reached.

The clock circuit 13 is a circuit for generating a store signal when the power is turned off, and generates a system clock. The control circuit 8 sets NO
This is a circuit that performs data recall and store control of the VRAM 9.

The voltage monitoring unit 11, the reset circuit 12, and the control circuit 8 supply an arbitrary voltage (+ Vc
cL) is supplied, and operation is performed with this voltage. The voltage adjusting unit 10 is supplied with a voltage (+ VccH) higher than the arbitrary voltage (+ VccL), and generates a voltage (+ Vcc) equivalent to the arbitrary voltage (+ VccL) from the voltage (+ VccH). And a circuit for supplying to a NOVRAM (nonvolatile S-RAM) 9.

The NOVRAM 9 is a non-volatile memory (non-volatile S-RAM) that stores the state of the apparatus when the power is turned on. Next, the operation of the NOVRAM 9 and its peripheral circuits will be described with reference to FIGS.

At the time shown in FIG. 7, when the power is turned on and before the circuit reaches the minimum operating voltage,
Voltage (+ Vcc) higher than any voltage (+ VccL)
H) is supplied to the NOVRAM
(Non-volatile S-RAM) 9
The VRAM 9 is in an operable state.

At the time after the above time, when the minimum operating voltage of the circuit is reached, the signal of the voltage monitoring unit 11 is turned on. Therefore, since "1" is input to the NOT circuit NOT1 in the control circuit 8, its output is "0". As a result, since the flip-flops FF1 and FF2 are reset by giving “0” to the reset input, the output becomes “0”.

The OR circuit OR1 is connected to the power supply monitor 11
From the FF2 and the output "0" of the FF2, the output becomes "1" and remains "1" until the power is turned off.
Is held.

Further, at the time, the NAND circuit NAND1
Is the signal “1” from the voltage monitoring unit 11 and the reset circuit 1
The output “0” is output from the output “1” from the output “2”. After the time, the first clock signal causes the reset circuit 12
Changes the output from “1” to “0”.

As a result, the reset circuit 1 of the NAND 1
Since the input from 2 changes from “1” to “0”, the output changes from “0” to “1”. As a result, a recall signal to NOVRAM 9 is generated. With this recall signal, the data in the NOVRAM 9 is read. Then, based on the read data, the device itself recognizes the state of the device when the power was last turned off.

Next, the data store operation of the NOVRAM 9 will be described. The power is turned off at the time of FIG.
At the time when the voltage becomes equal to or lower than the minimum operating voltage of the circuit, the voltage adjustment unit 10 supplied with a voltage (+ VccH) higher than an arbitrary voltage supplies the voltage to the NOVRAM 9, and thus the NOVRAM 9 can operate. It is in a state.

At the time, the voltage monitoring unit 11
In order to detect that the voltage is equal to or lower than the minimum operating voltage, the output signal of the voltage monitoring unit 11 becomes “0”. Therefore, the control circuit 8
Of the flip-flop FF which has been in the reset state becomes “0” and its output becomes “1”.
1, FF2 starts operating.

At this time, the OR circuit OR 1 outputs “0” by the logical sum of the output “0” of the flip-flop FF 2 and the output “0” of the voltage monitoring unit 11. afterwards,
At the time, the input data of FF1 becomes "1" due to the clock input of FF1, but FF1 outputs "0".

At this time, "0" which is the output of FF1 is given to the input of FF2.
"0" is output, and the output of OR1 is held at "0". At the time after the time, the FF1 outputs “1” because the input data of the FF1 is “1” due to the clock input of the FF1.

At this time, "1" which is the output of FF1 is given to the input of FF2.
Since “1” is output, and “1” of FF2 is input to OR1, the output is “1”.

As a result, the store pulse signal is generated between the time and the time. By the above-described store operation, NOVR is controlled by the control circuit 8.
The data of the AM9 S-RAM memory array is
M in the memory array 2 and then NO for several milliseconds
After the voltage supplied to the VRAM 9 is held, the voltage becomes 0 V at the time.

[0031]

The above-mentioned conventional apparatus has the following problems. (1) In a peripheral device such as a magnetic tape device, in order to quickly recover from an accident such as a power failure, a nonvolatile memory N
An OVRAM is used, and information on the device state is written in the NOVRAM.

In this case, in particular, since the supply voltage of the control circuit during the data write operation of the NOVRAM drops every moment, the circuit becomes unstable in operation and may malfunction (see FIGS. 7 to 7).

(2) A clock is used to write device information and the like to the NOVRAM and to read the device information from the NOVRAM. Therefore, the circuit becomes complicated.

(3) When the supply voltage to the control circuit or the like is uncertain, information is written to the NOVRAM or the NOVRA
Since information is read from M, the operation becomes unstable. Therefore, data reading and writing to the NOVRAM may not be performed normally, and the reliability of processing at the time of device recovery after an accident such as a power failure may be reduced.

An object of the present invention is to solve such a conventional problem, to stabilize data storage and recall operations in a NOVRAM (nonvolatile S-RAM), to eliminate malfunctions, and to simplify the circuit configuration. With the goal.

[0036]

FIG. 1 is a diagram for explaining the principle of the present invention. In FIG. 1, the same components as those shown in FIGS. 4 to 7 are denoted by the same reference numerals.

The present invention has the following configuration to solve the above-mentioned problems. (1) In the nonvolatile memory control circuit, the nonvolatile memory 9 and the operable signal are supplied to the nonvolatile memory 9.
Instructs to read data when supplied, and
A control circuit 8 for instructing writing of data when the supply is cut off, the power supply of any voltage is supplied during the operation accepted this voltage is minimum or more voltage required for the operation of the circuit
Voltage monitoring unit 11 that continuously notifies the control circuit 8
And a power supply having a voltage higher than the arbitrary voltage is supplied,
This is transformed to a voltage equal to the above-mentioned arbitrary voltage and
A voltage adjusting unit 10 is provided for supplying the circuit 8 and the nonvolatile memory 9 .

(2) In the configuration (1), the control circuit 8 uses a control signal output from the voltage monitoring unit 11 as an input signal and generates a single signal according to a change in the input signal. Was.

(3) In the configuration (1) or (2), the nonvolatile memory 9 may be a NOVRAM (nonvolatile static random access memory: nonvolatile S-RA).
M) and the control circuit 8 uses the NOVRA
By generating and outputting a recall signal for reading and writing data of M and a store signal, the NOVRAM
The reading and writing of data to and from the memory are controlled.

[0040]

The operation of the present invention based on the above configuration will be described with reference to FIG. As shown in FIG. 1A, the voltage monitoring unit 11 is configured to output a signal when the voltage reaches a voltage lower than or equal to a low limit at which the circuit operates.
It operates when ccL is supplied.

The voltage adjuster 10 is supplied with a voltage + VccH higher than the arbitrary voltage + VccL, and generates a voltage (+ Vcc) equivalent to the arbitrary voltage (VccL) from this voltage. Control circuit 8, NO
Output to VRAM 9 (VccL = Vcc).

NOVRAM 9 (nonvolatile S-RAM)
Is supplied with power (voltage + Vcc) from the voltage adjusting unit 10 and stores information on the device state. The control circuit 8
This circuit controls the operation of recalling and storing data in the NOVRAM 9, and generates a single signal only from an output signal from the voltage monitoring unit 11. The control circuit 8
Are supplied with power (+ Vcc) from the voltage adjustment unit 10.

In FIG. 1 (B), when the power is turned on at the time shown in FIG.
VccL and a voltage + VccH (VccL <VccH) higher than any voltage supplied to the voltage adjustment unit 10
Rises.

The recall signal and the store signal are determined at a time before the voltage monitoring unit 11 detects the low limit voltage, and the control circuit 8 changes the voltage monitoring unit 11 at the time. , A recall signal is output.

Similarly, when the power supply is turned off, the voltage (+ VccL) drops at the time point and the output signal of the voltage monitoring section 11 changes when the time point reaches the time point. Then, at a time after the time T has elapsed, the store signal changes and generates a pulse.

A store signal is output from the control circuit 8,
At the time when sufficient time has passed, NOVRAM 9 and
The voltage supplied to the control circuit 8 drops, and at time
Becomes

In this way, the store and recall operations for the NOVRAM can be performed while the supply voltage is stable. Therefore, no malfunction occurs and stable writing and reading of device information can be performed.

Further, since the conventional clock is not required, the circuit configuration is simplified.

[0049]

Embodiments of the present invention will be described below with reference to the drawings. FIGS. 2 and 3 are views showing an embodiment of the present invention, and the same components as those in FIGS. 1, 4 to 7 are denoted by the same reference numerals. MM denotes a monostable multivibrator, R denotes a resistor, and C denotes a capacitor.

This embodiment is an example applied to a magnetic tape device (see FIG. 5) similar to the above-mentioned conventional example.
M has the same configuration as that of the conventional example (see FIG. 4). Therefore, FIGS. 4 and 5 are referred to in the present embodiment, but detailed description is omitted.

The voltage adjusting unit 10 is connected to +12 V (+ Vcc
H) is connected to a power supply of H. The voltage of +12 V is adjusted to generate a voltage of +5 V (+ Vcc), and the voltage of +5 V is supplied to the control circuit 8 and the NOVRAM 9.

The control circuit 8 is a circuit that outputs a single pulse signal in response to a change in the input signal.
The configuration is as shown in FIG. That is, the control circuit 8 includes the monostable multivibrator MM and the negation circuit NO.
T1 and the like, and outputs a single pulse signal according to a change in the input signal.

The resistor R and the capacitor C are connected to the monostable multivibrator MM of the control circuit 8, and the pulse width τ of the output pulse is determined by the time constant of the resistor R and the capacitor C. .

The voltage monitoring unit 11 supplies +5 V (+ Vcc
L) is supplied, and the voltage is monitored as in the conventional example. Next, the operation of the embodiment will be described with reference to FIG.

First, it is assumed that the power is turned on at the time.
At this time, the power supplies of +5 V and +12 V sequentially rise. Accordingly, the output of the voltage regulator (regulator) 10 and the monostable multivibrator M of the control circuit 8
The output of M (recall, store signal) also rises. At the time, the +12 V power supply reaches approximately +6.5 V, and the output of the voltage adjusting unit 10 and the output of the monostable multivibrator MM of the control circuit 8 are determined.

Thereafter, at the time point of time, the + 5V power supply is switched to +4.
When the voltage reaches 3 V, the voltage monitoring unit 11 detects the low limit operating voltage. At the same time, the detection signal changes the clock input of the recall signal side circuit of the monostable multivibrator MM in the control circuit 8 from "0" to "1", and outputs a recall pulse by the rising clock.

This recall pulse is a pulse output between the times shown in FIG. 3 and the time shown in FIG. 3. For example, if the resistance R is 2.2 KΩ and the capacitance of the capacitor C is 560 pF, the pulse width τ is about τ = 1.2 μS.

Thus, the previously stored data is recalled until the +5 V and +12 V power supplies become stable at the time. The processing at the time of power off is as follows.

From the time point of time, the power supplies of + 5V and + 12V sequentially drop, and at the time point where the power supply of + 5V becomes + 4.5V, the voltage monitoring unit 11 detects the voltage lower than the low limit operating voltage. At this time, the input of the NOT circuit NOT1 in the control circuit 8 changes from “1” to “0”, and the output changes from “0” to “1”.

With this rising clock, the circuit on the store signal side of the monostable multivibrator MM operates and outputs a store pulse. At this time, the pulse width τ of the pulse generated between the times
Is τ = 1.2 μS, as described above.

At this time, the voltage of +5 V is supplied to the NOVRAM 9 and the control circuit 8, and
From the time when the power supply of V and + 12V falls below + 6V,
Start to descend as well.

Thereafter, the time reaches +5 V, +12
The V power supply becomes 0 V, but the data store operation is reliably performed between the following times. (Other Embodiments) Although the embodiments have been described above, the present invention can be implemented as follows.

(1) The present invention is not limited to a magnetic tape device, but is applicable to, for example, peripheral devices of various electronic computers such as a magnetic disk device and an optical disk device. (2) The control circuit for controlling the nonvolatile memory is not limited to the monostable multivibrator, and may be any circuit that outputs a single signal in response to a change in an input signal.

[0064]

As described above, the present invention has the following effects. (1) When the power is turned on or when the voltage rises and falls when the power is turned off, the data write and read operations to the NOVRAM (non-volatile S-RAM) are stabilized, and the normal operation can always be performed.

(2) Regardless of the conditions of power-on, power-off, power failure, and instantaneous interruption, data can be normally recalled and stored in the NOVRAM normally. (3) It is possible to quickly and surely recover from an accident such as a power failure using the data in the NOVRAM.

(4) The circuit configuration is simplified. (5) NOVRAM in peripheral devices such as magnetic tape devices
(Nonvolatile S-RAM) improves the reliability of data write and read operations.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram of a NOVRAM and its peripheral circuits according to an embodiment of the present invention.

FIG. 3 is a timing chart of each unit in the embodiment of the present invention.

FIG. 4 is an explanatory diagram of a NOVRAM.

FIG. 5 is a schematic block diagram of a magnetic tape device.

FIG. 6 is an explanatory diagram of a conventional NOVRAM and its peripheral circuits.

FIG. 7 is a timing chart of each section in a conventional example.

[Explanation of symbols]

 Reference Signs List 8 control circuit 9 nonvolatile S-RAM 10 voltage regulator 11 voltage monitor

Claims (3)

(57) [Claims] A nonvolatile memory; and an operable signal supplied to the nonvolatile memory .
Command to read data, and supply of the operation enable signal is interrupted.
A power supply of an arbitrary voltage and a control circuit that instructs data writing when it is hit are supplied, and while the voltage is higher than the minimum required for circuit operation, the above-mentioned operable signal is output.
A voltage monitoring unit that continuously notifies the control circuit, and a power supply having a voltage higher than the arbitrary voltage is supplied,
To the control circuit by transforming
Non-volatile memory control circuit characterized by comprising a voltage regulator for supplying to the said non-volatile memory with. As claimed in claim 2 wherein said control circuit, a control signal outputted from the voltage monitoring unit as an input signal, by a change of the input signal, according to claim 1, characterized in that with a circuit for generating a single signal The nonvolatile memory control circuit according to any one of the preceding claims. Wherein as the nonvolatile memory, nonvolatile S-
Using a NOVRAM that constitutes a RAM, and controlling and controlling the reading and writing of data to and from the NOVRAM by generating and outputting a recall signal and a store signal for reading and writing data of the NOVRAM using the control circuit. 3. The nonvolatile memory control circuit according to claim 1, wherein: