JP2886622B2 - Wafer scale semiconductor integrated circuit and method of manufacturing the same - Google Patents

Description

The present invention relates to a wafer-scale semiconductor integrated circuit in which a number of chips formed on a wafer are connected by connection wiring, and a method of manufacturing the same. Floating connection wiring at an input portion of each chip A wafer scale integrated circuit in which a large number of chips formed in a chip area on a wafer are connected by connection wiring, with the object of preventing the occurrence of
At least the chip located at the outer periphery of the chip area is provided with means for preventing the connection wiring from being in a floating state.

[Industrial Application Field] The present invention relates to a wafer-scale semiconductor integrated circuit in which a number of chips formed on a wafer are connected by connection wiring, and a method of manufacturing the same.

2. Description of the Related Art In recent years, a wafer-scale semiconductor integrated circuit in which a plurality of chips are formed on a single wafer and a wafer is used as one device without separating the chips to achieve high integration of a semiconductor memory or the like has been put into practical use. I have.

[Conventional technology]

Conventionally, in a wafer-scale integrated circuit in which a large number of identical functional chips are formed on a wafer, and each functional chip is connected by wiring to be used as one device, a wiring forming process is performed in the same manner.
Using a reticle 1 as shown in FIG. 20, a wiring pattern 3 of many chips is patterned on a wafer 2 shown in FIG. That is, the reticle 1 is formed around the wiring pattern portion 4 on which the wiring pattern is formed with a light shielding film such as a chrome film, and an exposure portion 5 for removing the light shielding film and allowing the irradiation light to pass therethrough. Is formed with a light shielding film 6 for shielding the irradiation light with a light shielding film. By exposing the wafer 2 while moving such a reticle 1 by a stepper, a large number of identical wiring patterns 3 are patterned on the wafer 2 as shown in FIG. 21, and a large number of identical functional chips are formed. .

A large number of chips formed on the wafer 2 are usually cut at the scribe lines 7 formed between the wiring patterns 3 by double exposure of the exposure unit 5 of the reticle 1, but the scribe lines 7 are formed in the wafer scale integrated circuit. Wirings for connecting the respective chips are formed thereon, and the wafer 2 is used as one device.

The following method is used to form wiring for connecting the chips.

(1) By irradiating a wafer with an electron beam in a predetermined pattern in an aluminum vapor phase, an aluminum wiring having a predetermined pattern is grown between chips.

(2) A mask for forming the wiring between the chips is formed by electron beam exposure, and the wiring between the chips is formed by photoetching using the mask.

(3) Each chip is connected by a bonding wire.

[Problems to be solved by the invention]

However, when the wiring pattern of all the chips formed on the wafer is patterned with the above-described reticle, the chips formed on the outer peripheral portion of the chip region are in a floating state because there are no adjacent chips on the outer peripheral side of the chip region. (Floating state) occurs in the connection wiring. Since the signal level on the floating connection wiring is indefinite, a through current flows through a CMOS circuit constituting an input line of each chip, which causes an increase in current consumption and a malfunction due to external noise.

Further, the above method has the following problems.

In the method shown in (1), the wiring between the chips on the wafer is directly exposed and patterned by an electron beam, so that the throughput is reduced.

In the method shown in (2), the wiring between the chips is formed by photoetching using a mask, so that there is a limit to high integration and it is also difficult to secure sufficient reliability.

In the method shown in (3), since it is necessary to form bonding pads for each chip, the degree of integration is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems, to prevent floating connection wiring from being generated at an input portion of each chip, and to realize this by an efficient method.

[Means for solving the problem]

The wafer scale semiconductor integrated circuit of the present invention is a wafer scale semiconductor integrated circuit in which a number of chips 11a and 11b formed in a chip area on a wafer 2 are connected by connection wiring, and a chip ( 11
a) means to prevent the connection wiring from floating (1)
8) is provided.

Further, the manufacturing method of the present invention is a method of manufacturing a wafer scale integrated circuit including a step of sequentially exposing a wiring pattern of a plurality of functional chips on a wafer by repeating exposure using a reticle. A connection wiring pattern section 9 for connection to an adjacent function chip is provided around the wiring pattern section 4 of the functional chip, and a light shielding section 6 is formed around the connection wiring pattern section 9.

[Action]

In the wafer-scale semiconductor integrated circuit of the present invention, the chip 11a formed on the outer periphery of the chip area is formed in a state where the floating connection wiring is cut off during patterning with the reticle.

Further, in the manufacturing method of the present invention, at the same time as the exposure of the wiring pattern by the wiring pattern portion 4, the connection wiring pattern connecting the wiring pattern and the wiring pattern to be exposed adjacently is exposed by the connection wiring pattern portion 9. .

〔Example〕

FIG. 1 is a view showing a reticle according to a first embodiment of the present invention. 20, the same components as those in FIG. 20 are denoted by the same reference numerals. The reticle 8 shown in FIG. 1 has a connection wiring pattern 9 for forming a connection wiring between adjacent chips on a wafer. The connection wiring pattern 9 shown in FIG. 1 extends in the illustrated X direction and is provided between the internal wiring pattern portion 4 and the light shielding portion 6. The connection wiring pattern 9 is formed of chrome having a function of blocking light.

FIG. 2 shows a reticle 8A having a connection wiring pattern 9 extending in the X and Y directions. Two connection wiring patterns 9 extend from each side of the internal wiring pattern portion 4.

The connection wiring between the chips is formed as follows using the reticle 8A of FIG. Attach reticle 8A to a stepper (not shown). In FIG. 3, reticle 8A is positioned as indicated by I. Then, the wafer is partially exposed. As a result, the connection wiring extending in the X and Y directions is formed at the same time as the internal connection wiring is formed in the region on the wafer corresponding to the internal connection wiring pattern portion 4. Next, the wafer is shifted so as to be exposed as shown in FIG. That is, the reticle 8A is moved so that the two left connection wiring patterns 9 when the reticle 8A is at the position I overlap the two right connection wiring patterns 9 when the reticle 8A is at the position II. Then, the wafer is exposed with the reticle 8A at the position II. Therefore, the area 7a on the wafer is exposed twice and the area 7b is exposed once. In this manner, as shown in FIG. 4, the internal connection wiring of each chip 3 and the connection wiring 10 for connecting the adjacent chips to each other can be formed simultaneously.

Also, the reticle is configured such that the two left connection wiring patterns 9 when the reticle 8A is at the position I are continuously coupled to the two right connection wiring patterns 9 when the reticle 8A is at the position II, or are partially overlapped. 8A can also be positioned.

Next, a second embodiment of the present invention will be described. Here, the connection wiring 10a shown in FIG. 4 is not used to connect the adjacent chips 3. That is, when the reticle 8A shown in FIG. 2 is used, the chips 3 located around the chip arrangement have connection wirings 10a which are not used for forming connections between the chips. Such a connection wiring 10a is in an electrically floating state. The presence of such floating connection wiring causes a malfunction of the wafer-scale semiconductor integrated circuit and increases power consumption. A second embodiment of the present invention is to solve such a problem.

In FIG. 5, a plurality of chips 11a and 11b are formed on a wafer 2. The chip 11a (shown by hatched blocks) is located at the periphery of the chip array, and the chip 11b is located so as to surround the chip 11a.
The internal connection wiring of each chip 11b and the connection wiring extending from each chip 11b are formed of a reticle similar to the reticle shown in FIG. Internal connection wiring of each chip 11a and each chip 11a
Is formed of a reticle different from the reticle for the chip 11b. That is, the reticle for the chip 11a located in the peripheral portion of the chip arrangement has a connection wiring pattern extending only in the direction of the adjacent chip.
In other words, there is no connection wiring pattern extending in the direction of the end of the wafer 2 and not used for connecting adjacent chips. Therefore, the input of the chip 11a has no floating connection wiring. The internal connection wiring pattern of the reticle for the chip 11a is the same as that for the chip 11b.

The second embodiment will be further described with reference to FIGS. 6 and 7 (a) to (c).

In the wafer scale semiconductor integrated circuit shown in FIG. 6, a large number of identical function chips 12a to 12i are formed in a chip area on a wafer 2 to constitute a semiconductor memory. Each chip
12a to 12i have the same wiring pattern in the chip and the same function, but have different connection wiring patterns with adjacent chips. That is, each of the chips 12a to 12i is patterned by a reticle having a different connection wiring pattern to an adjacent chip.

A reticle for patterning each of the chips 12a to 12i
Referring to the drawings, reticles 13a to 13i shown in FIGS. 7A to 7I are used to pattern chips 12a to 12i, respectively. That is, the reticle 13a shown in FIG. 7 (a) is for patterning the chip 12a, and since there is no chip adjacent to the chip 12a at the upper side in FIG. 6, the reticle 13a is connected except in that direction. The wiring pattern 14 is formed. Since the chip 12b does not have an adjacent chip on the right side in FIG. 6, the connection wiring pattern 14 is formed on the reticle 13b for patterning the chip 12b except for its direction.

In this way, the chips 12c to 12h are shown in FIGS.
Since the chips 12i are patterned by the reticles 13c to 13h shown in (h), and the chip 12i has an adjacent chip in all directions, the reticle 13i for patterning the chip 12i has the connection wiring pattern 4 formed in all directions.

Therefore, in each of the chips 12a to 12i patterned by the reticles 13a to 13i as described above, the occurrence of the floating connection wiring in the chips 12a to 12h located at the outer peripheral portion of the chip area is prevented, and the floating connection wiring is generated. This can prevent a malfunction or an increase in current consumption.

FIG. 8 shows a reticle corresponding to the schematic reticle shown in FIG. 7 (a). The illustrated reticle 8B does not have a connection wiring pattern extending upward.

The connection wiring extending from the chips 12a to 12h can be formed by another method. First, the internal connection wiring of the chips 12a to 12i and the connection wiring extending therefrom are formed by the same reticle (for example, the reticle 8A in FIG. 2). And
Thus, another reticle having a window located at a place where unnecessary connection wiring is formed is used. An example of this reticle is shown in FIG. The reticle 8C in FIG.
It is used after each chip is formed with the reticle 8A in the figure.
The reticle 8C has two windows 9e where unnecessary connection wiring extending upward and formed by the reticle 8A is formed. The electron beam is irradiated onto these unnecessary connection wirings through the window 9e of the reticle 8C. In this way, unnecessary connection wiring can be removed.

 Next, a third embodiment of the present invention will be described.

On the wafer 2 shown in FIG. 10, a large number of identical function chips 16 are formed to form a wafer scale semiconductor memory, and each chip 16 is all patterned by the same reticle.

As shown in FIG. 11, each chip 16 has a connection wiring 17 to an adjacent chip connected to an internal circuit (not shown) via a clamp circuit 18. The specific configuration of the clamp circuit 18 will be described with reference to FIG. 11. In the clamp circuit 18 shown in FIG. 11 (a), an N-channel MOS transistor Tr1 is connected between the connection line 17 and the ground G. The power supply Vcc is supplied to the gate of the transistor Tr1, and the transistor Tr1 is always turned on with high impedance. With such a configuration, when no input signal is input to the connection line 17, the transistor Tr1 is turned on and the connection line 1 is turned on.
7 is held at the L level, and when an H level signal is input to the connection line 17, the transistor Tr1 is turned on with high impedance, so that the connection line 17 is held at the H level.

Accordingly, since such a clamp circuit 18 is formed on each chip 16, the connection wiring 17 not connected to an adjacent chip in the chip 16 located on the outer peripheral portion of the chip area.
Is always kept at the L level to prevent a floating state. On the other hand, the connection wiring 17 to which the H-level or L-level signal is input transmits the signal regardless of the operation of the transistor Tr1, and the power consumption of the transistor Tr1 in each chip 6 is extremely small.

In addition, the clamp circuit 18 may be configured as shown in FIGS. 12 (b) to 12 (d). That is, in the clamp circuit 18 shown in FIG. 12 (b), a P-channel MOS transistor Tr2 is connected between the connection wiring 17 and the power supply Vcc, and the gate of the transistor Tr2 is connected to the ground G, and has a high impedance at all times. Is turned on. Therefore, the clamp circuit 18 always keeps the connection wiring 17 at the H level except when an L level signal is input to the connection wiring 17, so that the floating state of the connection wiring 17 is prevented.

In the clamp circuit 18 shown in FIG. 12 (c), the connection wiring 17 is connected to the ground G via the high resistance R1.
The operation is similar to that of the clamp circuit 18 shown in FIG.

In the clamp circuit 18 shown in FIG. 12 (d), the connection wiring 17 is connected to the power supply Vcc via the high resistance R2.
The operation is similar to that of the clamp circuit 18 shown in FIG.

Further, in the second embodiment, the clamp circuit 18 is formed on all the chips 16, but the clamp circuit 18 is formed only on the chip 19a formed on the outer peripheral portion of the chip area as shown in FIG. Chip 19 formed in the center of the chip area
If the clamp circuit 18 is not formed in b, the current consumption in each chip 19b can be reduced.

FIG. 14 shows the electrical configuration of each chip formed on the wafer 2. Each chip 30 shown has controller 30A and DRA
M30B. Adjacent chip 30 is bidirectional connection wiring 31
Connected by In the illustrated block, the controller 30A marked with “X” indicates that the controller 30A has a defective DRAM 30. As described later, a signal path connecting each chip is formed by connecting the controllers 30A related to the DRAM 30B having no defect.

FIG. 15 shows a detailed configuration of each chip 30 shown in FIG. The controller 30A includes a decoder 33, a direction selection circuit 34, an interface / address counter 35, a power switch 36, a bus 37, a plurality of clamp circuits 18, and an input buffer 38. Input lines XMIT-W, -S, -E and -N and RECVI-W,-
S, -E and -N are connected to a direction selection circuit 34 via a clamp circuit 18 and an input buffer 38 as shown. When input data from a chip (not shown) located on the left side of the chip 30 shown in FIG. 15 is written to the DRAM 30B in FIG. 15, either the input line XMITI-W or RECVI-W is used. On the other hand, when a chip functions as a terminal that simply transmits received data to an adjacent chip, the other input line is used. The output lines XMITO-W, -S, -E and -N and RECVO-W, -S, -E and -N are connected to the direction selection circuit 34.
Extending from. The decoder 33 receives a command signal and a write clock signal WCK supplied from an external device, and controls a direction selection circuit 34, an interface / address counter 35, and a power switch 36. The interface / address counter 35 converts the signal supplied from the decoder 33 into a DRAM.
Generates all signals required for 30B operation. For example,
A row address strobe signal, a column address strobe signal, a write enable signal, an output enable, an address signal, and the like. The read / write operation and the refresh operation of the DRAM 30B are performed by these signals. The power switch 36 supplies power to the DRAM 30B. This ON / OF
The F control is performed by the decoder 33.

FIG. 16 is a block diagram of the direction selection circuit 34 shown in FIG. The direction selection circuit 34 includes two direction selection decoders 35A,
35B, an input buffer 38, four AND gates 39, an OR gate 40, a switch circuit 41 and four AND gates 42. As shown in FIG. 17, each input buffer 38 includes a P-channel MOS transistor 38A and an N-channel MOS transistor 38B.
Formed by MOS inverter. The command signal CMND is input to the decoder 33 in synchronization with the write clock WCK. The decoder 33 outputs a decode signal supplied to the direction selectors 35A and 35B and the switch circuit 41. Input signal XMITI-N,
-W, -S and -E are input to the input buffer 38. Resistor
R2 clamp circuit 18 is connected to the input of input buffer 38. An output of the input buffer 38 is connected to an AND gate 39. This AND gate 39 has a direction selection decoder 35A.
A plurality of control signals generated and output at (4 in the illustrated case)
One) is given. The direction selection decoder 35A sets one of the control signals to a high level according to the command signal CMND. An OR gate 40 is provided at the output of the AND gate 39, and the output is input to the switch circuit 41. The switch circuit 41 supplies a signal from the OR gate 40 to either the interface / address counter 35 or the AND gate group 42 according to the command signal CMND. The AND gate 42 is controlled by the direction selection decoder 35B. The direction selection decoder 35B sets one of the AND gates 42 to active according to the command signal CMND. The signal from the switch circuit 41 passes through the AND gate 40 set to be active, and the output signal X
It is output as one corresponding output signal of MITO-N, -W, -S and -E. The same configuration is used for the input lines RECVI-N, -W,
Also provided for -S and -E.

The direction selection circuit 34 shown in FIG. 15 selects an input line as shown in FIG. In FIG. 18, the block marked X indicates a chip having a defect. When selecting one of the adjacent chips to be subjected to data transfer, each of the adjacent chips is accessed clockwise to determine whether each chip contains a defect. Information as to whether adjacent chips contain defects is provided from an EPROM (not shown) provided on the same board as the wafer scale device.

Apart from FIG. 18, an input line may be selected as shown in FIG. Common line 44 for upper half and lower half of wafer
Is provided. Supply voltage Vcc, Vs through common line 44
s (ground), command signal CMND and write clock W
CK is given to each chip. The space between the chips is formed so as to avoid a cell including a defect and a cut portion of the common line 44.

〔The invention's effect〕

As described above, according to the present invention, it is possible to prevent the occurrence of the floating connection wiring at the input portion of each chip, and to realize this by an efficient manufacturing method.

[Brief description of the drawings]

FIG. 1 is an explanatory view of the principle of the first embodiment of the present invention, FIG. 2 is a schematic diagram showing a reticle of the first embodiment of the present invention, and FIG. 3 is exposure using the reticle shown in FIG. FIG. 4 is a schematic view of a chip wiring pattern according to the first embodiment of the present invention, FIG. 5 is a diagram for explaining the principle of the second embodiment of the present invention, and FIG. FIG. 7 is a schematic diagram of a second embodiment, FIG. 7 is a schematic diagram of a reticle for patterning each chip of the second embodiment of the present invention, FIG. 8 is a diagram showing an example of a reticle used in the second embodiment, FIG. 9 is a view showing an example of a reticle used in a modification of the second embodiment, FIG. 10 is a schematic view of a third embodiment of the present invention, and FIG. 11 is a view of each chip according to the third embodiment. FIG. 12 is a view showing a configuration example of the clamp circuit shown in FIG. 11, FIG. 13 is a view showing a modification of the third embodiment, FIG. FIG. 15 is a diagram showing the electrical configuration of each chip on the wafer, FIG. 15 is a block diagram of each chip shown in FIG. 14, FIG. 16 is a circuit diagram of the direction selection circuit in FIG. 15, and FIG. 18 and 19 are diagrams for explaining chip selection by a connection selection circuit, FIG. 20 is a schematic diagram of a conventional reticle, and FIG. 21 is a conventional reticle. FIG. 3 is a front view of a wafer on which a wiring pattern has been exposed. In the figure, 2 is a wafer, 4 is an internal wiring pattern portion, 5 is an exposure portion, 6
Is a light shielding portion, 7 is a scribe line, 8, 8A, 8B, 8C is a reticle, 9 is a connection wiring pattern portion, 10 is a connection wiring, 10a is a floating connection wiring, 11a, 11b, 12a to 12i are chips, 13a to 13i. Is a reticle, 14 is a connection wiring pattern portion, 17 is an input line (connection wiring), 18 is a clamp circuit, 19a and 19b are chips, 30 is a chip, 30A is a controller, and 30B is a DRAM.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshihiko Iryu 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Takaaki Suzuki 1015 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (72) Inventor Hidenori Nomura 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Inside Fujitsu VSI Co., Ltd. (72) Inventor Hiroyuki Sugaki 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Inside Fujitsu VSI Inc. ( 56) References JP-A-1-303750 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/04, 21/82

Claims (12)

(57) [Claims] 1. A wafer scale semiconductor integrated circuit in which a large number of chips (11a, 11b) formed in a chip area on a wafer (10) are connected by connection wiring, wherein at least a chip located at an outer periphery of the chip area (11
a) means to prevent the connection wiring from floating (1)
8) A wafer-scale semiconductor integrated circuit comprising: 2. The device according to claim 1, wherein said means includes a transistor (Tr1, Tr2) provided between a floating connection wiring connected to an input portion of said chip and a predetermined power supply line.
3. A wafer-scale semiconductor integrated circuit according to claim 1. 3. The means chip includes resistors (R1, R2) provided between a floating connection wiring connected to an input portion of the chip and a predetermined power supply line. 3. A wafer-scale semiconductor integrated circuit according to claim 1. 4. Each chip has four sides, and has connection wiring for signal input on each side, and each connection wiring has a built-in CM.
2. The wafer scale semiconductor integrated circuit according to claim 1, wherein the integrated circuit is connected to an OS input buffer. 5. Each chip is connected to one of the four side connection wires.
The wafer scale semiconductor integrated circuit according to claim 4, further comprising a first direction selection circuit (35A) for selecting a book and taking in an input signal. 6. Each of the chips has a connection wiring for outputting an output signal on the four sides, and a second direction selection for selectively outputting a signal to one of the connection wirings on the four sides. Circuit (35B)
The wafer-scale semiconductor integrated circuit according to claim 5, comprising: 7. A switch circuit for selectively supplying a selected input signal to one of a selected output connection wiring and an internal logic circuit in a chip. 7. The wafer-scale semiconductor circuit according to 6. 8. The wafer according to claim 7, further comprising a decoder connected to the first and second direction selection circuits and the switch circuit, and outputting a signal for controlling the first and second direction selection circuits based on a command. Scale semiconductor integrated circuit. 9. A wafer scale semiconductor integrated circuit in which a number of chips (11a, 11b) formed in a chip area on a wafer (10) are connected by connection wiring, wherein the chip is located at an outer periphery of the chip area. Wherein the connection wiring is not formed on a side of the four sides which is not adjacent to another chip. 10. A method for manufacturing a wafer-scale semiconductor integrated circuit, comprising a step of sequentially exposing a wiring pattern of a plurality of functional chips on a wafer by repeating exposure using a reticle, wherein the reticle (8) A) a connection wiring pattern portion (9) for connection with an adjacent function chip is provided around the wiring pattern portion (4) of the functional chip above, and a light shielding portion (6) is formed around the connection wiring pattern portion (9). Of manufacturing a wafer scale semiconductor integrated circuit. 11. After each chip is formed with the same reticle (8A), further exposure is performed using a reticle (8C) having a window at a position corresponding to the floating connection wiring formed thereby. 11. The method for manufacturing a wafer-scale semiconductor integrated circuit according to claim 10. 12. A reticle (13a to 13h) having a connection wiring pattern portion extending only in the direction of an adjacent chip for exposing each of the chips (12a to 12h) located at the periphery of the chip arrangement on the wafer. 11. A reticle (13i) having four connection wiring pattern portions extending in mutually orthogonal directions is used for exposing each chip (12i) located inside the chip array. The manufacturing method of the wafer-scale semiconductor integrated circuit described in the above.