JP2890670B2 - Synchronous operation compatible waveform generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION <Industrial application field> The present invention relates to a synchronous operation adaptive waveform generator, and more particularly, to an improvement in the time relationship of signals when a plurality of waveform generators are synchronously operated. It is about.

<Related Art> In reproducing a plurality of phenomena that proceed simultaneously, a plurality of waveform generators are operated synchronously according to a common trigger signal.

FIG. 4 is a block diagram showing an example of such a conventional synchronous operation system. The two waveform generators 1 and 2 are provided with a clock CLK and a trigger TRIG applied from an external controller 3.
And generates and outputs a waveform according to the output control signal R / S (RUN / STOP).

By the way, in such a configuration, each waveform generator
Depending on the time relationship between the clock CLK in 1 and 2 and the rise of the trigger TRIG, a waveform may not be output.

That is, for example, the trigger T
In the case of reading the RIG and outputting a waveform, as shown in FIG. 5, when the trigger CLK shown in FIG. 5A rises and the clock CLK shown in FIG. Normal output is obtained. On the other hand, if the rising edge of the trigger TRIG shown in FIG. 6A is later than the rising edge of the clock CLK shown in FIG. 6B, the trigger TRIG cannot be read at the rising edge of the clock CLK. As shown in c), a normal output cannot be obtained.

When the output control signal R / S rises, the initial setting operation of each of the waveform generators 1 and 2 is executed, and the clock C
When the standby state of the LK is set, if the clock CLK is continuously applied, the output start time of the waveform is shifted due to the variation of the initial setting operation time, so that the synchronization between the output waveforms cannot be maintained.

Therefore, the controller 3 controls each of the waveform generators to be controlled.
Clock CLK and trigger whose time relationship is guaranteed so that each waveform generator 1, 2 can operate normally considering the operating conditions of 1, 2
It is necessary to output TRIG and output control signal R / S.

<Problems to be Solved by the Invention> However, according to such a conventional configuration, a separate control device must be prepared in addition to the waveform generating device, which complicates the system configuration and increases the cost.

Then, the control device must appropriately set the time relationship of the output signals in consideration of the operation time of the waveform generator to be controlled, and the operability is poor.

The present invention focuses on such a point, and an object of the present invention is to provide a synchronous operation compatible waveform generator capable of performing synchronous operation of a plurality of waveform generators with a very simple operation without using a special control device. To provide.

<Means for Solving the Problems> A synchronous operation compatible waveform generator according to the present invention includes a clock generator for generating a clock, a trigger generator for generating a trigger, and a signal for controlling an output operation of a waveform signal. An output control signal generating unit, a multiplexer for selecting a signal source for a clock, a trigger, and an output control signal to be supplied to the device according to the master mode and the slave mode, and an operation control unit for controlling the operation of each of these generating units and the multiplexer The multiplexer supplies a clock, a trigger, and an output control signal output from each generating unit to the inside and outside of the device when the master mode is set, and supplies the clock, trigger, and output from the outside when the slave mode is set. A control signal is supplied to the inside of the device.

<Operation> The waveform generator set to the master mode supplies the clock, trigger, and output control signals output from the internal generator to the inside and outside of the device, and the waveform generator set to the slave mode uses the master mode. The clock, trigger, and output control signals applied from the waveform generator set to the are supplied to the inside of the device.

Here, since the waveform generator set to the master mode is configured to supply a clock, a trigger, and an output control signal whose proper time relation is guaranteed to the waveform output to the inside and outside of the device, the master mode is set. And the device set in the slave mode can output waveforms at normal timing.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a main part of one embodiment of the present invention. In the figure, a clock generator 4 generates a clock CLK, and outputs it to a master circuit M side of a synchronization circuit 5, a multiplexer 6, and an output terminal 7. The trigger generator 8 generates a trigger TRIG and outputs it to the synchronization circuit 5. The synchronization circuit 5 outputs the trigger TRIG synchronized with the clock CLK to the master mode M side of the multiplexer 9 and the output terminal 10. The output control signal generator 11 is a signal R / S (RUN / STO) for controlling the output operation of a waveform signal of a waveform generator (not shown).
P) is generated and output to the master mode M side of the multiplexer 12 and the output terminal 13. The input terminal 1 of the external clock CLK is connected to the slave mode S side of the multiplexer 6.
4 is connected, an input terminal 15 of an external trigger TRIG is connected to the slave mode S side of the multiplexer 9, and an input terminal 16 of an external output control signal R / S is connected to the slave mode S side of the multiplexer 12. It is connected. The multiplexers 6, 9, and 12 select the internal when the master mode M is set as a signal source of the clock CLK, the trigger TRIG, and the output control signal R / S supplied to each unit in the device, and select the slaves. If the mode is set to S, the outside is selected. The control unit (CPU) 17
8, 11 and the operation of the multiplexers 6, 9, and 12, and an operation signal from a keyboard 18 provided on an operation panel and an external control bus (for example, an external control bus connected via a connector 19 and an interface 20). It operates according to the control of GP-IB). The mode setting of the multiplexers 6, 9, 12 is performed using, for example, soft keys displayed on a display screen (not shown).

FIG. 2 is a block diagram showing an example of a signal system in a synchronous operation system using three devices shown in FIG.
21 is used as a master device M, and devices 22 and 23 are used as slave devices S. Each multiplexer 6, 9, 12 of the master device 21 is connected to the master mode M side, and each multiplexer 6, 9, 12 of the slave devices 22, 23 is connected to the slave mode S side. And the master device 21
The output terminal 7 of the clock CLK is connected to the input terminal 14 of the clock CLK of each slave device 22, 23, and the output terminal 10 of the trigger TRIG of the master device 21 is connected to the input terminal 15 of the trigger TRIG of each slave device 22, 23. The output terminal 13 of the output control signal R / S of the master device 21 is connected to the input terminal 16 of the output control signal R / S of each of the slave devices 22 and 23.

In such a configuration, the clock generator 4, trigger generator 8, and output control signal generator 11 of the master device 21 control the clock CLK, trigger TRIG, Output control signal R /
S is generated and supplied to each unit in the device and also to each output terminal 7, 10, 13.

On the other hand, each of the slave devices 22 and 23 outputs a clock CLK, a trigger TRIG, and an output control signal R / S whose time relationship suitable for a waveform output input from the master device 21 is input via each of the input terminals 14 to 16. Supply to various parts inside the device.

As a result, the device 22 becomes the master device M and the devices 22 and 2
3 is controlled as a slave device S in accordance with a common signal whose time relationship suitable for the waveform output from the master device M is guaranteed, and the operation is controlled in accordance with a conventional external device. No control device is required.

Since the time relationship between the signals is appropriately set by the control unit on the master device side, the operator need only perform key operations such as a trigger, and the operability is greatly improved.

In the above embodiment, the example in which the number of slave devices is two has been described. However, when three or more slave devices are connected, they may be connected in parallel with the master device.

<Effects of the Invention> As described above, according to the present invention, it is possible to provide a synchronous operation compatible waveform generator capable of performing synchronous operation of a plurality of waveform generators with a very simple operation without using a special control device. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of one embodiment of the present invention, FIG. 2 is a block diagram showing an example of a signal system in a synchronous operation system using three devices of FIG. 1, and FIG. FIG. 4 is a block diagram showing an example of a signal system in the synchronous operation system, and FIGS. 4 and 5 are timing charts for explaining the time relationship of the signal system in FIG. 4 clock generator, 5 synchronization circuit, 6, 9, 12 multiplexer, 7, 10, 13 output terminal, 8 trigger generator, 11
... output control signal generator, 14-16 ... output terminals, 17 ... controller (CPU), 18 ... keyboard, 19 ... connector, 20 ... interface.

Continuation of the front page (56) References JP-A-61-224719 (JP, A) JP-A-61-186006 (JP, A) JP-A-57-14923 (JP, A) JP-A-62-23642 (JP) JP-A-61-234140 (JP, A) JP-A-3-85659 (JP, A) JP-A-51-48232 (JP, A) JP-A-63-16322 (JP, U) (58) Field surveyed (Int. Cl. ⁶ , DB name) H03L 7/00 G06F 1/04 G01R 31/28

Claims (1)

(57) [Claims] A clock generator for generating a clock; a trigger generator for generating a trigger; an output control signal generator for generating a signal for controlling a waveform signal output operation; and a master mode and a slave mode. A multiplexer for selecting a signal source of a clock, a trigger, and an output control signal to be supplied to the inside of the device; and an operation control unit for controlling the operation of each of these generating units and the multiplexer. Synchronous operation in which clocks, triggers, and output control signals output from the unit are supplied to the inside and outside of the device, and when the slave mode is set, clocks, triggers, and output control signals applied from the outside are supplied to the inside of the device. Applicable waveform generator.