JP2893666B2 - Drive-type pseudo failure generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for generating an external disturbance in an operating electronic circuit device by synchronizing a pseudo failure state of an arbitrary signal level in an arbitrary time series with a trigger signal and externally. The present invention relates to a drive-type simulated failure generator to be driven.

[0002]

2. Description of the Related Art For the purpose of debugging, evaluating, and testing a failure detection mechanism and a failure diagnosis program during the development of an electronic circuit device, it is important to cause a pseudo hardware failure to occur in an operating electronic circuit device. Technology. As a conventional effective means for generating a pseudo-failure state from the outside without modification of an electronic circuit device, a pseudo-failure generation device using a drive function (for reference, see NTT Technical Journal
Vol. 1 No. 10 1992.10).

FIG. 5 shows a conventional simulated failure generator using a drive function. In the figure, A is a simulated fault generator, B is an electronic circuit device to be debugged, tested, and evaluated in which IC1 and IC2 are connected by a signal line L1, C is a manual device, D is an external computer, 1 is a panel unit, 2, a control unit; 3, a communication interface unit; 4, a drive circuit unit; and 5, a probe.

In the conventional pseudo-failure generating apparatus A as shown in FIG. 5, regardless of the output state of the IC 1, the IC / LSI is supplied from the external drive circuit section 4 through the probe 5.
In the output stage O of the electronic components (IC1 in FIG. 5) such as
A current is supplied (= driven) so as to make the signal voltage level of the signal line L1 of the target electronic circuit device B constant, so that a fixed 0/1 stack failure state (when the signal voltage level is low and high). It is possible to cause a disturbance (a failure state that becomes constant).

[0005]

However, in actual debugging / evaluation / testing, an intermittent fault state, occurrence of a fault state synchronized with a certain signal, and a fault state in which the signal level changes on the time axis are complicated. Although it is necessary to simulate an advanced failure state, it is impossible for the simulated failure generator A shown in FIG. 5 to generate such a simulated failure.

Here, the present invention is capable of generating a disturbance in a simulated fault state synchronized with a trigger signal and generating a simulated fault state in an arbitrary signal voltage level on an arbitrary time axis. And a drive-type pseudo failure generator.

[0007]

The above-mentioned object can be attained by employing the following novel features of the present invention. That is, the first feature of the present invention is:
Comparison of the signal state of the external signal group with the set trigger condition set value in a pseudo-failure generation device that generates a pseudo-failure disturbance by forcibly flowing a current from outside to the signal line of an operating electronic circuit device Drive ON / OF by
A control unit for outputting a time-series control signal of F and drive voltage level, and a drive ON / O based on the control signal
A drive unit that sequentially outputs drive signals related to the FF and the drive voltage; and a connection unit that connects the drive unit to a signal line of the electronic circuit device and causes the drive signal to flow through the signal line. A drive type simulated fault generator which is configured to be able to generate a simulated fault state of an arbitrary signal voltage level in the electronic circuit device by synchronizing with a trigger signal by controlling in a series.

According to a second feature of the present invention, the control unit according to the first feature includes a setting unit for transmitting a signal to each unit in response to external data input, and a memory unit for storing data from the setting unit. A trigger unit comprising a trigger condition determining unit connected to the external signal group for comparing the signal state of the external signal group with the data in the memory unit, and a memory unit for storing data from the setting unit. A timing control unit that outputs a timing control signal based on a signal from the trigger condition determination unit; and a memory unit that stores data from the setting unit, and outputs a reference voltage control signal based on a signal from the trigger condition determination unit. And a reference voltage control unit.

A third feature of the present invention is that the first or the second
The drive unit according to the above feature is based on a drive circuit unit that sends a drive signal to a connection unit connected to a signal line of an electronic circuit device to be tested, and a control signal input from a timing control unit of a control unit. A drive ON / OFF control unit for controlling the drive ON / OFF timing of the drive circuit unit in time series, and a drive reference voltage value of the drive circuit unit based on a control signal input from a reference voltage control unit of the control unit And a drive voltage control unit that controls the drive type in a time-series manner.

[0010]

According to the present invention, the above means are adopted.
Based on the time series control of the drive ON / OFF and the drive voltage level caused by the trigger of the external signal group, the drive unit drives the signal line connected through the connection unit, so that it is synchronized with the trigger signal and is arbitrary on an arbitrary time axis. It is possible to generate a disturbance in a pseudo failure state at the signal voltage level.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG.
FIG. 2A is a block diagram showing the overall system structure of the drive-type simulated fault generator according to the present embodiment. FIG. 2A shows the voltage value generated from the memory unit of the timing control unit.
2B shows the voltage value generated from the memory unit of the reference voltage control unit, FIG. 2C shows the output value of the target electronic circuit component, and FIG. 2D shows the drive type simulated fault of this embodiment. FIG. 3 is a time-series graph showing output values of signal lines to which the generator is connected, FIG. 3 is a circuit diagram showing an example of a circuit configuration of a drive circuit unit of the drive-type simulated fault generator of this embodiment, and FIG. It is a perspective view which shows an example.

In the figure, A 'is a drive type pseudo failure generator of the present embodiment, B' is an electronic circuit device to be debugged, tested and evaluated in which IC3 and IC4 are connected by a signal line L2, and 6 is a control device. 7, a drive unit; 8, a connection unit; 9, a human interface unit 9a for receiving data input from a human hand C; and a communication unit 9b for receiving data input from an external computer D or the like. Memory unit 10a and trigger condition determination unit 10
b is a trigger unit.

Reference numeral 11 denotes a timing control unit provided with a memory unit 11a, 12 denotes a reference voltage control unit provided with a memory unit 12a, 13 denotes a drive ON / OFF control unit, 14 denotes a drive voltage control unit, 15 denotes a drive circuit unit, and 16 denotes a drive circuit unit. A setting data transfer line 17 is an external drive start instruction signal transfer line,
8 is a drive start signal transfer line, 19 is a timing control signal transfer line, and 20 is a reference voltage control signal transfer line.

Reference numeral 21 denotes an ON / OFF signal transfer line, 22 denotes a voltage signal transfer line, 23 and 24 denote drive signal transfer lines,
Reference numerals 5 and 26 denote IC connection clips, 27 denotes a signal line L2 cable, and 28 denotes a GND terminal cable of an IC or the like.
The same elements as those of the conventional example are denoted by the same reference numerals.

Next, the operation of this embodiment will be described with reference to the drawings. First, the signal line L2 and the ground (GND) terminal in the electronic circuit device B 'to be debugged, tested, and evaluated, in which a failure is to be caused, are connected to the drive circuit unit 15 by the connection unit 8.

As an example of the connection method, IC connecting clips 25 and 26 are attached to cables 27 and 28 shown in FIG.
Attachment to a signal pin of an electronic circuit device to be debugged, tested, and evaluated, such as an SI.

The setting section 9 in the control section 6 transmits data set by a human C or an external computer D from outside through the human interface section 9a or the communication interface section 9b through the setting data transfer line 16 to the trigger section 1
It has a function of writing to the memory unit 10a in the memory unit 0, the memory unit 11a in the timing control unit 11, and the memory unit 12a in the reference voltage control unit 12.

Using this function, the trigger condition set value signal S1 is stored in the memory section 10a of the trigger section 10 and the time series drive ON / O is stored in the memory section 11a of the timing control section 11.
The data signal S1 'of the FF timing set value [FIG.
An example is shown in the memory section 12 of the reference voltage control section 12.
The data signal S1 ″ of the time-series reference voltage set value is shown in FIG.
(B) shows an example].

When the setting section 9 receives a drive start instruction from the human hand C or the external computer D via the human interface section 9a or the communication interface section 9b, the external drive start instruction signal transfer line 1
7, the trigger condition determination unit 10b in the trigger unit 10
To the drive start signal S2.

The trigger condition judging section 10b is connected to the external signal line T
Trigger determination signal groups Ts1 to Ts fetched from T1 to Tn
It has a function of comparing the signal state of sn with the trigger condition set value signal set in the memory unit 10a in the trigger unit 10.
When the trigger determination signal groups Ts1 to Tsn satisfy the condition of the trigger condition set value signal after receiving the drive start signal S2, the timing control unit 11 and the reference voltage control through the drive start signal transfer line 18 as triggers. A drive start signal S2 'is sent to the unit 12.

When the timing control section 11 receives the drive start signal S2 ', the drive ON / OFF timing control signal S3 according to the time series drive ON / OFF timing set value in the internal memory section 11a.
Is transmitted to the drive ON / OFF control unit 13 in the drive unit 7 through the timing control signal transfer line 19.

Similarly, upon receiving the drive start signal S2 ', the reference voltage control section 12 internally stores the internal memory section 12a.
The reference voltage control signal S4 of the drive is sent to the drive voltage control unit 14 in the drive unit 7 through the reference voltage control signal transfer line 20 according to the time-series reference voltage set values in the table.

The drive ON / OFF control unit 13 controls the drive ON / OFF timing of the drive circuit unit 15 in a time series via the ON / OFF signal transfer line 21 in accordance with the timing control signal S3. Further, the drive voltage control unit 14 controls the drive reference voltage value of the drive circuit unit 15 in a time series via the voltage signal transfer line 22 according to the reference voltage control signal S4.

The drive circuit section 15 supplies a current when the output signal level is lower than the drive reference voltage when the drive is ON, and draws a current when the output signal level is higher than the drive reference voltage, thereby forming a signal line. The signal voltage level of L2 is matched with a drive reference voltage that changes in a time series. On the other hand, when the drive is OFF, a high impedance state is set, and the signal on the connected signal line L2 is not affected.

That is, the drive circuit section 15 is connected to the connection section 8
In addition, the signal voltage level of the signal line L2 connected through the cables 23, 24, 27, and 28 can be forcibly changed to a set time-series voltage level.

As an example, as shown in the time-series graph of FIG. 2, the drive-type simulated fault generator of (d) forcibly connects the original output signal voltage waveform of the electronic circuit component to be subjected to (c). The output signal voltage waveform of the signal line is shown. The dotted line in FIG. 2D indicates the electronic circuit component IC.
3. The original output signal voltage and the solid line indicate the signal voltage forcibly changed by the drive of the drive-type simulated fault generator A 'of this embodiment. Further, the drive circuit section 15 can be realized by the electronic circuit shown in FIG. 3, but the method shown in FIG. 3 is only an example.

[0027]

As described above, according to the present invention, a signal line in an electronic circuit device that is operating from the outside can be obtained by merely connecting the connection portion without modifying the target electronic circuit device. It is possible to generate a pseudo failure state of an arbitrary voltage level in an arbitrary time series in synchronization with a trigger signal.

The drive O is synchronized with the trigger signal.
Since the N / OFF timing and the drive voltage level can be freely controlled in a time series, a pseudo disturbance in an intermittent failure state synchronized with a trigger signal, a disturbance in a complex failure having a time series, TTL, ECL, etc. Thus, excellent usefulness and convenience are exhibited, for example, a disturbance of a pseudo failure state can be generated at a signal voltage level corresponding to the type of device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall system structure of a drive-type simulated fault occurrence device according to an embodiment of the present invention.

FIG. 2 (a) shows the voltage value generated from the memory unit of the timing control unit, FIG. 2 (b) shows the voltage value generated from the memory unit of the reference voltage control unit, and FIG. (D) of the output value of the electronic circuit component is a time series graph showing the output value of the signal line to which the drive type pseudo failure generating device of the present embodiment is drive-connected.

FIG. 3 is a circuit diagram illustrating an example of a circuit configuration of a drive circuit unit according to the embodiment.

FIG. 4 is a perspective view showing an example of the connection unit according to the first embodiment.

FIG. 5 is a block diagram showing a system structure of a conventional simulated failure generator using a drive function.

[Explanation of symbols]

A: Pseudo-failure generator A ': Drive-type pseudo-failure generator B, B': Electronic circuit device to be debugged, tested, evaluated C: Manual D: External computer L1, L2: Signal line 1: Panel section 2 , 6 ... Control unit 3 ... Communication interface unit 4, 15 ... Drive circuit unit 5 ... Probe 7 ... Drive unit 8 ... Connection unit 9 ... Setting unit 9a ... Human interface unit 9b ... Communication interface unit 10 ... Trigger unit 10a, 11a, Reference numeral 12a: Memory unit 10b: Trigger condition determination unit 11: Timing control unit 12: Reference voltage control unit 13: Drive ON / OFF control unit 14: Drive voltage control unit 16: Setting data transfer line 17: External drive start instruction signal transfer line 18: Drive start signal transfer line 19: Timing control signal transfer line 20: Reference voltage control signal transfer line 21: ON / OFF signal transfer line 22 ... voltage signal transfer line 23, 24 ... drive signal transfer line 25, 26 ... IC connection clip 27 ... signal line cable 28 ... GND terminal cable S1 ... trigger condition setting value signal S1 ', S1 ″ data signal S2, S2 ′ drive start signal S3 timing control signal S4 reference voltage control signal S5, S6 drive signal T1 to Tn external signal line Ts1 to Tsn trigger trigger signal group

Claims (3)

(57) [Claims] In a simulated fault generating apparatus for generating a simulated fault by externally forcing a current to flow through a signal line of an operating electronic circuit device, a signal state of an external signal group and a set trigger condition are provided. A control unit that outputs a time-series control signal of drive ON / OFF and drive voltage level by comparing with a set value, and a drive unit that sequentially outputs drive signals related to drive ON / OFF and drive voltage based on the control signal And a connection unit that connects the drive unit and the signal line of the electronic circuit device and allows the drive signal to flow through the signal line. A drive-type pseudo-failure generating device, wherein a pseudo-failure state of a signal voltage level is configured to be freely generated in synchronization with a trigger signal. 2. A control section comprising: a setting section for transmitting a signal to each section in response to external data input; a memory section for storing data from the setting section; and a signal for connecting the external signal group to the external signal group. A trigger unit comprising a trigger condition determination unit for comparing a state with data in the memory unit; and a memory unit for storing data from the setting unit, and a timing control signal is generated by a signal from the trigger condition determination unit. 2. A timing control unit for outputting a signal, and a reference voltage control unit having a memory unit for storing data from the setting unit and outputting a reference voltage control signal based on a signal from the trigger condition determination unit. The drive-type simulated failure generator according to the above. 3. A drive circuit for transmitting a drive signal to a connection portion connected to a signal line of an electronic circuit device to be tested or the like, and a drive circuit for transmitting a drive signal to a control signal input from a timing control unit of the control unit. A drive ON / OFF control unit for controlling the drive ON / OFF timing of the drive circuit unit in a time series based on the control signal, and a drive of the drive circuit unit based on a control signal input from a reference voltage control unit of the control unit. 3. The drive-type simulated fault occurrence device according to claim 1, further comprising: a drive voltage control unit that controls a reference voltage value in a time series.