JP2893792B2 - Power MOS transistor with overcurrent protection function - Google Patents
Power MOS transistor with overcurrent protection functionInfo
- Publication number
- JP2893792B2 JP2893792B2 JP2035376A JP3537690A JP2893792B2 JP 2893792 B2 JP2893792 B2 JP 2893792B2 JP 2035376 A JP2035376 A JP 2035376A JP 3537690 A JP3537690 A JP 3537690A JP 2893792 B2 JP2893792 B2 JP 2893792B2
- Authority
- JP
- Japan
- Prior art keywords
- vertical mosfet
- electrode
- thyristor
- mosfet
- vertical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 11
- 230000002265 prevention Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Landscapes
- Electronic Switches (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、パワーMOSトランジスタに関し、特にパワ
ー用の縦型MOSFETに流れる電流を検出し、過電流を自己
制御する過電流防止機能付のパワーMOSトランジスタに
関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power MOS transistor, and more particularly to a power MOS transistor with an overcurrent prevention function of detecting a current flowing in a vertical power MOSFET and self-controlling the overcurrent. Related to MOS transistors.
従来のパワー用の縦型MOSFETは、第４図に示すような
構造を有し、酸化シリコン膜７中のゲート電極６に正の
電圧が印加されるとＰ型のベース領域４のゲート電極６
に面する部分が反転し、ドレイン電極３からソース電極
８へ電流が流れる。The conventional vertical MOSFET for power has a structure as shown in FIG. 4, and when a positive voltage is applied to the gate electrode 6 in the silicon oxide film 7, the gate electrode 6 in the P-type base region 4 is formed.
, The current flows from the drain electrode 3 to the source electrode 8.
〔発明が解決しようとする課題〕 上述した従来のパワー用の縦型MOSFETにおいては、ゲ
ート電極に正の電圧を印加すると、ドレイン・ソース間
に電流が流れるが、ゲート電極に印加する電圧がある程
度（通常10V）以上になると、縦型MOSFET自身では流れ
る電流を制御できないという欠点がある。このため、例
えば負荷が短絡した場合や、リアクトルが磁気飽和した
場合など縦型MOSFETへ過電流が流れ縦型MOSFETが短絡又
は開放状態となる破壊を起すという欠点がある。[Problems to be Solved by the Invention] In the above-described conventional vertical MOSFET for power, when a positive voltage is applied to the gate electrode, a current flows between the drain and the source, but the voltage applied to the gate electrode is increased to some extent. Above (normally 10V), there is a drawback that the vertical MOSFET itself cannot control the flowing current. For this reason, for example, when a load is short-circuited, or when a reactor is magnetically saturated, an overcurrent flows into the vertical MOSFET, and there is a disadvantage that the vertical MOSFET is broken or short-circuited or opened.
また、外付部品を付けて過電流制御する方法はある
が、外付部品の占めるスペース，コスト等の問題があ
る。Although there is a method of controlling overcurrent by attaching external parts, there are problems such as the space occupied by the external parts and the cost.
本発明の過電流防止機能付のパワーMOSトランジスタ
は、第１導電型半導体基板にドレイン電極を共通にして
設けられた第１の縦型MOSFET及び第２の縦型MOSFETと、
前記第１導電型半導体基板内にこれと絶縁して設けられ
た半導体領域に設けられた第３の縦型MOSFET（又はサイ
リスタ）とを含み、前記第１の縦型MOSFETのゲート電極
と前記第３の縦型MOSFETのドレイン電極（又はサイリス
タのアノード電極）の共通接続点と前記第２の縦型MOSF
ETのゲート電極間に挿入された第１の抵抗素子と、前記
第２の縦型MOSFETのソース電極と前記第３の縦型MOSFET
（又はサイリスタ）のゲート電極間に挿入された第２の
抵抗素子と、前記第１の縦型MOSFETのソース電極及び前
記第３の縦型MOSFETのソース電極（又はサイリスタのカ
ソード電極）の共通接続点と前記第３の縦型MOSFET（又
はサイリスタ）のゲート電極間に挿入された第３の抵抗
素子とを有するというものである。A power MOS transistor with an overcurrent prevention function according to the present invention includes a first vertical MOSFET and a second vertical MOSFET provided on a first conductivity type semiconductor substrate with a common drain electrode;
A third vertical MOSFET (or thyristor) provided in a semiconductor region provided insulated from the first conductivity type semiconductor substrate, wherein a gate electrode of the first vertical MOSFET and the third vertical MOSFET are provided. 3 and a common connection point of a drain electrode (or an anode electrode of a thyristor) of the vertical MOSFET and the second vertical MOSFET.
A first resistance element inserted between the gate electrodes of the ET, a source electrode of the second vertical MOSFET, and a third vertical MOSFET;
(Or a thyristor) having a second resistance element inserted between its gate electrodes, and a common connection between a source electrode of the first vertical MOSFET and a source electrode of the third vertical MOSFET (or a cathode electrode of the thyristor). And a third resistance element inserted between the gate electrode of the third vertical MOSFET (or thyristor).
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）及び（ｂ）はそれぞれ本発明の第１の実
施例を示す回路図及び半導体チップの断面図である。FIGS. 1A and 1B are a circuit diagram and a cross-sectional view of a semiconductor chip, respectively, showing a first embodiment of the present invention.
この実施例は、裏面にN+領域２を設けたＮ型Si基板１
にドレイン電極３を共通にして設けられた第１の縦型MO
SFETQ1（ゲート電極６−1,ソース領域５−1,ベース領域
４−１及びＮ型Si基板１をドレイン領域として有してい
る。）及び第２の縦型MOSFETQ2（ゲート電極６−2,ソー
ス領域５−2,ベース領域４−２及びＮ型Si基板１をドレ
イン領域として有している。）と、Ｎ型Si基板１内にこ
れとＰ型領域６により絶縁して設けられたＮ型半導体領
域10に設けられた第３の縦型MOSFETQ3（ゲート電極６−
3,ソース領域５−3,ベース領域４−３及びＮ型半導体領
域10をドレイン領域として有している。）とを含み、第
１の縦型MOSFETQ1のゲート電極６−１と第３の縦型MOSF
ETQ3のドレイン電極９の共通接続点と第２の縦型MOSFET
Q2のゲート電極６−２間に挿入された第１の抵抗素子R1
と、第２の縦型MOSFETQ2のソース電極８−２と第３の縦
型MOSFETQ3のゲート電極６−３間に挿入された第２の抵
抗素子R2と、第１の縦型MOSFETQ1のソース電極８−３及
び第３の縦型MOSFETQ3のソース電極８−３の共通接続点
と第３の縦型MOSFETQ3のゲート電極６−３間に挿入され
た第３の抵抗素子R3とを有するというものである。第１
〜第３の抵抗素子はいずれも多結晶シリコン膜抵抗素子
であり、Ｎ型Si基板上に絶縁膜（図示しない）を介して
設けられているものとする。In this embodiment, an N-type Si substrate 1 having an N +
Vertical MO provided with a common drain electrode 3
An SFET Q1 (having a gate electrode 6-1, a source region 5-1, a base region 4-1, and an N-type Si substrate 1 as a drain region) and a second vertical MOSFET Q2 (a gate electrode 6-2, a source Region 5-2, the base region 4-2, and the N-type Si substrate 1 as drain regions) and an N-type provided in the N-type Si substrate 1 by being insulated from the P-type region 6. The third vertical MOSFET Q3 (gate electrode 6-6) provided in the semiconductor region 10.
3, a source region 5-3, a base region 4-3, and an N-type semiconductor region 10 are provided as drain regions. ), The gate electrode 6-1 of the first vertical MOSFET Q1 and the third vertical MOSFET
Common connection point of drain electrode 9 of ETQ3 and second vertical MOSFET
A first resistor R1 inserted between the gate electrodes 6-2 of Q2
A second resistance element R2 inserted between the source electrode 8-2 of the second vertical MOSFET Q2 and the gate electrode 6-3 of the third vertical MOSFET Q3; and a source electrode 8 of the first vertical MOSFET Q1. -3 and a third resistor element R3 inserted between the gate electrode 6-3 of the third vertical MOSFET Q3 and the common connection point of the source electrode 8-3 of the third vertical MOSFET Q3. . First
Each of the third to third resistance elements is a polycrystalline silicon film resistance element, and is provided on an N-type Si substrate via an insulating film (not shown).
第２図は本発明の過電流防止機能付パワーMOSFETを動
作させた時の各部の電圧波形を示す図である。FIG. 2 is a diagram showing voltage waveforms at various parts when the power MOSFET with an overcurrent prevention function of the present invention is operated.
まずゲート端子Ｇに正の電圧を印加すると主パワーMO
SFETである第１の縦型MOSFETQ1がオン状態となり続いて
縦MOSFETである第２の縦型MOSFETQ2がオン状態となる。
この遅れ時間は抵抗R1により決定される。第１の縦型MO
SFETQ1は流れる電流によりドレイン・ソース間に電圧を
発生する。その電圧を第２の縦型MOSFETQ2の分割抵抗
（R2,R3）において検出し一定以上の電圧が発生した場
合は第３の縦型MOSFETQ3がオンし第１の縦型MOSFETQ1の
ゲート電圧を下げ電流を一定値におさえるように動作す
る。従って過電流は防止される。First, when a positive voltage is applied to the gate terminal G, the main power MO
The first vertical MOSFET Q1 which is an SFET is turned on, and subsequently, the second vertical MOSFET Q2 which is a vertical MOSFET is turned on.
This delay time is determined by the resistor R1. The first vertical MO
The SFET Q1 generates a voltage between the drain and the source by the flowing current. The voltage is detected by the divided resistors (R2, R3) of the second vertical MOSFET Q2, and when a voltage equal to or higher than a predetermined value is generated, the third vertical MOSFET Q3 is turned on, and the gate voltage of the first vertical MOSFET Q1 is reduced Operates so as to keep a constant value. Therefore, overcurrent is prevented.
第３図（ａ）及び（ｂ）は、本発明の第２の実施例を
示す回路図及び半導体チップの断面図である。FIGS. 3A and 3B are a circuit diagram and a cross-sectional view of a semiconductor chip showing a second embodiment of the present invention.
この実施例は、第３の縦型MOSFETの代りに、Ｎ型半導
体基板１内に、酸化シリコン膜11により絶縁されたＰ型
半導体領域12に設けられたサイリスタＳを用いたもので
ある。過電流を検出してサイリスタＳが導通すると第１
の縦型MOSFETQ1を流れる主電流を止めてそのままの状態
を保持する。従って過電流状態が長く続かないので安全
である利点がある。In this embodiment, a thyristor S provided in a P-type semiconductor region 12 insulated by a silicon oxide film 11 in an N-type semiconductor substrate 1 is used instead of the third vertical MOSFET. When the thyristor S conducts upon detecting an overcurrent, the first
The main current flowing through the vertical MOSFET Q1 is stopped to maintain the state as it is. Therefore, there is an advantage that the overcurrent state does not last for a long time and is safe.
以上説明したように、本発明は第１の縦型MOSFETに流
れる電流によって発生するドレイン・ソース間電圧を第
２の縦型MOSFET及び第2,第３の抵抗によって検出し第１
の縦型MOSFETのゲート電圧を制御することにより、ドレ
イン端子とソース端子間に流れる電流を一定値以下に制
御する過電流防止機能付パワーMOSトランジスタを提供
できる効果がある。As described above, according to the present invention, the drain-source voltage generated by the current flowing through the first vertical MOSFET is detected by the second vertical MOSFET and the second and third resistances to detect the first voltage.
By controlling the gate voltage of the vertical MOSFET described above, there is an effect that a power MOS transistor with an overcurrent prevention function that controls the current flowing between the drain terminal and the source terminal to a certain value or less can be provided.
第１図（ａ）及び（ｂ）は、本発明の過電流防止機能付
のパワーMOSFETの第１の実施例を示す回路図及び半導体
チップの断面図、第２図は、第１の実施例の動作を表す
波形図、第３図（ａ）及び（ｂ）は第２の実施例を示す
回路図及びサイリスタ部の半導体チップの断面図、第４
図は、従来のパワーMOSFETを示す半導体チップの断面図
である。 １……Ｎ型Si基板、２……N+型領域、３……ドレイン電
極、4,4−1,4−2,4−３……ベース領域、5,5−1,5−2,5
−３……ソース領域、6,6−1,6−2,6−３……ゲート電
極、7,7−1,7−２……酸化シリコン膜、8,8−1,8−2,8
−３……ソース電極、９……ドレイン電極、10……Ｎ型
半導体領域、11……酸化シリコン膜、12……Ｐ型半導体
領域、13……Ｎ領域、14……サイリスタのゲート領域、
15……カソード領域、16……アノード電極、17……カソ
ード電極、18……サイリスタのゲート電極、Ｄ……ドレ
イン端子、Ｇ……ゲート端子、IDS……ドレイン・ソー
ス間電流、Q1……第１の縦型MOSFET、Q2……第２の縦型
MOSFET、Q3……第３の縦型MOSFET、R1……第１の抵抗素
子、R2……第２の抵抗素子、R3……第３の抵抗素子、Ｓ
……ソース端子、SR……サイリスタ、VDS……ドレイン
・ソース間電圧、VG……ゲート電圧。1 (a) and 1 (b) are a circuit diagram and a cross-sectional view of a semiconductor chip showing a first embodiment of a power MOSFET with an overcurrent prevention function according to the present invention, and FIG. 2 is a first embodiment. FIGS. 3 (a) and 3 (b) are circuit diagrams showing a second embodiment, a sectional view of a semiconductor chip of a thyristor section, and FIGS.
FIG. 1 is a sectional view of a semiconductor chip showing a conventional power MOSFET. 1 .... N-type Si substrate, 2 .... N + type region, 3 .... Drain electrode, 4,4-1,4-2,4-3 ... Base region, 5,5-1,5-2, Five
-3: Source region, 6,6-1, 6-2, 6-3 ... Gate electrode, 7,7-1,7-2 ... Silicon oxide film, 8,8-1,8-2, 8
-3: Source electrode, 9: Drain electrode, 10: N-type semiconductor region, 11: Silicon oxide film, 12: P-type semiconductor region, 13: N region, 14: Gate region of thyristor,
15 ...... cathode region, 16 ...... anode electrode, 17 ...... cathode electrode, 18 a gate electrode of the ...... thyristor, D ...... drain terminal, G ...... gate terminal, I DS ...... drain-source current, Q1 ... ... First vertical MOSFET, Q2 ... Second vertical MOSFET
MOSFET, Q3 ... third vertical MOSFET, R1 ... first resistor, R2 ... second resistor, R3 ... third resistor, S
...... source terminal, SR ...... thyristor, V DS ...... drain-to-source voltage, V G ...... gate voltage.
Claims (1)
通にして設けられた第１の縦型MOSFET及び第２の縦型MO
SFETと、前記第１導電型半導体基板内にこれと絶縁して
設けられた半導体領域に設けられた第３の縦型MOSFET
（又はサイリスタ）とを含み、前記第１の縦型MOSFETの
ゲート電極と前記第３の縦型MOSFETのドレイン電極（又
はサイリスタのアノード電極）の共通接続点と前記第２
の縦型MOSFETのゲート電極間に挿入された第１の抵抗素
子と、前記第２の縦型MOSFETのソース電極と前記第３の
縦型MOSFET（又はサイリスタ）のゲート電極間に挿入さ
れた第２の抵抗素子と、前記第１の縦型MOSFETのソース
電極及び前記第３の縦型MOSFETのソース電極（又はサイ
リスタのカソード電極）の共通接続点と前記第３の縦型
MOSFET（又はサイリスタ）のゲート電極間に挿入された
第３の抵抗素子とを有することを特徴とする過電流防止
機能付のパワーMOSトランジスタ。1. A first vertical MOSFET and a second vertical MOSFET provided with a common drain electrode on a first conductivity type semiconductor substrate.
An SFET and a third vertical MOSFET provided in a semiconductor region provided insulated from the first conductivity type semiconductor substrate.
(Or a thyristor), and a common connection point between a gate electrode of the first vertical MOSFET and a drain electrode (or an anode electrode of the thyristor) of the third vertical MOSFET and the second thyristor.
A first resistance element inserted between the gate electrodes of the vertical MOSFETs, and a second resistor inserted between the source electrode of the second vertical MOSFET and the gate electrode of the third vertical MOSFET (or thyristor). 2 and a common connection point between the source electrode of the first vertical MOSFET and the source electrode (or the cathode electrode of the thyristor) of the third vertical MOSFET and the third vertical MOSFET.
A power MOS transistor having an overcurrent prevention function, comprising: a third resistance element inserted between gate electrodes of a MOSFET (or thyristor).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2035376A JP2893792B2 (en) | 1990-02-15 | 1990-02-15 | Power MOS transistor with overcurrent protection function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2035376A JP2893792B2 (en) | 1990-02-15 | 1990-02-15 | Power MOS transistor with overcurrent protection function |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03238869A JPH03238869A (en) | 1991-10-24 |
| JP2893792B2 true JP2893792B2 (en) | 1999-05-24 |
Family
ID=12440183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2035376A Expired - Lifetime JP2893792B2 (en) | 1990-02-15 | 1990-02-15 | Power MOS transistor with overcurrent protection function |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2893792B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3164065B2 (en) | 1998-06-24 | 2001-05-08 | 日本電気株式会社 | Semiconductor device |
-
1990
- 1990-02-15 JP JP2035376A patent/JP2893792B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03238869A (en) | 1991-10-24 |
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