JP2900911B2 - 3D graphic processing memory system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to 3D graphics
Regarding processing memory system, especially software 3D
3D graphics processing memory for performing image generation processing
Regarding the stem .

[0002]

[0003]

2. Description of the Related Art Conventionally, an image generation method called a Z-buffer method is disclosed in, for example, an image processing method disclosed in Japanese Patent Application Laid-Open No. 04-362794. This Japanese Patent Application Laid-Open No. 04-3627
In the image processing method disclosed in Japanese Unexamined Patent Application Publication No. 94-94, a dedicated Z-buffer independent of a frame buffer is provided. If the calculated value of the value is smaller than the value of the Z buffer, the process of updating the Z buffer with a new calculated value of the Z value is performed to generate image data.

In a system having such a dedicated Z buffer, when 3D image processing is not performed, Z
Since the buffer-only memory is not used at all, there is a problem in terms of memory utilization efficiency and economy.

[0005] Further, a method has been considered in which a virtual Z buffer is provided on a main memory to eliminate a dedicated Z buffer, thereby improving the use efficiency and economy of the memory.

[0006]

The above-mentioned prior art has the following problems.

First, in the prior art, since the graphic controller has a memory dedicated to the Z buffer, the memory dedicated to the Z buffer is not used at all when the 3D processing is not performed. There was a problem that the economy was poor. Further, the required capacity of the Z buffer changes according to the screen resolution, but the capacity is fixed in the dedicated Z buffer, so that the efficiency is also low in this regard.

Secondly, in order to solve the above-mentioned problems, a method is provided in which a virtual Z-buffer is provided on the main memory to eliminate the dedicated Z-buffer and improve the economic efficiency. Since the main memory bus is occupied each time the display refresh is performed, the efficiency of access from the CPU side is reduced, resulting in a problem that the system performance is reduced.

Third, when a virtual Z-buffer is provided on the main memory and a dedicated Z-buffer is eliminated, the CPU can handle the most easily by packing the color information and the Z-value information for each pixel. Is a data format that is arranged on a memory, but only the color information of each pixel is required for display and the Z value information is not required. Therefore, a process of removing the Z value information by the CPU at the time of display must be performed. . Performing such processing by the CPU leads to a decrease in the performance of the entire system.

An object of the present invention is to provide a Z-buffer on a main memory without having a dedicated Z-buffer memory, thereby enabling 3D graphic processing involving processing in the depth direction, and further, independent of a main memory bus. An object of the present invention is to provide a 3D graphic processing memory system capable of preventing a reduction in speed due to the influence of display refresh by preparing a display frame buffer having a bus.

[0011]

In order to achieve the above object, a 3D graphic processing memory system according to the present invention comprises:
3D image generation by software by CPU 3
In a D graphic system, a main memory having a virtual Z buffer and storing color information and Z value information of 3D image data continuously arranged for each pixel unit is provided independently of the main memory. A display frame buffer for storing color information of the 3D image data, a graphic controller for reading color information stored in the display frame buffer and controlling 3D display processing, the main memory, and the display frame. Switch means for controlling transfer of pixel data between buffers; and the display frame buffer is connected to the switch means and the graphic controller by a dedicated bus independent of a bus of the main memory.

In the 3D graphic processing memory system according to the present invention, the switch means selectively switches between a bus of the main memory and a dedicated bus of a display frame buffer by a signal from the graphic controller. It is characterized by having done.

In the 3D graphic processing memory system according to the present invention, when the image data is transferred from the main memory to the display frame buffer by the switch means, only the color information for each pixel is removed except for the Z value information. Is transferred.

According to a fourth aspect of the present invention, in the 3D graphic processing memory system according to the present invention, the switch means includes a plurality of semiconductor switches each having a bit width of color information and Z value information of the 3D image data. Is selectively intermittently transmitted to transfer color information for each pixel on the main memory to the display frame buffer.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a 3D graphic processing memory system according to an embodiment of the present invention. Referring to FIG. 1, a 3D graphic processing memory system according to the present embodiment includes a CPU 10, a memory controller 15 having a data bus buffer, and a main memory for storing programs and holding image data and corresponding Z value data. 20; a display frame buffer 30 for holding the generated image data; a graphic controller 40 for actually controlling the display; and a switch circuit 50 for transferring data between the main memory 20 and the display frame buffer 30. Be composed.

That is, in the present embodiment, a virtual Z buffer is provided on the main memory 20 and a dedicated Z buffer is provided.
The configuration eliminates the buffer memory.

The CPU 10 and a main memory 20 for holding image data and the corresponding Z value data are connected by a main memory bus 21. The display frame buffer 30 that holds the generated image data is connected to the graphic controller 40 via a dedicated bus 31.

The dedicated bus 31 is connected to the main memory bus 21 via a switch circuit 50 for transferring data between the main memory 20 and the display frame buffer 30. The switching operation of the switch circuit 50 is controlled by a control signal 41 from the graphic controller 40.

Next, the operation of the 3D graphic processing memory system according to the present embodiment configured as described above will be described.

First, the CPU 10 executes a program stored in the main memory 20. When the program is a 3D graphic application program corresponding to the present invention, the CPU 10 generates a 3D image by calculating the coordinates of the object, and holds the image data in the main memory 20. At this time, the Z value in the depth direction is also stored in the main memory 20.

The color information and the Z value for each pixel of the image data are packed and continuously arranged on the main memory 20 in a data format that the CPU 10 can easily handle.

The generated image data is transferred from the main memory bus 21 to the display frame buffer 30 via the switch circuit 50 at a certain timing and held by the graphic controller 40.

When image data is transferred from the main memory 20 to the display frame buffer 30, the switch circuit 5
With 0, only the color information of each pixel of the image data is selected, and only the color information is transferred to the display frame buffer 30. That is, when transferring the image data from the main memory 20 to the display frame buffer 30, the switch circuit 50 removes the Z-value data not related to the display and transfers only the color information.

When a 3D image is not generated, the switch circuit 50 is switched to transfer the image data from the main memory 20 to the display frame buffer 30 without processing.

In a normal state other than the time of image data transfer, the switch circuit 50 operates to completely disconnect the main memory bus 21 from the frame buffer bus 31 and does not hinder the flow of data in the main memory bus 21.

On the other hand, the image data held in the display frame buffer 30 is periodically transmitted to the frame buffer bus 31.
Through the graphic controller 40 and displayed on the display device. As described above, by temporarily storing the generated image data in the display frame buffer 30, the image data can be displayed without obstructing the flow of data in the main memory 20.

The switch circuit 50 can switch the main memory bus 21 and the frame buffer bus 31 one-to-one under the control of the graphic controller 40 via the control signal 41. In this state, since the data of the display frame buffer 30 flows directly to the main memory bus 21, the CPU 10 can refer to the contents of the display frame buffer 30 and write the data directly. Mutual data transfer between the memory 20 and the display frame buffer 30 is also possible.

As described above, the display frame buffer 30 independent of the main memory 20 is provided, and the display data is transferred using the frame buffer bus 31 independent of the main memory bus 21. The main memory bus 21 is not occupied every time the display is refreshed, so that a decrease in system performance due to a decrease in access efficiency due to the display refresh can be reduced.

When image data is transferred from the main memory 20 to the display frame buffer 30, the Z-value information in the Z-buffer is discarded so that only the color information of the pixel is transferred, so that the CPU 10 displays the image data at the time of display. It is not necessary to perform processing for removing Z-value information unnecessary for display from image data, and it is possible to prevent performance degradation due to the processing for removing Z-value information.

[0031]

Next, embodiments of the present invention will be described with reference to the drawings. Assuming that each of the image data and the Z value stored in the main memory 20 has a width of 16 bits, for example, when the width of the main memory bus 21 is 64 bits, image data of two pixels is held.

Specifically, as shown in FIG. 2, the color information “C” and the Z value “Z” for each pixel are represented by C0 · Z0, C1
.. Are stored in the main memory 20 in a packed data format such as Z1,.

FIG. 3 shows a specific configuration example of the switch circuit 50. Referring to FIG. 3, the switch circuit 50 includes seven semiconductor switches 51 to 57 each having a 16-bit width.
It is composed of These semiconductor switches 51 to 57 are
It is individually controlled by the graphic controller 40 through a control signal 41.

At the time of generating a 3D image, the CPU 10 creates a new image reflecting the depth direction using the Z buffer method based on the Z value, and as a result updates the contents of the main memory 20. At this time, the image data on the main memory 20 is continuously stored for each pixel in a data format as shown in FIG. By repeating the same processing, image data for one screen is created on the main memory 20.

Referring to FIG. 3, in a normal state, semiconductor switches 51 to 57 of switch circuit 50 are cut off, and data on main memory bus 21 and data on frame buffer bus 31 are transferred to each other. There is no.

If image data for one screen is generated on the main memory 20 in the format of FIG. 2 and the main memory bus 21 and the frame buffer bus 31 are not used for other purposes, the semiconductor switch 51 , 53 are turned on, and the other semiconductor switches are opened, so that “Word0” of the main memory bus 21 and “Word0” of the frame buffer bus 31 become “Word2” of the main memory bus 21 and the “Word2” of the frame buffer bus 31. “Wordl” conducts. At this time, when a read cycle is started for the main memory 20 and a write cycle is started for Word0 and Wordl of the frame buffer 31, the color information C0 and C1 shown in FIG. Written.

At the next timing, only the semiconductor switch 54 and the semiconductor switch 56 are turned on.
The color information C2 and C3 shown in FIG. 2 are written into the display frame buffer 30.

As described above, by controlling the semiconductor switches 51 to 57 of the switch circuit 50 to transfer image data, only the color information is transferred to the display frame buffer 30 through the connected switch circuit 50. Will be held.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments.

[0040]

As described above, according to the 3D graphic processing memory system of the present invention, first, there is obtained an effect that 3D graphic processing can be performed relatively economically. The reason is that there is a virtual Z buffer on the main memory without having a memory dedicated to the Z buffer.

Second, when 30 images are generated, an effect is obtained that a decrease in system performance due to a decrease in access efficiency from the CPU due to the influence of image display refresh can be reduced. The reason is that a display frame buffer independent of the main memory is provided, and display data is transferred using a bus independent of the bus of the main memory.

Third, there is no need for the CPU to remove the Z value information unnecessary for display from the image data at the time of display, and it is possible to prevent the performance from being reduced by the process of removing the Z value information. can get.
The reason is that a switch means is provided between the main memory bus and the display frame buffer bus so that the two buses can be electrically separated from each other by a signal from the controller and the data can be transferred bidirectionally. This is because, when transferring image data from the main memory to the display frame buffer, the Z value information in the Z buffer is discarded, and only the color information of the pixel is transferred.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a 3D graphic processing memory system according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining an image data format on a main memory in the 3D graphic processing memory system according to the embodiment of the present invention.

FIG. 3 is a block diagram illustrating a specific configuration example of a switch circuit according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 CPU 15 Memory controller 20 Main memory 21 Main memory bus 30 Display frame buffer 31 Frame buffer bus 40 Graphic controller 41 Control signal 50 Switch circuit 51-57 Semiconductor switch

Claims (3)

(57) [Claims] 1. A 3D graphic system for generating a 3D image by software using a CPU, comprising a virtual Z buffer and continuously arranging color information and Z value information of 3D image data for each pixel. A main memory for storing, a display frame buffer provided independently of the main memory for storing color information of the 3D image data, and a 3D display process for reading the color information stored in the display frame buffer. A graphic controller for performing control, and switch means for controlling transfer of pixel data between the main memory and the display frame buffer. The display frame buffer is connected to a dedicated bus independent of a bus of the main memory. It is connected to the switch means and the graphic controller, the switch By means, for displaying from said main memory
When transferring image data to the frame buffer,
A 3D graphic processing memory system wherein only color information for each pixel is transferred except for information . 2. The apparatus according to claim 1, wherein said switch means selectively switches between a bus of said main memory and a dedicated bus of a display frame buffer in accordance with a signal from said graphic controller. 3
D graphics processing memory system. 3. The switch means comprises a plurality of semiconductor switches having the same bit width as the color information and the Z-value information of the 3D image data, and selectively turning on and off the semiconductor switches to allow the main switch to be turned on and off. The 3D graphic processing memory system according to claim 1, wherein color information for each pixel on a memory is transferred to the display frame buffer.