JP2906522B2 - Bias circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a bias circuit.

[Conventional technology]

Generally, when an analog circuit such as an operational amplifier is configured by a complementary MOS transistor (CMOS transistor), a constant current source 5 is required.

Usually, as shown in FIG. 3, p-channel transistor Q _n
Is biased to an appropriate voltage V _rp or V _rn , and the transistors Q _p and Q _n are operated in a saturation region to form a constant current source 5.

The bias circuit 10 _a is commonly connected to the source power supply V _DD,
P-channel MOS transistors Q ₁ and Q ₂ having a common gate and a current mirror configuration outputting a bias voltage V _rp from the drain terminal of the primary side transistor, and a secondary side source having a common gate and the primary side being directly connected to the primary side Is the source resistance R
Connected in parallel between the source and the drain of the p-channel MOS transistor to Q ₁ and a self-bias unit 4 _a with n-channel transistors Q _3, Q ₄ of the connected current mirror arrangement to a source power supply V _SS, secondary side through the startup portion 1 _a having a startup transistor Q ₆ of n channels that are
have. The dimensions of the transistors Q ₁ , Q ₂ , Q ₃ , and Q ₄ constituting the gate bias section 4 _a are respectively (W / L) ₁ , (W / L
_{L) 2, (W / L} ) 3, (W / L) 4 to the bias current I _B is obtained by calculating as follows.

First, when (W / L) ₁ <(W / L) ₂ , (W / L) ₃ = (W / L) ₄ , Equation (1) is obtained.

Then, when (W / L) ₁ = (W / L) ₂ , (W / L) ₃ <(W / L) ₄ , Equation (2) is obtained.

Where k = μ _N C _ox / 2, μ _N is the electron mobility, C _ox
Is the oxide film capacity per unit area.

Power supply voltage dependency of the bias current I _B flowing through the bias circuit as can be seen from the above equation is small.

Therefore, when an operational amplifier is configured using this bias circuit, the increase in power consumption when the power supply voltage V _DD is increased is suppressed, and the advantage that the performance of the operational amplifier such as gain is less dependent on the power supply voltage is reduced. is there.

If the transistors Q ₁ , Q ₂ , Q ₃ , and Q ₄ of the constant current section 4 _a are in the off state when the power is turned on, this bias circuit is used only when the power is turned on in order to avoid stabilization in the off state. circuit have the circuit to the original operating point from the start-up transistor Q ₆ infused with start current, has a so-called start-up section 1a.

[Problems to be solved by the invention]

When an operational amplifier is configured with the above-described conventional bias circuit, if a plurality of operational amplifiers are formed on one chip, the number of DC current paths is increased by the number of operational amplifiers, and power consumption is increased.

The direct current path of the bias circuit itself shown in FIG. 3 also has a total of four paths by adding two of the paths for the start-up circuit.

Originally, the start-up circuit only needs to operate when the power is turned on. Continuing to supply a DC current after the start-up operation ends increases power consumption.

Furthermore, the conventional bias circuit has a small temperature dependence of the bias current in a low power supply voltage range, but has a disadvantage that the bias current sharply increases when the power supply voltage exceeds a certain voltage value.

 The cause is as follows.

That is, the gate voltage v ₆ Startup transistor Q ₆ is fixed to the value of the equation (3).

And the power supply voltage v ₆ to the voltage V _DD is greater because the transistor Q ₆ becomes a first (4) a current flows to turn on the V _DD power supply to the transistor Q ₃ through the transistor Q _6.

[Means for Solving the Problems] A bias circuit according to the present invention is configured such that a source is commonly connected to a high-voltage power supply, a gate is commonly connected, and a first bias voltage is supplied from a drain end of a primary transistor to the outside. A mirrored p-channel transistor pair,
The primary and secondary sides of the p-channel transistor have drains connected to each other so that the primary side and the secondary side intersect with each other and the gates are connected in common, and a second bias voltage is applied from the drain end of the primary side transistor to the outside. A self-bias unit having a current mirror configuration of an n-channel transistor pair, wherein the source on the secondary side is supplied via a source resistor and the source on the primary side is directly connected to a low-voltage power supply, and the secondary side of the p-channel transistor pair A start-up unit having a start-up transistor that connects a source and a drain in parallel between the source and the drain of the transistor and inputting a control signal to start bias supply, wherein the start-up unit receives a control signal. And a single pulse having a predetermined pulse width is used as a gate of the start-up transistor. DOO to provide a pulse generator which supplies, and the self-bias unit is constituted by a switch section for inputting the control signal to the control terminal to open and the source resistor and the low voltage power supply.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram of one embodiment of the present invention.

The self-biasing unit 4 includes an n-channel switching transistor Q ₅ between the source resistance and the source resistor R connected to the source of the n-channel transistor Q ₄ which is the primary side of the self-biasing unit 4 _{a in} FIG. Switch unit 3 is inserted.

Further, start-up unit 1, and a pulse generator 2 and startup transistor Q ₆ having a delay circuit D in place of the third view of the startup portion 1 _a.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation of the circuit of FIG.

When the control signal S _C is at the low level (hereinafter abbreviated as "L"),
The transistor Q ₆ of the start-up part 1 is off,
Output bias voltage for p-channel transistor gate of the constant current source for the switching transistor Q ₅ is also turned off
V _rp is at a high level (hereinafter abbreviated as “H”), the bias voltage V _rN for the n-channel transistor gate is “L”, and the circuit current I _DD is zero.

When the control signal S _C becomes "H", at the rising time t ₁ of the signal S _C, the pulse signal S _T of the pulse width T pulse generator 1 is single
The occurs, turn on the start-up transistor Q _6.

Then, the transistor Q ₅ for the switch since the ON by the control signal S _C, the bias circuit 10 is stabilized time t ₂ later in the original operating point.

When the control signal S _C becomes "L" at time t ₃ again, the output bias voltage V _rp is "H", V _rN becomes "L", the circuit current I _DD is zero.

By using the bias circuit of the present invention, the DC current I _DD can be set to zero when the operational amplifier is not operated, and the circuit can be reduced in power consumption.

Further, the DC current path of the bias circuit itself has two paths, which is half that of the conventional circuit shown in FIG.

Here, as a second embodiment, the pulse generator 2
Even if the pulse signal S _T is inverted, if the polarity of the start-up transistor Q ₆ and the switching transistor Q ₅ in the reverse, the same effect can be obtained.

〔The invention's effect〕

As described above, the bias circuit of the present invention can reduce the DC current path of the bias circuit itself by connecting the switch transistors in series, and further, can reduce the DC current to zero when the operational amplifier is not operated. There is an effect that power can be used.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a timing chart of signals of respective parts for explaining the operation of the circuit of FIG. 1, and FIG. 3 is a circuit diagram of an example of a conventional bias circuit. is there. 1. Startup part 2. Pulse generator 3.
Switch section, 4… Self-biasing section, D… Delay circuit, I _DD
... circuit current, Q _1, Q ₂ ... p-type transistors, Q _3, Q ₄ ... n-type transistor, Q ₅ ... switching transistors, Q ₆ ... startup transistor, R ... source resistance, S _C ... control signal, S _T : pulse signal, T: pulse width, V _DD : drain power supply voltage, V _SS : source power supply voltage, V _rN : bias voltage for n-channel transistor gate, V _rp ... bias voltage for p-channel transistor gate.

Claims (1)

(57) [Claims] A p-channel transistor pair having a current mirror structure, wherein a source is commonly connected to a high-voltage power supply, a gate is commonly connected, and a first bias voltage is supplied from a drain end of a primary transistor to the outside. The primary side and the secondary side of the channel transistor are connected so that the primary side and the secondary side intersect with each other, the drains are connected to each other, the gates are connected in common, the second bias voltage is supplied to the outside, and the secondary side source is the source. A self-biasing unit having a current mirror configuration of an n-channel transistor pair in which a source on a primary side is directly connected to a low-voltage power supply via a resistor, and a source / source of a transistor on a secondary side of the p-channel transistor pair.
A start-up unit having a start-up transistor for connecting a source and a drain in parallel between the drains and inputting a control signal to start bias supply, wherein the start-up unit receives a control signal and outputs a predetermined pulse. A pulse generator for supplying a single pulse having a width to the gate of the start-up transistor; and a switch unit for inputting the control signal to a control terminal between the source resistor and the low-voltage power supply. A bias circuit.