JP2803291B2 - Bias circuit - Google Patents

Description

The present invention relates to a bias circuit, and more particularly to an operation circuit.
The present invention relates to a startup circuit when a bias circuit of an amplifier (operational amplifier) is a self-bias type.

[Conventional technology]

Compatible with analog circuits such as operation amplifiers
When using a MOS transistor (CMOS transistor), a constant current source is required. Normally, an appropriate voltage is applied between the gate and source of a P-type transistor or an N-type transistor, and the transistor is operated in a saturation region to serve as a constant current source.

FIG. 3A is a circuit diagram showing the simplest bias circuit.

In FIG. 3A, the bias circuit is a P-type MOS.
It comprises transistors Q ₁ and Q ₂ , an N-type MOS transistor Q ₃ and a resistor R. Here, the gate width / gate length of the MOS transistors Q ₁ , Q ₂ , Q ₃ , that is, W / L (μm) is all 20/10, and the resistance value of the resistor R is 100 KΩ. Bias current I _B of the bias circuit is given by the following equation.

Here, V _DD is the power supply voltage, and V _TP is the threshold voltage of the P-type transistor. The bias circuit configuration, but is simple, as shown in FIG. 3 (b), since the bias current I _B is substantially proportional to the power supply voltage V _DD, disadvantage that the power consumption at the power supply voltage is high is large There are, also because of the power supply voltage V _DD dependence of the bias current I _B, there is a disadvantage that the performance of the gain equalization is dependent on the power supply voltage V _DD.

The power supply voltage dependency is small circuit bias current, there is a fourth view (a) MOS transistor Q ₄ by adding a circuit, such as, commonly referred to as self-biasing circuit. Assuming that the dimensions of the MOS transistors Q ₁ , Q ₂ , Q ₃ , and Q ₄ are (W / L) ₁ , (W / L) ₂ , (W / L) ₃ , and (W / L) ₄ , , Given by:

If (W / L) ₁ <(W / L) ₂ , (W / L) ₃ = (W / L) ₄ , If (W / L) ₁ = (W / L) ₂ , (W / L) ₃ <(W / L) ₄ , Here, k '= a μ _N C _ox / 2, the mu _N electron mobility, C _ox is the oxide film capacitance per unit area, R is the resistance value of the resistor R.

As shown in the power supply voltage dependency fourth diagram of the bias current flowing through the bias circuit (b), the range of V _DD = 2V~8V, next I _B 0.2 .mu.A, to take an approximately constant value, the power supply voltage In this case, the power consumption is increased and the dependence of the performance of the operational amplifier on the power supply voltage is improved. FIG. 4 (a)
W / L (μm) is the same as in FIG. 3 (a).

This bias circuit has two operating points. One is a normal operating point through which the bias current I _B, the other is an undesirable operating point bias current I _B becomes zero. To explain the latter operating point, first, the MOS transistor Q ₄
Is turned off, the potential of the node _Vrp rises to the power supply voltage level, and the MOS transistors Q ₁ and Q ₂ are turned off. The potential of the contact V _rN the MOS transistor Q ₁ is turned off is lowered to ground level, MOS transistors Q _3, Q ₄ are turned off. When this operating point is set, the bias current is fixed to zero even if the power supply voltage is increased, and the operation amplifier does not operate. To avoid this, a start-up circuit as shown in FIG. 5A is usually added.

The operation of the start-up circuit will be described with reference to FIG. Start-up circuits added to the left side of the bias circuit are MOS transistors Q ₅ , Q ₆ , Q ₇ , Q ₈ , Q ₉
Having. Where the W / L of transistors Q ₁ , Q ₂ , Q ₃ , Q ₅ , Q ₇ , Q ₈
([Mu] m) is 20/10, the transistor Q ₄ are 40/10, the transistor Q ₆ is 10/100, the transistor Q ₉ is 10/50, R is 100 K.OMEGA.

Assuming that the bias current of the bias circuit composed of the MOS transistors Q ₁ , Q ₂ , Q ₃ , Q ₄ and the resistor R is zero,
The potential of the node _Vrp has risen to the power supply voltage level. Therefore, the MOS transistors Q ₅ , Q ₆ , Q ₇ , Q ₈ that constitute the start-up circuit are all off, and the MOS transistors
The gate potential of the Q ₉ is raised to the power supply voltage V _DD level. On the other hand, since the potential of the node V _rN is at ground level, it takes the power supply voltage between the gate and source of the transistor Q _9, the transistor Q ₉ is turned on. When the transistor Q ₉ is turned on, through the transistor Q ₉ from the power source, current flows into the transistor Q _3, a bias circuit is set to the normal operating point. Then, the current also flows through the transistors Q ₅ and Q ₇ and Q ₆ and Q ₈ on the startup circuit side. When a current flows through the bias circuit and the start-up circuit, the gate potential of the transistor Q ₉ is lowered, the node
The potential of _VrN rises. Therefore, the gate-source voltage of the transistor Q ₉ is reduced, the transistor Q ₉ is turned off, ends the start-up operation.

[Problems to be solved by the invention]

The above-described conventional bias circuit has a low power supply voltage dependency of the bias current at a low power supply voltage, but has a drawback that the bias current sharply increases when the power supply voltage exceeds a certain value. The cause is as follows. The gate potential of the transistor Q ₉ is the power supply voltage level Only at the point where the power supply voltage drops. Becomes a or more, the transistor Q ₉ is turned on, current flows from the power source through the transistor Q ₉ to the transistors Q _{3. Here, V TP6, V TN9, V} TN3 , respectively transistors Q _6, Q _9, the threshold voltage of Q _3, k 'is _{μ P C ox / 2, μ} P
Is the hole mobility, and (W / L) ₆ is the dimension of Q ₆ .

In order to increase the voltage at which the bias current starts to increase, it is necessary to reduce the size (W / L) ₆ of the transistor Q ₆ because the threshold voltage of the transistor is fixed. The dimensions of the transistor Q ₆ in FIG. 5 (b) W / L = 1
The power supply voltage dependence of the bias current when 0/100 (μm) is shown. Bias current I _B has started to increase from around V _DD = 3.5V. To increase this to about 6V, the dimensions of the transistor Q ₆ must be reduced to W / L = 10/2000 ( μm) degree, in disadvantages that the additionally required area size L only long min is there.

The configuration of the bias circuit according to the present invention is to provide a bias circuit that solves the above-mentioned drawbacks and prevents the current from increasing rapidly even when the power supply voltage is increased.

[Means for solving the problem]

The configuration of the present invention is characterized in that, in a bias circuit in which a start-up circuit having a constant current element is connected to a self-bias circuit, the constant current element is a depletion type MOS transistor in which a gate is short-circuited to a source or a drain. And

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1A is a circuit diagram of the bias circuit shown in FIG. 1, and FIG. 1B is a characteristic diagram of the bias current versus the power supply voltage.

1 (a), in Fig. 1 (b), the bias circuit of this embodiment, FIG. 5 depletion transistor of P-type transistor Q ₆ is N-type in the conventional bias circuit shown in (a) It is replaced by a constant current element consisting of Q _ND (W / L is 20/10). Other parts are the same as in FIG. 5 (a). Transistor Q _ND and constant current value are bias current I _B
As will become smaller, determines the size of the transistor Q _ND. By doing so, even when the power supply voltage V _DD rises, the gate potential of the transistor Q ₉ is kept low and avoid the transistor Q ₉ is turned on. Therefore, it is possible to prevent a sudden rise of the bias current as seen in the conventional bias circuit.

FIG. 2 is a circuit diagram of a bias circuit according to another embodiment of the present invention. 2, in this embodiment, a P-type depletion transistor _QPD (W / L = _23/10 ) is used as a constant current element instead of the transistor _QND of FIG. 1A. Other parts are the same as those in FIG. 1 (a).

Note that the conductivity type of the depletion transistor used for this constant current element may be the conductivity type that is easier to make in the process used.

〔The invention's effect〕

As described below, the present invention reduces the power supply voltage dependency of the bias current by using a constant current element composed of a depletion type MOS transistor in the start-up circuit, and has the effect of significantly reducing the circuit layout area. is there.

[Brief description of the drawings]

FIG. 1A is a circuit diagram of a bias circuit according to an embodiment of the present invention, FIG. 1B is a characteristic diagram of a bias current vs. power supply voltage of the circuit of FIG. 1A, and FIG. FIG. 3 (a) is a circuit diagram of a normal bias circuit, and FIG. 3 (b) is a diagram of a bias current vs. power supply voltage of the circuit of FIG. 3 (a). FIG. 4 (a) is a circuit diagram of a bias circuit having no power supply voltage dependency, FIG. 4 (b) is a characteristic diagram of bias current vs. power supply voltage of the circuit of FIG. 4 (a),
FIG. 5 (a) is a circuit diagram of a conventional bias circuit, and FIG. 5 (b) is a characteristic diagram of a bias current versus a power supply voltage of the circuit of FIG. 5 (a). Q ₁ to Q ₉ ...... MOS transistors, R ...... resistance, I _B ...... bias current, V _DD, V _SS ...... supply voltage.

Claims (2)

(57) [Claims] A source terminal is connected to a high potential side of a power supply, and a current-mirror-connected p-channel MOS transistor pair and a source terminal of a secondary-side transistor are connected to a source terminal of a primary-side transistor via a source resistor. The first terminal connected to the low potential side of the power supply together with the source terminal and connected to the current mirror
N-channel MOS transistor pair and the p-channel M
A first p-channel MOS transistor for start-up in which the source terminal and the drain terminal of the transistor on the secondary side of the OS transistor pair are connected in parallel, and a source terminal connected to the low potential side of the power supply and a current mirror connected Two n-channel MOS transistor pairs, a second p-channel MOS transistor connected between the drain terminal of the transistor on the primary side of the second n-channel MOS transistor pair and the high potential side of the power supply, And a constant current source connected between the drain terminal of the transistor on the secondary side of the pair of n-channel MOS transistors and the high potential side of the power supply. A drain terminal is connected to a drain terminal of a transistor on the secondary side of the first n-channel MOS transistor pair, and a first bias voltage is supplied from the connection point. Is connected to the outside, and the drain terminal of the transistor on the secondary side of the pair of p-channel MOS transistors is connected to the drain terminal of the transistor on the primary side of the first pair of n-channel MOS transistors. , A second bias voltage is supplied to the gate of the second pair of p-channel MOS transistors, and the first bias voltage is supplied to the gate of the second pair of p-channel MOS transistors. A connection point between the first p-channel MOS transistor and a connection point between the first p-channel MOS transistor and the current source. 2. The bias circuit according to claim 1, wherein said constant current source is a depletion type MOS transistor having a gate terminal and a source terminal short-circuited.