JP2912700B2 - Simulation method for semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for simulating a semiconductor integrated circuit, and more particularly, to a timing check in a logic simulation of a sequential circuit. Aiming to enable simulation of a large number of semiconductor integrated circuits, a simulation of timing check in which logic data of a timing check circuit including a timing detection circuit section and a judgment circuit section is added to logic data of a sequential circuit in logic design data. Logic design data for a simulation processor, detects each simulation signal input to the sequential circuit based on the timing detection circuit unit, and makes the determination based on the detection signal detected by the timing detection circuit unit. The circuit part A method for simulating a semiconductor integrated circuit, comprising: determining whether a normal simulation signal is input to the sequential circuit; and performing error detection of the sequential circuit based on the determination result and an output signal of the sequential circuit. The determination circuit of the timing check circuit is replaced with a determination program provided in an external device, and logic data of the timing detection circuit except for the determination circuit is added to the sequential circuit input to the simulation processor. The detection signal detected by the unit is output to the external device, and the external device determines whether a normal simulation signal has been input based on the determination program.

The present invention relates to a method of simulating a semiconductor integrated circuit, and more particularly to a timing check in a logic simulation of a sequential circuit.

Simulation at the stage of logic design of a semiconductor integrated circuit is performed using a simulation processor. As the scale and density of semiconductor integrated circuits increase, the capacity of the simulation processor itself becomes insufficient. Therefore, it is necessary to reduce the number of gates added only for the simulation to cope with the capacity shortage.

[Prior Art] Conventionally, when logic design data of a semiconductor integrated circuit is created, simulation is performed by inputting the logic design data and test pattern data to an engineering workstation (EWS). The EWS has a built-in simulation processor for performing a simulation, and the logic design data of the semiconductor integrated circuit is input to the processor. At this time, since a timing check simulation is required for a sequential circuit such as a latch circuit, a flip-flop circuit, and a counter in the semiconductor integrated circuit, a timing check circuit has to be added according to the sequential circuit.

More specifically, as for the counter in the logic design data, for example, as shown in the block diagram of FIG. 3, a timing check circuit including a detection circuit unit 3 and a judgment detection circuit unit 4 is necessary for the counter 2. Met.

The detection circuit unit 3 includes a counter circuit 5 for counting the width of the clock CK having the logical value “H” and a counter circuit 6 for counting the width of the clock CK having the logical value “L”. Therefore, each of the counter circuits 5 and 6 counts each clock width of the clock CK input to the counter 2.

The detection circuit unit 3 detects whether data DA, DB, DC, and DD have been input before the predetermined clock CK is input, and a predetermined time elapses after the predetermined clock CK is input. Hold the same clock CK until data D
A hold circuit 8 is provided for detecting whether A, DB, DC, or DD has been input.

Further, the detection circuit unit 3 detects whether the data DA, DB, DC, DD has been input before the load signal L is input, and a setup circuit 9 until a predetermined time elapses after the load signal L is input. The data DA, DB,
A hold circuit 10 is provided to detect whether DC or DD has been input.

The judgment detection circuit unit 4 includes a judgment circuit 11 and an exclusive OR circuit 12
The determination circuit 11 receives the detection results from the circuits 5 to 10, and inputs the clock CK, the load signal L, and the data DA to DD input to the counter 2 at normal timing based on the detection results. Is determined. Then, the judgment circuit 11 inputs the result of the judgment to the exclusive OR circuit 12. And the exclusive OR circuit
The simulation result of the timing check of the counter 2 is output with the signal from the counter 2 input to 12.

This timing check circuit reads out from a library prepared in advance and automatically adds it to the counter 2.

That is, the logic data of the timing check circuit used only for the timing check in addition to the logic design data of the semiconductor integrated circuit is input to the simulation processor. Therefore, assuming that the number of gates of the semiconductor integrated circuit is, for example, 10,000, and the number of gates of the timing check circuit added to the sequential circuit in the semiconductor integrated circuit is 1,000, the simulation processor will use the timing check circuit. It is necessary to secure a capacity in consideration of the number of gates.

[Problems to be Solved by the Invention] However, as the number of gates of the semiconductor integrated circuit increases with the increase in the scale and density of the semiconductor integrated circuit, the number of sequential circuits also increases, and the number of timing check circuits also increases. There has been a problem that the number of gates of the circuit increases and the capacity of the simulation processor becomes insufficient, so that simulation cannot be performed. Therefore,
It is conceivable to add a simulation processor, but since the simulation processor is very expensive, there is a problem in terms of cost in adding the simulation processor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to reduce the number of gates of a timing check circuit as much as possible, thereby enabling a simulation of a semiconductor integrated circuit having a large number of gates. It is an object of the present invention to provide a method of simulating a semiconductor integrated circuit that can be used.

Means for Solving the Problems In order to achieve the above object, the present invention provides a timing in which logic data of a timing check circuit including a timing detection circuit section and a determination circuit section is added to logic data of a sequential circuit in logic design data. The logic design data for the simulation of the check is input to the simulation processor, and each simulation signal input to the sequential circuit is detected based on the timing detection circuit unit, and the detection signal detected by the timing detection circuit unit is detected. A semiconductor integrated circuit for determining whether or not a normal simulation signal is input to the sequential circuit based on the determination result and performing an error detection of the sequential circuit based on the determination result and an output signal of the sequential circuit; In a circuit simulation method, a determination circuit section of the timing check circuit Is replaced with a determination program provided in an external device, logic data of a timing detection circuit unit excluding the determination circuit unit is added to the sequential circuit input to the simulation processor, and a detection signal detected by the timing detection circuit unit is added. An output is provided to the external device, and the external device determines whether a normal simulation signal is input based on the determination program.

[Operation] Each simulation signal input to the sequential circuit is detected by a timing detection circuit unit, and the detection signal detected by the timing detection circuit unit is input to an external device having a determination program for determining the detection signal. You. Then, the external device determines whether or not a normal simulation signal is input based on the detection signal based on the determination program.

As a result, the determination circuit section is replaced by a determination program provided in an external device, so that the number of gates can be reduced accordingly.

Embodiment An embodiment of a semiconductor integrated circuit embodying the present invention will be described below with reference to FIG. The same components as those in the conventional example are denoted by the same reference numerals, and description thereof is omitted.

The determination circuit for checking the timing of the counter 2 includes a computer 13 as an external device and an exclusive OR circuit 12. Then, the exclusive OR circuit 12
Are added as part of the logic design data in the simulation processor 1.

On the other hand, the computer 13 has a judgment program composed of the C language, and the detection results of the circuits 5 to 10 of the detection circuit unit 3 are respectively input. And computer 13
Input the detection results of the circuits 5 to 10 and determine the timing check of the counter 2 based on the determination program.

The exclusive OR circuit 12 in the simulation processor 1 outputs a simulation result of the timing check of the counter 2 based on the output signal from the counter 2 and the determination result from the microcomputer 13. ing.

Next, the operation of the semiconductor integrated circuit configured as described above will be described.

A counter 2 in the simulation processor 1 operates based on each simulation signal, and a timing detection circuit unit 3 constituting a timing check circuit.
Detects a simulation signal input to the counter 2.

That is, the counter circuit 5 of the timing detection circuit unit 3 counts the width of the clock CK having the logical value “H”, and the counter circuit 6 counts the width of the clock CK having the logical value “L”. Then, both counter circuits 5 and 6 output the result of detecting the width of the clock CK to the computer 13.

The setup circuit 7 detects whether the data DA, DB, DC, and DD have been input before the predetermined clock CK is input to the counter 2, and the hold circuit 8 has detected that the predetermined clock CK has been input to the counter 2. Thereafter, the same clock CK is held until a predetermined time elapses, and it is detected whether the data DA, DB, DC, and DD have been input. Then, the detected result is stored in the computer 13.
Output to

Further, the setup circuit 9 detects whether the data DA, DB, DC, and DD have been input before the load signal L is input to the counter 2, and the hold circuit 10 determines whether a predetermined time has elapsed after the load signal L was input. The load signal L is held until the data DA, DB, DC, and DD are input. And
The detection result is output to the computer 13.

Then, the detection results of the circuits 5 to 10 are input to the computer 13, and the computer 13 outputs the determination results to the exclusive OR circuit 12 of the simulation processor 1 based on a determination program. On the other hand, the exclusive OR circuit 12 receives an output signal from the counter 2.

The exclusive OR circuit 12 outputs an error detection signal of the counter 2 based on the determination result from the computer 13 and the output signal from the counter 2.

As described above, in the present embodiment, the determination made by the conventional determination circuit 11 is performed by the determination program processing of the computer 13, so that the conventional determination circuit 11 in the timing check circuit is unnecessary, and the timing check circuit is not necessary. Only the number of gates can be reduced, and a simulation of a semiconductor integrated circuit having a large number of gates can be performed.

FIG. 2 shows a flip-flop 15 which is one of the sequential circuits.
1 shows the configuration of the timing check circuit.

Then, the timing detection circuit unit 3 includes the counter circuits 16, 1
7, a setup circuit 18, and a hold circuit 19. Also in this case, the detection signals of the circuits 16 to 19 are output to the computer 13, which makes a determination by the determination program for the flip-flop 15, and outputs it to the exclusive OR circuit 20.

[Effects of the Invention] As described above in detail, the present invention can reduce the number of gates of the timing check circuit as much as possible, and can simulate a semiconductor integrated circuit having a large number of gates. Having.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a semiconductor integrated circuit of the present invention, FIG. 2 is a block diagram showing another example of the semiconductor integrated circuit of the present invention, and FIG. 3 is a block diagram showing a conventional semiconductor integrated circuit. is there. In the figure, 1 is a simulation processor, 2 is a counter and flip-flop as a sequential circuit, 3 is a timing detection circuit section, and 4 is a determination circuit section.

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 17/50 JICST file (JOIS)

Claims (1)

(57) [Claims] 1. A simulation of timing check in which logic data of a timing check circuit comprising a timing detection circuit section (3) and a judgment circuit section (4) is added to logic data of a sequential circuit (2) in logic design data. Logic design data for simulation processor (1)
And detects each simulation signal input to the sequential circuit (2) based on the timing detection circuit section (3), and detects the simulation signal based on the detection signal detected by the timing detection circuit section (3). The determination circuit unit (4) determines whether a normal simulation signal has been input to the sequential circuit (2), and uses the determination result and an output signal of the sequential circuit (2) to determine whether the sequential circuit (2) has a normal simulation signal. In a simulation method of a semiconductor integrated circuit for performing error detection, the determination circuit unit (4) of the timing check circuit is replaced with a determination program provided in an external device, and a sequential circuit (1) input to the simulation processor (1) is used. 2)
The logic data of the timing detection circuit section (3) excluding the determination circuit section (4) is added to the detection signal, and the detection signal detected by the timing detection circuit section (3) is output to the external device.
A method for simulating a semiconductor integrated circuit, wherein the external device determines whether or not a normal simulation signal is input based on the determination program.