JPH0566632B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for simulating a digital logic circuit realized with basic logic elements such as an AND gate, an OR gate, or a flip-flop.

[Background of the invention]

Logic circuit simulation involves constructing a logic circuit model equivalent to a digital logic device on a general-purpose computer before manufacturing, and checking whether it operates correctly. Conventionally, methods for realizing such logic circuit simulations have been described, for example, in "C.ACM" (Volume 12,
102-110, 1969) and ``Exclusive Simulation of Activities in Digital Networks'' (Exclusive
Simulation of Activity in Digital Networks)
It is published under the title. According to this method, the output signal values of all the basic logic elements constituting the logic circuit can be calculated in detail. In the case of an element whose output signal value is determined after a certain period of time has passed, it is not guaranteed whether the output signal value will be determined at low level or high level depending on the combination of input applied signal values, and these values must be calculated one by one. It is extremely difficult to do so.

FIG. 2 shows a simple logic circuit including a flip-flop. In Figure 2, 20 is a gate, 21 and 22
is a flip-flop. flipflop 2
1 and 22 generally consist of a data input terminal D, a clock input terminal T, a set input terminal S, a reset input terminal R, and output data terminals Q ₀ and Q ₁ ,
The signal value of data input terminal D is the clock input terminal T.
is reflected in the output value by changing the signal value. FIG. 3a shows a time chart during normal operation of the flip-flops 21 and 22.

However, when the change time T D of the data input terminal _D and the change time T _C of the clock input terminal T are not in the time relationship required to set the data input signal value in the flip-flops 21 and 22, that is, when the input setup time 31 , when the input hold time 32 does not satisfy the limit value of the logic element, the output signal value becomes temporarily uncertain and becomes fixed after a certain time elapses. FIG. 3b shows a time chart in this case. Conventionally, no consideration has been given to expressing the generation state of an uncertain signal value that physically exists in such a flip-flop using a logic circuit simulation.

[Purpose of the invention]

An object of the present invention is to determine the unstable state of a flip-flop at a specific time in a simulation of a logic circuit including a flip-flop, and to easily check the operation of subsequent stage circuits.

[Summary of the invention]

The gist of the present invention is that the operation of determining the output signal from the generation of the undefined output signal value of the flip-flop is performed by logic circuit simulation, thereby facilitating the investigation of the cause of malfunction of the logic circuit. In other words, in the present invention, when a factor that causes the flip-flop to become uncertain occurs, the output signal value is made into an uncertain value, and after the time at which the flip-flop can be made certain has elapsed, it is applied as a definite signal value to the subsequent logic element model. This is what I did.

[Embodiments of the invention]

FIG. 4 shows a connection relationship for expressing a logic circuit model on the main memory of a computer. Fourth
In the figure, 41 and 42 are element tables,
This corresponds to, for example, the flip-flops 21 and 22 in FIG. The information in each element table includes the type of element (AND, OR, flip-flop, etc.), element delay time (the time required to propagate the signal value from the input terminal to the output terminal), unstable value time width (unstable value The signal value table address, source element address, and sink element address. The element table 41 is connected to the preceding element table (not shown) by its element address, and connected to the succeeding element table 42 and other similar element tables by its sink element address. The source element address indicates an address on the main memory where the previous stage element table is stored, and the sink element address indicates an address on the main memory where the subsequent stage element table is stored. 43 is element table 4
1, and its storage address on the main memory is indicated by the signal value table address in the element table. Signal value table 4
3 is for holding the input/output signal value (0 or 1) of the element in question, but in the present invention, it is also used to hold the uncertain cutoff time and the change time of the input signal (for example, flip-flop D, S, T). can bring information.

FIG. 5 is called a time loop, and the time loop itself is the same as that disclosed in the above-mentioned document. Each slot of time loop 50 is
Elapsed time T, T+1 of logic circuit simulation
...corresponds to event records 51, 52, 5
3.... are connected. An event record consists of a signal value and an element address of an element (sink element) to which the signal value propagates. For example, in the example of the logic circuit shown in FIG. 2, if the signal IN becomes "1" at time T and the output of the gate 20 changes from "0" to "1", the event record 51 records the signal value as "1". " is set, and the address of the element table of the flip-flop 21 is set as the element address.

Next, the processing procedure of the logic circuit simulation of the present invention will be explained with reference to FIG.

When the time loop 50 in FIG. 5 advances to time T, the event records 51, 54, and 55 connected to that slot are retrieved (step 11). Then, the signal value to the sink element of the element address indicated in the retrieved event record is propagated, the sink element table (Fig. 4) indicated by the element address is read, and the output signal value of the sink element is read. The signal value to be calculated and propagated to the next sink element and the event record of the element address shown in the element table are connected to the slot after the element delay time (steps 15, 16, 17, etc.). At this time,
The signal value propagating to the sink element becomes an uncertain value,
When the element being processed further satisfies the uncertainty generation condition in the flip-flop, the negative value of the data input signal value is connected to an event record after the time equal to the element delay time D plus the unstable value time width _TW . This is the event record 52 in FIG. 5, where "X" indicates that the signal value is uncertain. Furthermore, an uncertain termination time is obtained from the signal value table attached to the element table, and an event record with a determined signal value is connected to the slot at that time. Event record 53 in FIG. 5 shows this.

When the time loop progresses and the event record 52 is executed, it is extracted from the source element address in the previous stage element table, and if it is significantly different from the uncertain termination time of the source element, and if it is an event record for uncertain termination, the event record's Perform processing, and if the condition is not met, do not execute the event record (steps 12, 13, 14, etc.).

In the manner described above, the logic circuit simulation continues until the preset time is reached.

〔Effect of the invention〕

According to the present invention, by determining the unstable state of a flip-flop at a specific time, the logical operation of a digital logic device including a flip-flop can be confirmed by logic circuit simulation.
Additionally, it is possible to easily find the cause of the malfunction.

[Brief explanation of the drawing]

FIG. 1 is a flowchart for explaining the logic circuit simulation method according to the present invention, FIG. 2 is a diagram showing an example of the logic circuit, FIG. 3 is an operation time chart of FIG. 2, and FIG. 4 is a flowchart for explaining the logic circuit simulation method according to the present invention. A diagram showing an element table and an element signal value table to be used, and FIG. 5 is a diagram showing the relationship between a time loop and an event record. 41, 42...Element table, 43...Element signal value table, 50...Time loop, 51-5
5...Event record.

Claims (1)

[Claims] 1. A method in which a logic circuit model equivalent to a digital logic circuit is constructed on an electronic computer and a logic circuit simulation is executed based on input signal stimulation applied from the outside, in which a flip-flop logic element is not included in the logic circuit model. The stable value time width information is set to determine whether the flip-flop logic element is in an unstable state. If the flip-flop logic element is in an unstable state, the output signal value of the flip-flop logic element model is set to an uncertain value, and then the time when it is considered stable is determined. A logic circuit simulation method characterized in that, after the elapse of time, the output signal value of the flip-flop logic element model is determined based on the input signal value, thereby preventing continuation of an unstable state to the logic element model at a subsequent stage.