JP2913799B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2913799B2 JP2913799B2 JP2222917A JP22291790A JP2913799B2 JP 2913799 B2 JP2913799 B2 JP 2913799B2 JP 2222917 A JP2222917 A JP 2222917A JP 22291790 A JP22291790 A JP 22291790A JP 2913799 B2 JP2913799 B2 JP 2913799B2
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- insulating film
- groove
- channel stopper
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 16
- 239000003990 capacitor Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- -1 arsenic ions Chemical class 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に１トランジスタ型メ
モリセルを有する半導体装置に関する。Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a one-transistor type memory cell.
１トランジスタと１容量部からなるダイナミックメモ
リセルを有する半導体装置の一例として溝型容量部を有
するものがある。As an example of a semiconductor device having a dynamic memory cell including one transistor and one capacitor, there is a semiconductor device having a groove-type capacitor.
第３図（ａ），（ｂ）は従来の半導体装置の一例を示
す断面図及びレイアウト図である。3A and 3B are a cross-sectional view and a layout diagram showing an example of a conventional semiconductor device.
第３図（ａ），（ｂ）に示すように、Ｐ型シリコン基
板１の表面に設けて素子形成領域を区画するフィールド
酸化膜２と、フィールド酸化膜２の下面に設けたチャネ
ルストッパ６と、素子形成領域に設けた溝と、溝の内面
に設けたＮ型拡散層５と、Ｎ型拡散層５を含む表面に設
けた容量絶縁膜４と、素子形成領域上に設けたワード線
８を兼ねるゲート電極７に整合して素子形成領域に設け
且つ一方がＮ型拡散層５と接続し、他方がビット線９に
接続するソース・ドレイン領域12とを有して構成してい
る。As shown in FIGS. 3A and 3B, a field oxide film 2 provided on the surface of a P-type silicon substrate 1 to define an element formation region, and a channel stopper 6 provided on the lower surface of the field oxide film 2 A groove provided in the element forming region, an N-type diffusion layer 5 provided on the inner surface of the groove, a capacitor insulating film 4 provided on a surface including the N-type diffusion layer 5, and a word line 8 provided on the element forming region. And a source / drain region 12 connected to the N-type diffusion layer 5 and the other connected to the bit line 9.
この従来の半導体装置は、電荷蓄積領域となる不純物
拡散層とチャネルストッパとが隣接しているため空乏層
内に存在する不純物濃度が高く、リーク電流が大きく、
容量部の電荷保持特性が悪いという問題点があった。In this conventional semiconductor device, the impurity concentration in the depletion layer is high because the impurity diffusion layer serving as the charge storage region and the channel stopper are adjacent to each other, and the leakage current is large.
There has been a problem that the charge retention characteristics of the capacitance section are poor.
本発明の半導体装置は、一導電型半導体基板上に設け
て素子形成領域を区画するフィールド絶縁膜と、前記フ
ィールド絶縁膜の下面に設けたチャネルストッパと、前
記素子形成領域に設けて上端に前記フィールド絶縁膜の
端部がひさし状に突出した溝と、前記チャネルストッパ
と隔離して前記溝内の側面及び底面に設けた逆導電型の
拡散層と、前記拡散層を含む表面に設けた容量絶縁膜
と、前記容量絶縁膜上に設けて前記溝内を充填する容量
電極と、前記拡散層に接続して素子形成領域に設けた転
送ゲート用トランジスタとを有する。The semiconductor device of the present invention includes a field insulating film provided on a semiconductor substrate of one conductivity type to define an element forming region, a channel stopper provided on a lower surface of the field insulating film, and an upper end provided on the element forming region. A groove in which the end of the field insulating film protrudes like an eaves, a diffusion layer of a reverse conductivity type provided on the side and bottom surfaces in the groove separated from the channel stopper, and a capacitance provided on a surface including the diffusion layer An insulating film; a capacitor electrode provided on the capacitor insulating film to fill the trench; and a transfer gate transistor connected to the diffusion layer and provided in an element formation region.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図（ａ），（ｂ）は本発明の第１の実施例を示す
断面図及びレイアウト図である。FIGS. 1A and 1B are a sectional view and a layout diagram showing a first embodiment of the present invention.
第１図（ａ），（ｂ）に示すように、Ｐ型シリコン基
板１の上に選択的にP+型のチャネルストッパ６及びフィ
ールド酸化膜２を設けて素子形成領域を区画し、フィー
ルド酸化膜２の端部を含む素子形成領域を異方性プラズ
マエッチングにより選択的にエッチングして内径が0.8
〜1.0μｍ、深さ３〜５μｍの溝と、溝の上端にフィー
ルド酸化膜２の端部が0.1〜0.2μｍの幅で突出したひさ
し状の突出部を設ける。次に、斜め入射回転イオン注入
技術によりドーズ量１×1014〜１×1015cm-2のヒ素イオ
ンをイオン注入し、突出部の下部以外の溝の内面にＮ型
拡散層５を形成する。ここで、チャネルストッパ６とＮ
型拡散層５は隔離された状態で形成される。次に、溝内
を合む表面に容量絶縁膜４を形成し、溝内を充填した容
量電極３を形成する。次に、素子形成領域上に設けたリ
ード線８と一体化したゲート電極７に整合して一方がＮ
型拡散層５と接続するソース・ドレイン領域12を素子形
成領域に設ける。次に、ソース・ドレイン領域12の他方
と接続するビット線９とを設けてメモリセルを構成す
る。As shown in FIGS. 1 (a) and 1 (b), a P + type channel stopper 6 and a field oxide film 2 are selectively provided on a P type silicon substrate 1 to partition an element formation region, and The element formation region including the end of the film 2 is selectively etched by anisotropic plasma etching to have an inner diameter of 0.8.
A groove having a thickness of about 1.0 μm and a depth of 3 μm to 5 μm, and an eave-shaped protrusion having an end of the field oxide film 2 protruding with a width of 0.1 μm to 0.2 μm are provided at the upper end of the groove. Next, arsenic ions having a dose of 1 × 10 14 to 1 × 10 15 cm −2 are ion-implanted by the oblique incidence rotation ion implantation technique, and the N-type diffusion layer 5 is formed on the inner surface of the groove other than the lower part of the protrusion. . Here, the channel stopper 6 and N
The mold diffusion layer 5 is formed in an isolated state. Next, the capacitance insulating film 4 is formed on the surface that fits in the groove, and the capacitance electrode 3 filling the groove is formed. Next, one of the N is aligned with the gate electrode 7 integrated with the lead wire 8 provided on the element formation region.
A source / drain region 12 connected to the mold diffusion layer 5 is provided in the element formation region. Next, a memory cell is formed by providing a bit line 9 connected to the other of the source / drain regions 12.
第２図（ａ），（ｂ）は本発明の第２の実施例を示す
断面図及びレイアウト図である。FIGS. 2A and 2B are a sectional view and a layout diagram showing a second embodiment of the present invention.
第２図に示すように、溝の内面の深い領域にホウ素イ
オンをドーズ量１×1012〜２×1013cm-2でイオン注入
し、浅い領域にリンイオンをドーズ量１×1014〜１×10
15cm-2でイオン注入して容量部を形成した以外は第１の
実施例と同様の構成を有しており、隣接メモリセル相互
間のパンチスルーを防止し、且つ容量部の電荷蓄積能力
が増加する利点がある。As shown in FIG. 2, boron ions are implanted at a dose of 1 × 10 12 to 2 × 10 13 cm −2 into a deep region on the inner surface of the groove, and phosphorus ions are implanted at a dose of 1 × 10 14 to 1 in a shallow region. × 10
It has the same configuration as that of the first embodiment except that the capacitor portion is formed by ion implantation at 15 cm -2 , prevents punch-through between adjacent memory cells, and has the charge storage capability of the capacitor portion. There is an advantage to increase.
以上説明したように本発明は、１トランジスタと１容
量部から形成されるダイナミックメモリセルの溝容量部
にフィールド酸化膜の端部がひさし状に突出した溝を設
けることにより、容量部の不純物拡散層とチャネルスト
ッパとを隔離して容量部の電荷保持特性を向上させると
いう効果を有する。As described above, according to the present invention, by providing a groove in which an end of a field oxide film protrudes in an eaves shape in a groove capacitance portion of a dynamic memory cell formed by one transistor and one capacitance portion, impurity diffusion of the capacitance portion is provided. This has the effect of isolating the layer and the channel stopper to improve the charge retention characteristics of the capacitor.
第１図（ａ），（ｂ）及び第２図（ａ），（ｂ）は本発
明の第１及び第２の実施例を示す断面図及びレイアウト
図、第３図（ａ），（ｂ）は従来の半導体装置の一例を
示す断面図及びレイアウト図である。 １……Ｐ型シリコン基板、２……フィールド酸化膜、３
……容量電極、４……容量絶縁膜、５……Ｎ型拡散層、
６……チャネルストッパ、７……ゲート電極、８……ワ
ード線、９……ビット線、10……溝容量部、11…Ｐ型拡
散層。FIGS. 1 (a) and (b) and FIGS. 2 (a) and (b) are cross-sectional views and layout diagrams showing first and second embodiments of the present invention, and FIGS. 3 (a) and 3 (b). 2A and 2B are a cross-sectional view and a layout diagram illustrating an example of a conventional semiconductor device. 1 ... P-type silicon substrate, 2 ... Field oxide film, 3
…… Capacitive electrode, 4 …… Capacitive insulating film, 5 …… N-type diffusion layer,
6 channel stopper, 7 gate electrode, 8 word line, 9 bit line, 10 groove capacitance portion, 11 P-type diffusion layer.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/822 H01L 21/8242 H01L 27/108 H01L 27/04 H01L 21/76 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/822 H01L 21/8242 H01L 27/108 H01L 27/04 H01L 21/76
Claims (1)
域を区画するフィールド絶縁膜と、前記フィールド絶縁
膜の下面に設けたチャネルストッパと、前記素子形成領
域に設けて上端に前記フィールド絶縁膜の端部がひさし
状に突出した溝と、前記チャネルストッパと隔離して前
記溝内の側面及び底面に設けた逆導電型の拡散層と、前
記拡散層を含む表面に設けた容量絶縁膜と、前記容量絶
縁膜上に設けて前記溝内を充填する容量電極と、前記拡
散層に接続して素子形成領域に設けた転送ゲート用トラ
ンジスタとを有することを特徴とする半導体装置。A field insulating film provided on a semiconductor substrate of one conductivity type to define an element forming region; a channel stopper provided on a lower surface of the field insulating film; A groove in which the end of the film protrudes in an eaves shape; a diffusion layer of a reverse conductivity type provided on a side surface and a bottom surface in the groove separated from the channel stopper; and a capacitance insulating film provided on a surface including the diffusion layer And a capacitor electrode provided on the capacitor insulating film to fill the trench, and a transfer gate transistor connected to the diffusion layer and provided in an element formation region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2222917A JP2913799B2 (en) | 1990-08-24 | 1990-08-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2222917A JP2913799B2 (en) | 1990-08-24 | 1990-08-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04105360A JPH04105360A (en) | 1992-04-07 |
| JP2913799B2 true JP2913799B2 (en) | 1999-06-28 |
Family
ID=16789888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2222917A Expired - Lifetime JP2913799B2 (en) | 1990-08-24 | 1990-08-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2913799B2 (en) |
-
1990
- 1990-08-24 JP JP2222917A patent/JP2913799B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04105360A (en) | 1992-04-07 |
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