JP2526649B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2526649B2 JP2526649B2 JP63322464A JP32246488A JP2526649B2 JP 2526649 B2 JP2526649 B2 JP 2526649B2 JP 63322464 A JP63322464 A JP 63322464A JP 32246488 A JP32246488 A JP 32246488A JP 2526649 B2 JP2526649 B2 JP 2526649B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- groove
- capacitance
- insulating film
- type region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000003990 capacitor Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 11
- 239000010408 film Substances 0.000 description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 239000010410 layer Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 239000013039 cover film Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000005260 alpha ray Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に溝型キャパシタを有
する１トランジスタ型ダイナミックRAMのメモリセルに
関する。The present invention relates to a semiconductor device, and more particularly to a memory cell of a one-transistor dynamic RAM having a groove type capacitor.
近年、半導体集積回路の高密度化に伴い、ダイナック
RAMのメモリセルのキャパシタ部は、十分大きな蓄積容
量を確保するために、平面構造から３次元構造へと変わ
りつつあり、その代表例が溝型キャパシタを有するメモ
リセルである。従来、この種の半導体装置は、第８図の
ようにＰ型シリコン基板１に、ボロン拡散層のチャンネ
ルストッパ２及びフィールド酸化膜３からなる素子分離
領域が形成され、容量部となる溝をリソグラフィー技術
により形成し、溝の内側面に斜めイオン注入により、ボ
ロンおよびヒ素を導入し、ｐ型領域４および浅いｎ型領
域５を形成し、pn接合による容量部を設ける。溝の内面
を覆い、容量絶縁膜６を形成した後、溝埋込むように多
結晶シリコン７を形成し、ｎ型領域５の対極となる容量
電極とする。容量電極７上に酸化膜12およびトランジス
タ領域にゲート酸化膜14を形成しワード線および、これ
に接続されるゲート電極15をスパッタ後、リソグラフィ
ーでパターニングする。このゲート電極15をマスクにし
て、ヒ素をイオン注入することによりP+型のソース・ド
レイン拡散層16を設け、全面に層間絶縁膜17を形成し、
所定の開口部を形成した後、アルミニウム配線19をパタ
ーン形成し、カバー膜20を全面に形成することなより１
トランジスタ型ダイナミックRAMのメモリセルを得てい
た。In recent years, with the increase in the density of semiconductor integrated circuits,
The capacitor portion of the memory cell of the RAM is changing from a planar structure to a three-dimensional structure in order to secure a sufficiently large storage capacity, and a typical example thereof is a memory cell having a groove type capacitor. Conventionally, in this type of semiconductor device, as shown in FIG. 8, an element isolation region including a channel stopper 2 of a boron diffusion layer and a field oxide film 3 is formed on a P-type silicon substrate 1, and a groove serving as a capacitance portion is formed by lithography. Formed by a technique, boron and arsenic are introduced into the inner surface of the groove by oblique ion implantation to form a p-type region 4 and a shallow n-type region 5, and a capacitor portion by a pn junction is provided. After forming the capacitive insulating film 6 covering the inner surface of the groove, polycrystalline silicon 7 is formed so as to fill the groove to form a capacitive electrode serving as a counter electrode of the n-type region 5. An oxide film 12 is formed on the capacitor electrode 7 and a gate oxide film 14 is formed in the transistor region, and the word line and the gate electrode 15 connected thereto are sputtered and then patterned by lithography. Using this gate electrode 15 as a mask, arsenic is ion-implanted to provide a P + type source / drain diffusion layer 16, and an interlayer insulating film 17 is formed on the entire surface.
After forming the predetermined opening, the aluminum wiring 19 is patterned and the cover film 20 is formed on the entire surface.
I was getting a memory cell of a transistor type dynamic RAM.
このような構成により、ｎ型領域５およびｐ型領域４
によるpn接合容量と、ｎ型領域５および容量絶縁膜６を
介して対向する容量電極７とによる容量が並列に形成さ
れ、比較的大きな容量を実現していた。With such a configuration, the n-type region 5 and the p-type region 4 are
The pn junction capacitance due to and the capacitance due to the capacitance electrode 7 facing each other via the n-type region 5 and the capacitance insulating film 6 are formed in parallel, and a relatively large capacitance is realized.
上述した従来の半導体装置は、溝の内部のみを電荷蓄
積部として用いる構造となっているので、溝内部のみで
電荷蓄積容量を増やそうとしても限界がある。例えば溝
を深く掘り容量を増やそうとすると、溝部の開口部と深
さの比（アスペクト比）が高くなり溝の埋込みが難しく
なる。また、シリコン基板中の接合容量を用いているた
め、α線入射により空乏層内で不要なキャリアが発生し
ソフトエラーが起きるという欠点がある。Since the above-described conventional semiconductor device has a structure in which only the inside of the groove is used as the charge storage portion, there is a limit in increasing the charge storage capacity only inside the groove. For example, if the groove is dug deeper to increase the capacity, the ratio of the opening of the groove to the depth (aspect ratio) becomes high, and it becomes difficult to embed the groove. Further, since the junction capacitance in the silicon substrate is used, there is a drawback that unnecessary carriers are generated in the depletion layer due to the incidence of α rays and a soft error occurs.
本発明の目的は、上記の欠点を除き、容量用溝を深く
形成することなく、大容量を有する溝型キャパシタを提
供するものである。The object of the present invention is to provide a groove type capacitor having a large capacity without deeply forming a capacity groove, except for the above drawbacks.
本発明の半導体装置は、溝型キャパシタの蓄積電極用
溝埋込みポリシリコン上に、蓄積容量用絶縁膜を介し
て、トランジスタのソース側と接続された容量電極を形
成することにより溝埋込み容量電極上に蓄積容量部を設
けることを有している。In the semiconductor device of the present invention, the capacitor electrode connected to the source side of the transistor is formed on the trench-filled polysilicon for trench electrode for storage electrode via the storage capacitor insulating film. The storage capacitor section is provided in the.
そのため、本発明の溝型キャパシタでは、従来の半導
体基板中の接合容量および、溝部に設けられた絶縁膜を
介して設けられた容量に加えて溝を埋込む容量電極上に
絶縁膜を介してソース領域に接続された対向電極を設け
て形成された容量が付加される。Therefore, in the groove-type capacitor of the present invention, in addition to the junction capacitance in the conventional semiconductor substrate and the capacitance provided via the insulating film provided in the groove portion, the capacitance electrode filling the groove is provided with the insulating film interposed therebetween. A capacitance formed by providing a counter electrode connected to the source region is added.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図乃至第５図は、本発明の第１の実施例のメモリ
セルを得るための断面工程図である。1 to 5 are cross-sectional process diagrams for obtaining a memory cell according to the first embodiment of the present invention.
先ず第１図に於てＰ型シリコン基板１にボロン拡散層
のチャンネルストッパ２及び厚さ１μｍのフィールド酸
化膜３からなる素子分離領域を設ける。その後、基板１
の内部に至る溝をフォトリソグラフィーによって形成
し、斜めイオン注入によるボロン導入でｐ型領域４とヒ
素導入で浅いｎ型領域５を形成する。次に厚さ100〜200
Åの容量絶縁膜、たとえば酸化膜６を少なくとも溝内部
全面に形成し、溝を埋込むように多結晶シリコンを形成
し、容量電極７とする。First, in FIG. 1, a P-type silicon substrate 1 is provided with an element isolation region composed of a channel stopper 2 of a boron diffusion layer and a field oxide film 3 having a thickness of 1 μm. Then, the substrate 1
A groove reaching the inside of is formed by photolithography, and boron is introduced by oblique ion implantation to form a p-type region 4 and arsenic is introduced to form a shallow n-type region 5. Next thickness 100-200
A capacitor insulating film Å, for example, an oxide film 6 is formed at least on the entire inner surface of the groove, and polycrystalline silicon is formed so as to fill the groove to form the capacitor electrode 7.
次に第２図に示す様に第２の容量絶縁膜（酸化膜）８
を熱酸化法により全面に100〜120Å形成する。基板１の
表層部のｎ型領域５への接続を確保するために、フォト
レジスト９を塗布パターニングして、コンタクトホール
10を形成する。Next, as shown in FIG. 2, the second capacitance insulating film (oxide film) 8
Is formed on the entire surface by thermal oxidation. In order to secure the connection to the n-type region 5 on the surface layer of the substrate 1, a photoresist 9 is applied and patterned to form a contact hole.
Forming 10.
つづいて、第３図に示す様に、蓄積容量電極11として
多結晶シリコンをCVD成長法により2000〜2500Å形成
し、その容量電極11の抵抗値を下げ、かつ、ソース領域
の形成を同時に行うために不純物を熱拡散により導入す
る。この不純物の一部はコンタクトホール10を通して、
基板１の表層部に拡散される。次に膜厚2000〜2500Åの
酸化膜12をCVD法により形成した後、フォトレジスト13
を塗布、パターニングする。Subsequently, as shown in FIG. 3, polycrystalline silicon is formed as the storage capacitor electrode 11 by the CVD growth method to 2000 to 2500 Å to reduce the resistance value of the capacitor electrode 11 and simultaneously form the source region. Impurities are introduced into by thermal diffusion. Part of this impurity passes through the contact hole 10,
It is diffused in the surface layer portion of the substrate 1. Next, an oxide film 12 having a film thickness of 2000 to 2500Å is formed by the CVD method, and then a photoresist 13
Is applied and patterned.
さらに第４図に示す様に、蓄積容量電極11と酸化膜12
をフォトレジスト13をマスクにしてエッチングし、トラ
ンジスタ部のチャネル上の酸化膜をエッチング除去し、
ゲート酸化膜14,多結晶シリコンによるゲート電極およ
びワード線15,ヒ素導入によるソース・ドレイン拡散層1
6,BPSGなどによる層間絶縁膜17,ドレイン上のコンタク
トホール18を公知の方法で形成する。Further, as shown in FIG. 4, the storage capacitor electrode 11 and the oxide film 12
Is etched using the photoresist 13 as a mask, the oxide film on the channel of the transistor section is removed by etching,
Gate oxide film 14, gate electrode and word line 15 made of polycrystalline silicon, source / drain diffusion layer 1 by arsenic introduction 1
6, an interlayer insulating film 17 made of BPSG or the like and a contact hole 18 on the drain are formed by a known method.
最後に第５図に示す様に、ビット線のアルミニウム配
線19,カバー膜20を公知の方法で形成することにより、
本実施例の１トランジスタ型ダイナミックRAMが完成す
る。Finally, as shown in FIG. 5, by forming the aluminum wiring 19 of the bit line and the cover film 20 by a known method,
The one-transistor type dynamic RAM of this embodiment is completed.
このような構成により、ソース領域16には、ｎ型領域
５およびｐ型領域４からなる接合容量、ｎ型領域５およ
び埋込容量電極７からなる容量部、さらに、蓄積容量電
極11および埋込容量電極７からなる容量部がそれぞれ並
列に接続される。With such a configuration, in the source region 16, the junction capacitance formed of the n-type region 5 and the p-type region 4, the capacitance portion formed of the n-type region 5 and the embedded capacitance electrode 7, the storage capacitance electrode 11 and the embedded capacitance electrode 11 are formed. Capacitance portions including the capacitance electrodes 7 are connected in parallel.
第６図乃至第７図は、本発明の第２の実施例のメモリ
セルを得るための断面工程図である。第１の実施例の第
１図まで、形成した後、第６図に示す様に第２の容量絶
縁膜を膜厚100Åの酸化膜21と膜厚100Åの窒化膜22との
２層構造で形成し、基板１の表層部のｎ型領域５上にフ
ォトリソグラフィーでコンタクトホールを開けた後、多
結晶シリコンにより蓄積容量電極11を形成し、不純物拡
散を行ない、フォトレジスト23を塗布、パターニングす
る。6 to 7 are sectional process diagrams for obtaining a memory cell according to the second embodiment of the present invention. After forming up to FIG. 1 of the first embodiment, as shown in FIG. 6, a second capacitive insulating film is formed with a two-layer structure of an oxide film 21 having a film thickness of 100Å and a nitride film 22 having a film thickness of 100Å. After forming a contact hole by photolithography on the n-type region 5 in the surface layer portion of the substrate 1, a storage capacitor electrode 11 is formed by polycrystalline silicon, impurities are diffused, and a photoresist 23 is applied and patterned. .
次に第７図に示す様に、蓄積容量電極11の不要部分を
エッチングした後、熱酸化法により、酸化膜12を形成す
る。この時の窒化膜22はほとんど酸化されない。さらに
エッチングにより、トランジスタ部の基板１のシリコン
表面を露出させ、ゲート酸化を行ない、以下、第１の実
施例の第４図から第５図まで従えば本実施例の１トラン
ジスタ型ダイナミックRAMが完成する。Next, as shown in FIG. 7, after etching unnecessary portions of the storage capacitor electrode 11, an oxide film 12 is formed by a thermal oxidation method. At this time, the nitride film 22 is hardly oxidized. Further, by etching, the silicon surface of the substrate 1 of the transistor portion is exposed and gate oxidation is performed, and the one-transistor dynamic RAM of this embodiment is completed according to FIGS. 4 to 5 of the first embodiment. To do.
この実施例では、第７図の窒化膜22をマスクにして蓄
積容量電極11上に酸化膜を形成するため、蓄積容量電極
11の側壁にも酸化膜を形成することができ、また蓄積容
量電極11を形成する時、ポリシリコン一層でエッチング
するためエッチング条件を複雑にすることがない。In this embodiment, since the oxide film is formed on the storage capacitor electrode 11 by using the nitride film 22 shown in FIG.
An oxide film can be formed also on the side wall of 11, and when forming the storage capacitor electrode 11, etching is performed with a single layer of polysilicon, so that the etching conditions are not complicated.
以上説明したように本発明は、溝埋込み用容量電極上
に容量絶縁膜を介して蓄積容量電極を設けることによ
り、メモリセル面積を増大させることなく、電荷蓄積容
量を増すことができる。また電荷蓄積容量が増えるた
め、α線によるソフトエラーに強いメモリセルを作るこ
とができる効果がある。As described above, according to the present invention, the charge storage capacitance can be increased without increasing the memory cell area by providing the storage capacitance electrode on the trench filling capacitance electrode via the capacitance insulating film. Further, since the charge storage capacity is increased, there is an effect that a memory cell that is resistant to a soft error due to α ray can be manufactured.
第１図乃至第５図は、本発明の第１の実施例の１トラン
ジスタ型タイナミックRAMを得るための断面工程図、第
６図乃至第７図は、本発明の第２の実施例を得るための
断面工程図、第８図は従来の１トランジスタ型ダイナミ
ックRAMの断面図である。 １……Ｐ型シリコン基板、２……ボロン拡散層（チャン
ネルストッパ）、３……フィールド酸化膜、４……ｐ型
領域、５……ｎ型領域、６……容量絶縁膜、７……容量
電極（多結晶シリコン）、８……第２の容量絶縁膜、9,
13,23……フォトレジスト、10,18……コンタクトホー
ル、11……蓄積容量電極（多結晶シリコン）、12,21…
…酸化膜、14……ゲート酸化膜、15……ワード線、16…
…n+拡散層、17……層間絶縁膜、19……ビット線、20…
…カバー膜、22……窒化膜。1 to 5 are sectional process diagrams for obtaining a one-transistor type dynamic RAM according to the first embodiment of the present invention, and FIGS. 6 to 7 show a second embodiment of the present invention. 8 is a sectional view of a conventional one-transistor dynamic RAM. 1 ... P-type silicon substrate, 2 ... boron diffusion layer (channel stopper), 3 ... field oxide film, 4 ... p-type region, 5 ... n-type region, 6 ... capacitance insulating film, 7 ... Capacitance electrode (polycrystalline silicon), 8 ... Second capacitance insulating film, 9,
13,23 …… Photoresist, 10,18 …… Contact hole, 11 …… Storage capacitor electrode (polycrystalline silicon), 12,21…
… Oxide film, 14 …… Gate oxide film, 15 …… Word line, 16…
… N + diffusion layer, 17… Interlayer insulation film, 19 …… Bit line, 20…
… Cover film, 22 …… Nitride film.
Claims (1)
イッチングトランジスタとを含んで構成される１トラン
ジスタ型ダイナミックRAMを有する半導体装置におい
て、一導電型の半導体基板に設けられた溝と、前記溝の
内面の表面に設けられた逆導電型領域と、前記溝内面の
前記逆導電型領域の表面を覆って設けられた第１の絶縁
膜と、前記溝を全て埋込み少なくとも前記半導体の１主
表面の高さよりも高く設けられた第１の電極と、前記第
１の電極上を覆って設けられた第２の絶縁膜と、前記第
２の絶縁膜を介して前記第１の電極と対向して設けられ
た第２の電極とを有し、前記第１の電極の一端と前記第
２の電極の一端とが同一の前記スイッチトランジスタの
ソース領域に共通に接続されていることを特徴とする半
導体装置。1. A semiconductor device having a one-transistor dynamic RAM in which one memory cell includes one capacitor and one switching transistor, wherein a groove provided in a semiconductor substrate of one conductivity type, A reverse conductivity type region provided on the surface of the inner surface of the groove, a first insulating film provided to cover the surface of the reverse conductivity type region of the inner surface of the groove, and at least one main part of the semiconductor filling the groove. A first electrode provided higher than the height of the surface, a second insulating film provided over the first electrode, and opposed to the first electrode via the second insulating film. A first electrode and a second electrode are commonly connected to the same source region of the switch transistor. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63322464A JP2526649B2 (en) | 1988-12-20 | 1988-12-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63322464A JP2526649B2 (en) | 1988-12-20 | 1988-12-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02165670A JPH02165670A (en) | 1990-06-26 |
| JP2526649B2 true JP2526649B2 (en) | 1996-08-21 |
Family
ID=18143943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63322464A Expired - Lifetime JP2526649B2 (en) | 1988-12-20 | 1988-12-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2526649B2 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61239661A (en) * | 1985-04-16 | 1986-10-24 | Nec Corp | Semiconductor memory device |
| JPS62190868A (en) * | 1986-02-18 | 1987-08-21 | Matsushita Electronics Corp | Semiconductor memory |
| JPS6321865A (en) * | 1986-07-16 | 1988-01-29 | Nec Corp | Semiconductor device for transistor type dynamic memory cell |
| JPS63119252A (en) * | 1986-11-06 | 1988-05-23 | Matsushita Electric Ind Co Ltd | Semiconductor memory device |
| JPS63146461A (en) * | 1986-12-10 | 1988-06-18 | Mitsubishi Electric Corp | Semiconductor memory device |
-
1988
- 1988-12-20 JP JP63322464A patent/JP2526649B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02165670A (en) | 1990-06-26 |
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