JP2913853B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to gallium arsenide and the like.
The present invention relates to a field effect transistor (FET) such as a Schottky junction field effect transistor (MESFET) on a Group 5 compound semiconductor substrate.

[0002]

2. Description of the Related Art In a high-speed integrated circuit using a Group 3-5 compound semiconductor such as gallium arsenide (GaAs), a transistor is directly formed on a semi-insulating substrate.

[0003]

However, in a semi-insulating substrate of these compound semiconductors, when an external electric field is applied, electric charges enter and exit at a deep level in the semi-insulating substrate to generate space charges. I do. This space charge has a significant effect on the characteristics of the device fabricated on the substrate.

[0004] F including GaAs-MESFET
It has long been known that an integrated circuit using an ET device has a characteristic interference effect between elements called a side gate effect. The semi-insulating substrate 9 as shown in FIG.
Focusing on the n-channel FET 5 on the upper side, a typical phenomenon is that when a negative potential is applied to the adjacent n-region (side gate electrode 6), the drain current of the FET 5 decreases. It is. The source of this side gate effect is due to the space charge at the interface with the substrate 9.

It is an object of the present invention to provide an FET having a structure capable of suppressing a side gate effect generated when an FET is formed on a semi-insulating substrate.

[0006]

SUMMARY OF THE INVENTION The present invention relates to a semi-insulating substrate .
N-type conductive layer (p-type conductive layer) formed on the surface and n-type conductive layer
A gate metal traversing the surface of the layer (p-type conductive layer).
In an n-channel (p-channel) field-effect transistor, a portion extending from an n-type conductive layer (p-type conductive layer)
The semiconductor layer is characterized in that a semiconductor layer is deposited on the surface of the semi-insulating region that is in contact with the gate metal of the semiconductor device such that valence band (conduction band) energy acts as a barrier against hole (electron) injection.

[0007]

Specifically, consider a situation when an n-channel FET is directly formed on a semi-insulating substrate. Normally, if an n-type channel and a semi-insulating substrate are joined (n
−i junction) and an energy band diagram as shown in FIG. 11 similar to the np junction. The n-channel Fermi level is
Just below the bottom of the conduction band, the Fermi level of the semi-insulating substrate is near the center of the forbidden band. On the semi-insulating substrate side, negative space charges are accumulated with a width of W, and on the n-channel side, electrons are depleted with a width of d to cancel them, and accumulated as positive space charges.

If a negative potential is applied to the semi-insulating substrate, the ni-junction has a space-charged portion spread further on both sides of the junction, just like a reverse bias of a pn junction. It will be. From the n-channel side,
The channel is further depleted of the n-layer by the ni interface,
It will be narrowed. If this n-channel is used as the operation channel of the FET, it means that the channel is narrowed and the drain current of the FET is reduced, and a situation in which the side gate effect occurs is explained.

However, in an FET integrated circuit, adjacent elements (side gates) actually exist at a distance of several μm or more. Therefore, the voltage applied to the side gate affects the ni junction of the FET of interest,
A special mechanism is required to cause the side gate effect.

In the case of the n-channel MESFET, one of the mechanisms is injection of holes from the Schottky junction metal used as the gate electrode. Injection of holes causes double injection of carriers into the semi-insulating substrate together with electron injection from the side gate, and as a result, accumulation of negative charges near the n-i interface occurs, and the n-i junction , The side gate voltage reaches directly. Conventionally, in a MESFET fabricated on a semi-insulating substrate, the side gate effect has been caused by the hole injection.

FIG. 9 and FIG. 10 show energy bands when a Schottky junction metal and a semi-insulating substrate or n-substrate come into contact with each other in the case of GaAs. These figures are written as potential energy for electrons. In the case of GaAs, the energy position of the Schottky junction is almost determined by the surface state density of GaAs, which is about 0.9 eV from the conduction band, which is slightly closer to the valence band. Therefore, when the deep level comes into contact with the semi-insulating substrate near the center of the forbidden band, the potential energy slightly rises near the Schottky junction metal as shown in FIG. On the other hand, when it comes into contact with the n-type substrate, as shown in FIG. Therefore, GaAs is formed from the Schottky junction metal side.
From the viewpoint of injection of holes into s, the contact with the semi-insulating substrate has a lower barrier against holes than in the case of contact with the n-type substrate, and the holes are easily injected. In addition, the above description is the same in the case of a p-channel MESFET if the role of electron holes is exchanged.

Generally, a compound semiconductor MESFET has a gate shape as shown in FIGS. 7 is a plan view, and FIG. 8 is a cross-sectional view taken along the line AA of FIG. 7. In these figures, 1 is a source electrode, 2 is a drain electrode, 3 is a gate electrode, 4 is an n-type conductive layer, and 9 is half. 4 shows an insulating substrate.
In this shape, in order to cut off the FET with the gate voltage, it is necessary to protrude the Schottky junction metal (gate electrode 3) up to the semi-insulating region as shown by hatching in FIG. is there. Therefore, hole injection from the protruding region directly contributed to the generation of the side gate effect.

However, as shown in FIGS. 1 and 2, the surface of the semi-insulating region in contact with the Schottky junction type metal (gate electrode 3) has a valence band higher than that of the substrate so as to be a barrier against hole injection. When the underlying semiconductor layer is deposited,
When the Schottky metal side is biased to a positive potential, FIG.
The potential is as follows. In the case where there is no semiconductor layer serving as a barrier against holes, when the Schottky metal side is biased to the same voltage, the potential becomes as shown in FIG. Comparing the two, it is expected that hole injection is more suppressed in the case of FIG. In fact, the injection of holes over the potential barrier is approximately proportional to exp (-q △ V / kT), as in the case of thermionic emission. here,
ΔV is the height of the potential barrier, q is the elementary charge, k is the Boltzmann constant, and T is the temperature. At room temperature, (kT /
Since q) × (ln10) = 60 mV, the hole injection amount is reduced to 1/10 even if the potential barrier is increased only by 60 mV. Due to this effect, the injection of holes is greatly reduced, and the occurrence of the side gate effect is largely suppressed. The semiconductor layer deposited here may have a conduction band above or below that of the substrate as shown in FIG.

Also in the case of a p-channel FET, the side gate effect can be suppressed by the same operation as in the above discussion in which the roles of holes and electrons are exchanged. That is, a semiconductor layer whose conduction band energy is higher than that of the substrate may be deposited so as to be a barrier against electron injection, and the energy of the valence band of the semiconductor layer is higher than that of the substrate. It can be above or below.

[0015]

1 and 2 show a GaAs n-channel Schottky junction field effect transistor which is an embodiment of the structure of the present invention. FIG. 5 shows a change in drain current of the FET due to the side gate voltage. The n-type conductive layer 4 is formed by ion implantation of silicon, and the metal forming the gate electrode 3 is tungsten. An undoped AlGaAs layer is used for the semiconductor layer 12 serving as a barrier to holes. For comparison, FIG. 6 shows a change in the drain current of the conventional FET shown in FIGS. 7 and 8. As shown in FIG. 6, in the case of the conventional FET, when the side gate voltage becomes lower than a certain voltage (-3 V in this case), the drain current starts to decrease. In the case of, even if the side gate voltage is further reduced, the drain current does not decrease. The barrier semiconductor layer 12 used here may be of any type as long as the valence band comes to a lower energy side than the substrate 9, and the energy of the conduction band does not matter.

The p-channel Schottky junction field effect transistor also has an undoped A layer as a semiconductor layer for suppressing electron injection from the gate metal.
An lGaAs layer can be used. The effect of the invention was recognized as in the case of the above-mentioned n-channel field effect transistor.

The field effect transistor of the present invention is MESF
In addition to ET, any field effect transistor using a semi-insulating substrate can be applied. The semiconductor material of the substrate may be a group 3-5 compound semiconductor other than GaAs, for example, InP.

[0018]

As described above, the structure of the field-effect transistor according to the present invention is such that the semiconductor serving as a barrier against hole (electron) injection is provided on the surface of the semi-insulating region of the semi-insulating substrate surface in contact with the gate metal. Since the layer is deposited, it is very effective in suppressing the side gate effect.

[Brief description of the drawings]

FIG. 1 is a plan view for explaining an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining one embodiment of the present invention, and is a cross-sectional view taken along line AA of FIG.

FIG. 3 is an energy band diagram for explaining a MESFET according to one embodiment of the present invention.

FIG. 4 is an energy band diagram for explaining a conventional MESFET.

FIG. 5 is a characteristic diagram showing voltage-current characteristics for explaining a MESFET according to one embodiment of the present invention.

FIG. 6 is a characteristic diagram showing voltage-current characteristics for explaining a conventional MESFET.

FIG. 7 is a plan view for explaining a conventional MESFET.

8 is a cross-sectional view for explaining a conventional MESFET, and is a cross-sectional view taken along line AA of FIG.

FIG. 9 is an energy band diagram for explaining a conventional MESFET.

FIG. 10 is an energy band diagram for explaining a conventional MESFET.

FIG. 11 is an energy band diagram for explaining a conventional MESFET.

FIG. 12 is a schematic cross-sectional view for explaining the operation of a conventional MESFET.

[Explanation of symbols]

 Reference Signs List 1 source electrode 2 drain electrode 3 gate electrode 4 n-type conductive layer 5 n-channel FET 6 side gate electrode 9 semi-insulating substrate 10 source region 11 drain region 12 semiconductor layer serving as hole injection barrier

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 27/098 H01L 29/775-29/778 H01L 29 / 80-29/812

Claims (2)

(57) [Claims] 1. An n-type conductive layer formed on a surface of a semi-insulating substrate.
A conductive layer and a gate metal traversing the surface of the n-type conductive layer.
Including the n-channel field effect transistor made by the surface of the semi-insulating substrate to contact <br/> to the gate metal portion extending from the n-type conductive layer, the valence band of the semi-insulating substrate A field-effect transistor having a semiconductor layer with lower energy than the valence band. 2. A p-type conductor formed on a surface of a semi-insulating substrate.
A conductive layer and a gate metal traversing the surface of the n-type conductive layer.
Including in the p-channel field effect transistor made by the surface of the semi-insulating substrate to contact <br/> to the gate metal portion extending from the p-type conductive layer, the conduction conduction band of the semi-insulating substrate A field-effect transistor comprising a semiconductor layer having higher energy than the band.