JP2914023B2 - Method of forming fine wiring - Google Patents
Method of forming fine wiringInfo
- Publication number
- JP2914023B2 JP2914023B2 JP20073292A JP20073292A JP2914023B2 JP 2914023 B2 JP2914023 B2 JP 2914023B2 JP 20073292 A JP20073292 A JP 20073292A JP 20073292 A JP20073292 A JP 20073292A JP 2914023 B2 JP2914023 B2 JP 2914023B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- opening
- insulating film
- cavity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims description 26
- 239000007789 gas Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 6
- 150000002736 metal compounds Chemical class 0.000 claims description 6
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims 1
- 229910052750 molybdenum Inorganic materials 0.000 claims 1
- 229910052715 tantalum Inorganic materials 0.000 claims 1
- 229910052719 titanium Inorganic materials 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 239000000460 chlorine Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 229910017767 Cu—Al Inorganic materials 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- -1 Cu and W Chemical class 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 150000001336 alkenes Chemical class 0.000 description 1
- 150000001345 alkine derivatives Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- TUTOKIOKAWTABR-UHFFFAOYSA-N dimethylalumane Chemical compound C[AlH]C TUTOKIOKAWTABR-UHFFFAOYSA-N 0.000 description 1
- GCSJLQSCSDMKTP-UHFFFAOYSA-N ethenyl(trimethyl)silane Chemical compound C[Si](C)(C)C=C GCSJLQSCSDMKTP-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置における微細
配線の形成方法に関する。The present invention relates to a method for forming fine wiring in a semiconductor device.
【０００２】[0002]
【従来の技術】従来のＬＳＩにおける微細配線の形成方
法は、半導体基板上に配線材料となる金属膜をスパッタ
法により均一に堆積し、ドライエッチング技術により選
択的にエッチングして配線を形成するか、または、半導
体基板上にＣＶＤ法により金属膜を均一に堆積し、ドラ
イエッチング技術により選択的にエッチングして配線を
形成する方法が広く採用されている。2. Description of the Related Art A conventional method for forming a fine wiring in an LSI is to form a wiring by uniformly depositing a metal film as a wiring material on a semiconductor substrate by a sputtering method and selectively etching by a dry etching technique. Alternatively, a method of forming a wiring by uniformly depositing a metal film on a semiconductor substrate by a CVD method and selectively etching the metal film by a dry etching technique has been widely adopted.
【０００３】[0003]
【発明が解決しようとする課題】この従来の微細配線の
形成方法は、スパッタ法を用いるものでは生産性、表面
モフォロジー（Ｍｏｒｐｈｏｌｏｇｙ）等の膜質に優れ
た金属膜を得ることができるが、段差被覆性や埋め込み
についてはＣＶＤ法に劣り、一方、ＣＶＤ法を用いるも
のでは段差被覆性や埋め込みについては優れているが表
面モフォロジー等の膜質でスパッタ法に劣るという問題
があった。According to this conventional method for forming fine wiring, a metal film having excellent film quality such as productivity and surface morphology can be obtained by using a sputtering method. The properties and embedding are inferior to the CVD method, while those using the CVD method are excellent in step coverage and embedding, but are inferior to the sputtering method due to film quality such as surface morphology.
【０００４】また、金属膜をパターニングするためのド
ライエッチングは異方性に優れ現在ＬＳＩ配線の加工法
としては最も優れているが、信頼性という観点からＡｌ
に代わる配線材料として期待されているＣｕやＷ等の金
属に対してはＡｌと異なりドライエッチングは困難であ
り、配線を形成するのは困難である。Also, dry etching for patterning a metal film has excellent anisotropy and is currently the most excellent method for processing an LSI wiring.
Unlike Al, metals such as Cu and W, which are expected as an alternative wiring material, are difficult to dry-etch, unlike Al, and are difficult to form wiring.
【０００５】本発明の目的は、エッチング加工の困難な
金属を使用した場合にも埋め込みや段差被覆性に優れ、
かつ表面モフォロジーの良好な配線を実現できる配線形
成方法を提供することにある。[0005] An object of the present invention is to provide excellent embedding and step coverage even when a metal that is difficult to etch is used,
Another object of the present invention is to provide a wiring forming method capable of realizing a wiring having good surface morphology.
【０００６】[0006]
【課題を解決するための手段】本発明の微細配線の形成
方法は、半導体基板上に設けた絶縁膜を選択的にエッチ
ングして第１の開口部を形成する工程と、前記第１の開
口部を含む表面に前記絶縁膜に比べてエッチングレート
の大きい材料膜を堆積してパターニングし配線形成用パ
ターンを有するスペーサを形成する工程と、前記スペー
サを含む表面に層間絶縁膜を堆積する工程と、前記層間
絶縁膜を選択的にエッチングして第２の開口部を形成し
前記スペーサの表面を露出させる工程と、前記スペーサ
をエッチング除去して前記絶縁膜と前記層間絶縁膜との
間に空洞を形成する工程と、前記空洞内に揮発性金属化
合物ガスを導入して前記第１の開口部の前記半導体基板
の表面から順次金属膜を選択成長させて前記空洞内を充
填する工程とを含んで構成される。According to the present invention, there is provided a method for forming a fine wiring, comprising the steps of selectively etching an insulating film provided on a semiconductor substrate to form a first opening; Depositing and patterning a material film having a higher etching rate than the insulating film on the surface including the portion to form a spacer having a wiring forming pattern; and depositing an interlayer insulating film on the surface including the spacer. Selectively etching the interlayer insulating film to form a second opening to expose the surface of the spacer; and removing the spacer by etching to form a cavity between the insulating film and the interlayer insulating film. And a step of introducing a volatile metal compound gas into the cavity to selectively grow a metal film sequentially from the surface of the semiconductor substrate in the first opening to fill the cavity. In constructed.
【０００７】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【０００８】図１（ａ）〜（ｅ）は本発明の一実施例を
説明するための工程順に示した半導体チップの断面図で
ある。FIGS. 1A to 1E are sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.
【０００９】まず、図１（ａ）に示すように、Ｓｉ基板
１の表面を熱酸化して酸化シリコン膜２を０．１〜２μ
ｍの厚さに形成し、ドライエッチング技術を用いて選択
的に第１の開口部３を形成してＳｉ基板１の表面を露出
させる。First, as shown in FIG. 1A, the surface of a Si substrate 1 is thermally oxidized to form a silicon oxide film 2 of 0.1 to 2 μm.
m, and the first opening 3 is selectively formed using a dry etching technique to expose the surface of the Si substrate 1.
【００１０】次に、図１（ｂ）に示すように、第１の開
口部３を含む表面にＬＰＣＶＤ（減圧ＣＶＤ）法で多結
晶シリコン膜４を０．０５〜１μｍの厚さに堆積し、ド
ライエッチング技術を用いてパターニングし配線形成用
パターンを有するスペーサを形成する。Next, as shown in FIG. 1B, a polycrystalline silicon film 4 is deposited to a thickness of 0.05 to 1 μm on the surface including the first opening 3 by LPCVD (low pressure CVD). Then, patterning is performed using a dry etching technique to form a spacer having a wiring forming pattern.
【００１１】次に、図１（ｃ）に示すように、ＬＰＣＶ
Ｄ法で多結晶シリコン膜４を含む表面に酸化シリコン膜
５を０．１〜２μｍの厚さに堆積し、酸化シリコン膜５
を選択的にドライエッチングし、第１の開口部３より離
れた位置に第２の開口部６を形成して多結晶シリコン膜
４の表面を露出させる。Next, as shown in FIG.
A silicon oxide film 5 is deposited to a thickness of 0.1 to 2 μm on the surface including the polycrystalline silicon film 4 by the method D.
Is selectively dry-etched, a second opening 6 is formed at a position distant from the first opening 3, and the surface of the polycrystalline silicon film 4 is exposed.
【００１２】次に、図１（ｄ）に示すように、基板温度
６００〜１０００℃でＨＣ１ガスを導入し、第２の開口
部６から多結晶シリコン膜４をエッチングして空洞７を
形成する。ＨＣ１に対する酸化シリコン膜２，５及び単
結晶Ｓｉ（Ｓｉ基板１）のエッチングレートは多結晶シ
リコン膜４のエッチングレートに比べ小さいのであまり
エッチされない。Next, as shown in FIG. 1D, a HC1 gas is introduced at a substrate temperature of 600 to 1000 ° C., and the polycrystalline silicon film 4 is etched from the second opening 6 to form a cavity 7. . Since the etching rates of the silicon oxide films 2 and 5 and the single crystal Si (Si substrate 1) with respect to HC1 are smaller than the etching rate of the polycrystalline silicon film 4, they are not etched much.
【００１３】次に、図１（ｅ）に示すように、ＣＶＤ法
により基板温度５０〜２５０℃で第２の開口部６よりビ
ス・ヘキサフルオロアセチルアセトネート・カッパ（以
下Ｃｕ（ｈｆａ）2 と記す）ガスを供給しＣｕ膜８を空
洞７内に成長させる。ここで、Ｃｕ（ｈｆａ）2 を用い
たＣｕ膜８の成長は選択性があり、酸化シリコン膜上に
は成長しないため、Ｃｕ膜８は第１の開口部３のＳｉ基
板１の表面から順次成長して空洞７内を充填していく。Next, as shown in FIG. 1E, bis hexafluoroacetylacetonate kappa (hereinafter referred to as Cu (hfa) 2 ) is formed through the second opening 6 at a substrate temperature of 50 to 250 ° C. by the CVD method. A gas is supplied to grow the Cu film 8 in the cavity 7. Here, the growth of the Cu film 8 using Cu (hfa) 2 is selective and does not grow on the silicon oxide film. It grows and fills the cavity 7.
【００１４】なお、基板温度２００〜８００℃で第２の
開口部６から、Ｃｕ（ｈｆａ）2 ガスとジメチルアルミ
ニウムハイドライド（以下ＤＭＡＨと記す）ガスを同時
に供給してＣｕ−Ａｌ合金膜を空洞７内に選択成長させ
ても良い。ここで、Ｃｕ（ｈｆａ）2 ガス及びＤＭＡＨ
ガスを用いたＣｕ−Ａｌ合金膜の成長は選択性があり、
酸化シリコン膜上には成長せず、開口部３のＳｉ基板１
の表面から順次Ｃｕ−Ａｌ合金膜が選択成長して空洞７
内を充填していく。At a substrate temperature of 200 to 800 ° C., Cu (hfa) 2 gas and dimethyl aluminum hydride (hereinafter referred to as DMAH) gas are simultaneously supplied from the second opening 6 to form a Cu—Al alloy film in the cavity 7. It may be selectively grown inside. Here, Cu (hfa) 2 gas and DMAH
The growth of Cu-Al alloy film using gas is selective,
The Si substrate 1 in the opening 3 does not grow on the silicon oxide film.
The Cu—Al alloy film is selectively grown sequentially from the surface of
Fill inside.
【００１５】図２は本発明の第２の実施例を説明するた
めの半導体チップの断面図である。FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.
【００１６】図２に示すように、第１の実施例と同様の
工程により、酸化シリコン膜２，５の間に空洞７を形成
する。次に、ＣＶＤ法により基板温度２００〜８００℃
で第２の開口部６から、ＴｉＣｌ4 ＋ＮＨ3 ガスを供給
し第１の開口部に３のＳｉ基板１の表面にＴｉＮ膜９を
５〜２０ｎｍの厚さに成長させる。ここで、ＴｉＣｌ4
＋ＮＨ3 を用いたＴｉＮ膜９の成長は選択性があり、酸
化シリコン膜上には成長せず第１の開口部３のＳｉ基板
１の表面のみに成長する。次に、基板温度１５０〜４０
０℃で第２の開口部６よりＣｕ（ｈｆａ）2 ガスを供給
しＣｕ膜８を空洞７内に成長させる。ここでＣｕ（ｈｆ
ａ）2 ガスを用いたＣｕ膜８の成長は選択性があり酸化
シリコン膜上には成長しないため、Ｃｕ膜８はＴｉＮ膜
９の表面から成長していく。ＴｉＮ膜９はＣｕ膜８のＳ
ｉ基板１中への拡散を抑制するのでより高温での成長が
可能となる。As shown in FIG. 2, a cavity 7 is formed between the silicon oxide films 2 and 5 by the same steps as in the first embodiment. Next, the substrate temperature is 200 to 800 ° C. by the CVD method.
Then, a TiCl 4 + NH 3 gas is supplied from the second opening 6 and a TiN film 9 is grown to a thickness of 5 to 20 nm on the surface of the third Si substrate 1 in the first opening. Here, TiCl 4
The growth of the TiN film 9 using + NH 3 is selective and grows only on the surface of the Si substrate 1 in the first opening 3 without growing on the silicon oxide film. Next, a substrate temperature of 150 to 40
A Cu (hfa) 2 gas is supplied from the second opening 6 at 0 ° C. to grow a Cu film 8 in the cavity 7. Here, Cu (hf
a) Since the growth of the Cu film 8 using the two gases is selective and does not grow on the silicon oxide film, the Cu film 8 grows from the surface of the TiN film 9. The TiN film 9 is made of S
Since diffusion into the i-substrate 1 is suppressed, growth at a higher temperature becomes possible.
【００１７】なおＳｉ基板１の代りにＧａＡｓ基板やＩ
ｎＰ基板を用いても良い。In place of the Si substrate 1, a GaAs substrate or I
An nP substrate may be used.
【００１８】また、酸化シリコン膜２，５の形成方法は
熱酸化、ＣＶＤ法、スパッタ法のいずれかを用いて形成
しても良く、絶縁膜として酸化シリコン膜以外に窒化シ
リコン膜やＰＳＧ膜又はＢＰＳＧ膜を用いても良い。The silicon oxide films 2 and 5 may be formed by any of thermal oxidation, CVD, and sputtering. In addition to the silicon oxide film, the insulating film may be a silicon nitride film, a PSG film, or the like. A BPSG film may be used.
【００１９】また、多結晶シリコン膜４のエッチングガ
スとしてはＨＣ１に限らずＣｌ2 等の塩素系ガス、フッ
素系ガスを用いても良い。The etching gas for the polycrystalline silicon film 4 is not limited to HC1, but may be a chlorine-based gas such as Cl 2 or a fluorine-based gas.
【００２０】スペーサとしては多結晶シリコン膜に限ら
ず非晶質Ｓｉ膜やＡｌ膜を用いても同様の結果を得る事
ができる。非晶質Ｓｉ膜やＡｌ膜の場合のエッチャント
も塩素系ガス、フッ素系ガスを用いることが可能であ
る。Similar results can be obtained by using not only a polycrystalline silicon film but also an amorphous Si film or an Al film as a spacer. As an etchant for an amorphous Si film or an Al film, a chlorine-based gas or a fluorine-based gas can be used.
【００２１】Ｃｕ膜の形成にはＣｕ（ｈｆａ）2 以外に
ヘキサフルオロアセチルアセトネート・トリメチルビニ
ルシラン・カッパ，ベータ・ダイケトネート・Ｌ・カッ
パ，ベータ・ケトイミネート・Ｌ・カッパ，ベータ・ダ
イケトネート・ジ・Ｌ・カッパ，ベータ・ダイケトネー
ト・ジ・Ｌ・カッパ，ベータ・ケトイミネート・ジ・Ｌ
・カッパ（但し、Ｌはホスフィン，アルケン，アルキン
のいずれか）を用いても良い。For the formation of the Cu film, in addition to Cu (hfa) 2 , hexafluoroacetylacetonate / trimethylvinylsilane / kappa, beta / diketonate / L / kappa, beta / ketoiminate / L / kappa, beta / diketonate / di / L・ Kappa, Beta-Diketonate-Di-L-Kappa, Beta-Ketominate-Di-L
-Kappa (where L is any one of phosphine, alkene and alkyne) may be used.
【００２２】なお、基板温度１００〜５００℃でのＷＦ
6 ＋Ｈ2 ，ＷＦ6 ＋ＳｉＨ4 ，ＷＦ6 ＋ＳｉＨ2 Ｆ2 の
供給，基板温度１００〜５００℃でのＭｏＦ5 ＋Ｈ2 に
おいても同様に空洞７内への配線形成が可能であり、そ
れぞれＷ膜，Ｍｏ膜が形成される。WF at a substrate temperature of 100 to 500 ° C.
6 + H 2 , WF 6 + SiH 4 , WF 6 + SiH 2 F 2 , and MoF 5 + H 2 at a substrate temperature of 100 to 500 ° C. can similarly form wiring in the cavity 7. An Mo film is formed.
【００２３】[0023]
【発明の効果】以上説明したように本発明は、微細加工
の困難な金属を用いて埋め込み、段差被覆性に優れ、か
つ表面モフォロジーの良好な配線を実現できるという効
果を有する。As described above, the present invention has an effect of embedding by using a metal which is difficult to be finely processed, and realizing a wiring excellent in step coverage and excellent in surface morphology.
【図１】本発明の第１の実施例を説明するための工程順
に示した半導体チップの断面図である。FIG. 1 is a sectional view of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.
【図２】本発明の第２の実施例を説明するための半導体
チップの断面図である。FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a second embodiment of the present invention.
１ Ｓｉ基板 ２，５ 酸化シリコン膜 ３，６ 開口部 ４ 多結晶シリコン膜 ７ 空洞 ８ Ｃｕ膜 ９ ＴｉＮ膜 Reference Signs List 1 Si substrate 2, 5 Silicon oxide film 3, 6 Opening 4 Polycrystalline silicon film 7 Cavity 8 Cu film 9 TiN film
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/3205 H01L 21/3213 H01L 21/768 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/3205 H01L 21/3213 H01L 21/768
Claims (7)
エッチングして第１の開口部を形成する工程と、前記第
１の開口部を含む表面に前記絶縁膜に比べてエッチング
レートの大きい材料膜を堆積してパターニングし配線形
成用パターンを有するスペーサを形成する工程と、前記
スペーサを含む表面に層間絶縁膜を堆積する工程と、前
記層間絶縁膜を選択的にエッチングして第２の開口部を
形成し前記スペーサの表面を露出させる工程と、前記ス
ペーサをエッチング除去して前記絶縁膜と前記層間絶縁
膜との間に空洞を形成する工程と、前記空洞内に揮発性
金属化合物ガスを導入して前記第１の開口部の前記半導
体基板の表面から順次金属膜を選択成長させて前記空洞
内を充填する工程とを含むことを特徴とする微細配線の
形成方法。A step of selectively etching an insulating film provided on a semiconductor substrate to form a first opening; and a step of forming an etching rate on a surface including the first opening as compared with the insulating film. Depositing and patterning a large material film to form a spacer having a wiring forming pattern, depositing an interlayer insulating film on a surface including the spacer, and selectively etching the interlayer insulating film to form a second insulating film. Forming an opening to expose the surface of the spacer; forming a cavity between the insulating film and the interlayer insulating film by etching away the spacer; and forming a volatile metal compound in the cavity. Introducing a gas to selectively grow a metal film sequentially from the surface of the semiconductor substrate in the first opening to fill the cavity.
を同時に空洞内に導入して第１の開口部の半導体基板の
表面から順次合金膜を選択成長させる請求項１記載の微
細配線の形成方法。2. The formation of fine wiring according to claim 1, wherein at least two kinds of volatile metal compound gases are simultaneously introduced into the cavity to selectively grow the alloy film sequentially from the surface of the semiconductor substrate in the first opening. Method.
を順次空洞内に導入して第１の開口部の半導体基板の表
面から金属化合物膜及び金属膜を順次選択成長させて積
層する請求項１記載の微細配線の形成方法。3. The method according to claim 1, wherein at least two kinds of volatile metal compound gases are sequentially introduced into the cavity, and the metal compound film and the metal film are sequentially grown selectively from the surface of the semiconductor substrate in the first opening and stacked. 2. The method for forming a fine wiring according to 1.
膜，ＰＳＧ膜，ＢＰＳＧ膜のいずれかである請求項１記
載の微細配線の形成方法。4. The method according to claim 1, wherein the insulating film is any one of a silicon oxide film, a silicon nitride film, a PSG film, and a BPSG film.
ｉ膜，Ａｌ膜のいずれかである請求項１記載の微細配線
の形成方法。5. A spacer comprising a polycrystalline silicon film and an amorphous S
2. The method for forming a fine wiring according to claim 1, wherein the method is one of an i film and an Al film.
る請求項１記載の微細配線の形成方法。6. The method according to claim 1, wherein the metal film is one of Cu, W, and Mo.
のいずれかを含む化合物膜である請求項３記載の微細配
線の形成方法。7. The method according to claim 1, wherein the metal compound film is at least Ti, W, Ta.
4. The method for forming a fine wiring according to claim 3, wherein the method is a compound film containing any one of the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20073292A JP2914023B2 (en) | 1992-07-28 | 1992-07-28 | Method of forming fine wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20073292A JP2914023B2 (en) | 1992-07-28 | 1992-07-28 | Method of forming fine wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0653215A JPH0653215A (en) | 1994-02-25 |
| JP2914023B2 true JP2914023B2 (en) | 1999-06-28 |
Family
ID=16429262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20073292A Expired - Lifetime JP2914023B2 (en) | 1992-07-28 | 1992-07-28 | Method of forming fine wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2914023B2 (en) |
-
1992
- 1992-07-28 JP JP20073292A patent/JP2914023B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0653215A (en) | 1994-02-25 |
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