JP2914966B2 - Image processing method and apparatus - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to an image for synthesizing image data stored in a memory.
The present invention relates to an image processing method and apparatus. [Background of the Invention] Image data is stored in a memory as a set of bit data.
Remembered. Therefore, one image stored in the memory
When combining image data with other image data
Is to convert one image data and the other
It is necessary to perform reading and combining processing in bit units. On the other hand, a processing device such as a microprocessor for performing the synthesizing process.
Is the unit of access to the memory and the unit of arithmetic processing
Is a byte unit or a word unit. This kind of processing
To realize the processing of the image data by the
Generates a bit address for each bit of the image data.
Processing, such as a microprocessor, and images
Bits of image data between the memory that stores the data
A complicated circuit for generating an address is required. This kind of
References to the technology include U.S. Patent No. 4,435,792.
There is information. Also, the memory that stores the images is divided into words,
Some are accessible in word units.
Combine images by moving image data over the memory
The fact is that is not taken into account. This kind of
Japanese Unexamined Patent Publication No. Sho 59-119385 discloses a technique for reference.
is there. In addition, data is read out in word units, and
There are technologies that try to separate important data. This species
Japanese Patent Application Laid-Open No. 53-83537 discloses
There is. Furthermore, it is related to a device that performs this type of processing.
Is a Micro Processor from ADVANCED MICRO DEVICES
Am 29116 and the like. [Object of the invention] The present invention has been made in view of the above points,
The purpose is to store the image data in the memory.
It is possible to access in word units
An image processing method that can combine image data with other image data
Method and apparatus. [Summary of the Invention] In order to achieve the above object, the present invention
Is composed of a large number of bits, and has a predetermined number of bits.
The memory divided into words consisting of
From the first image data consisting of a set and the set of multiple bits
From the arbitrary bit position
And the first image data and the second image data are
Logic synthesis and store the synthesized image data in the memory.
The first image data from the memory
And synthesizing the first image data from the memory.
2 and the image data including the image data
The read word is read in units of
Image data is stored in registers in units of multiple words,
Word containing the second image data stored in the register
The second image data in the
Based on the first image data in the word containing the image data
The bit position matching process is performed in the corresponding manner, and the read first
The first image data in the word containing the image data
By performing physical synthesis, the first image data is stored.
From the given arbitrary bit position, the second
Logic synthesis of image data
The image data is the memo read from the first image data.
Are sequentially stored at the word position of the memory in units of the word.
An image processing method is characterized in that: Also, the feature of the present invention is that a large number of bits are
Are divided into word units consisting of a predetermined number of bits.
A first image data consisting of a set of a plurality of bits;
The second image data consisting of a set of several bits is
A memory for storing the image data from the position of the first image data;
And the second image data as a unit of the divided word.
And input image data in multiple words
Is stored in a register in units of
The second image in the word containing the extracted second image data
Converting the data to a word containing the input first image data;
Bit position matching processing based on the first image data in
In the word including the input first image data,
By logically synthesizing the first image data of
An arbitrary bit position where the first image data is stored
Logically synthesizes the second image data having an arbitrary bit width.
A data processing unit, and the first image data from the memory.
Data from the memory to the first image and data.
And the second image data to be
The word is read out sequentially in units of
Data processing unit to perform logic synthesis processing from the data processing unit.
Read the first image data from the processed composite image data.
At the word position in the memory
An image processor comprising a memory access unit for sequentially storing
In the control unit. According to a preferred embodiment of the present invention, the first image data
Is the image data to be synthesized, and the second image data is the image data to be synthesized.
Image data. Also, according to a preferred embodiment of the present invention, the first image
The data and the second image data are pixel data. Further, according to a preferred embodiment of the present invention, the word unit
The number of bits of the byte coincides with the number of bits of the byte. With the above configuration, the access unit of the image data
Memory can be
Above, the logic synthesis of the image data becomes possible. But
Image data with a processing device such as a microprocessor.
Bit address of image data between memory and memory
The need for a complicated circuit for generating the data is eliminated. In synthesizing images, the first image data is used as a reference.
Then, the position of the first image data is determined by the image data after synthesis.
Data is pre-determined as the location where data should be stored.
The operation of storing the image data of the
It is easy, and the processing required for storage becomes unnecessary, resulting in
The image synthesis processing becomes faster. [Embodiment of the Invention] An explanation will be given taking an example of image processing as shown in FIG.
In FIG. 1, M1 is a CRT (Cathode Ray Tube) screen and
One-to-one image area, M2 is image data to be combined
The stored storage areas XA and XB are the image area M1 and the case.
Processing areas that are actually image processing targets in the delivery area M2
A, WA0-2, WB0,1 are divided into 16-bit units, for example.
The word boundary to cut, R0-w represent raster units, na, n
b is the number of bits in each raster R0 to m of the processing areas XA and XB
Values A0-n and B0-n are words in processing areas XA and XB.
Address and FC are processing errors with different bit start values na and nb.
M for aligning rear XA and XB internally and performing logical operations
odify function. As shown in FIG. 1, the image area M1 and the storage area M2
Takes a structure that is aware of byte or word boundaries. This
This means that current processing units such as microprocessors
It is in units of words or words, so its data and
Access method for dress or byte boundary only
Because it is taking. However, when performing image processing
Is a word boundary, like the processing areas XA and XB shown in FIG.
Take a data array that ignores the world. Therefore, the processing area
To perform image processing between XA and XB, the Modify function FC
The following three processing functions are required. (1) Processing areas XA and XB with different bit start positions na and nb
So that processing can be performed between
Word data in processors that handle
Perform the conversion. (2) As described above, a memory having a word boundary structure
Since data access is in word units,
The data at address A0 of processing area XA is na bit data.
Data is not processed. Therefore, this na bit data
Function to remove and save data from arithmetic processing (mask)
Is required. (3) Further, the normal image processing is performed by a single pixel representing a pixel.
This is done on a pixel-by-pixel basis, while
In no-chrome display, each pixel is represented by one bit,
-In display, multiple bits per pixel (usually 4 bits)
Express. Therefore, the operation processing unit can be performed with an arbitrary bit width.
And the function of the above (2) is required. Above
Operation of Modify function FC with three processing functions second
This will be described with reference to the drawings. FIG. 2 shows, for example, a word unit.
It is assumed that data is accessed by
In the description, all word units are assumed. In the figure,
SRC (A) and (B) are the software read from processing area XB.
Registers for storing source data, DST (A) and (B)
Destination data read from processing area XA
The registers to be stored, MRG (A) and (B) are the processing areas XA and
The result of the arithmetic processing between XB, that is, the registers SRC (A),
Calculation processing of (B) and register, DST (A), (B)
This is a register that stores the result. Note that the above registers
SRC (A), (B) and DST (A), (B)
It has a data length of 2 words. Of these, register SRC
(A) and (B) are the bit addresses of the processing areas XA and XB.
Operation using SN (= nb) and DN (= na)
I do. (A) When SN> DN, rotate to the left by the value of SN-DN
I do. (B) When SN <DN, rotate right by DN-SN value
I do. (C) No rotation operation when SN = DN. In this way, each bit address nb (SN), na (DN) is used
And adjust the operation start bit position.
The bit width of the elephant is calculated by the preset width of WN.
Other non-processed data is saved. here,
In FIG. 2, registers DST (A) and (B) and register MRG
(A) and (B) have different hardware structures,
Even the same register has no effect on operation. What
The contents of rotated registers SRC (A) and (B)
Is the bit position before operation processing automatically after the operation processing is completed.
To the original location. Next, referring to FIGS. 3, 4, 5, 6 and FIG.
Image processing between processing areas XA and XB by 4 bits
The processing procedure in the case of performing the processing in units of width will be described in detail. Fig. 3
In S1, the start word address A0 of the processing area XA is
The processing step to be set, S2 is the start bit position (address
S) Processing step to set na to SN, S3 is processing area XB
Processing step for setting the start word address B0 of
Processing step for setting start bit position (address) nb to SN
Up, S5 is a Modify function FC that has the above-mentioned Modify function
S6 to S9 are processing steps in the processing area XB.
In the logical step, S6 is a processing step for finding the next bit address.
Step, S7 is a processing step for setting the next SN, S8
Is a processing step of updating the address in word units, and S9 is
Processing step for read access to the next word data,
S10 to S14 are processing steps in the processing area XA.
Is the processing step for finding the next bit address, S11 is the next
S12 is a processing step for setting the DN, where the calculation result is stored.
Write access to the contents of register MRG (A)
Step S13 updates the address in word units.
In step S14, the next word data is read
This is a processing step to access. SB1 and SB2 are the judgment processing steps.
And performs determination processing as described below. (I) Judgment processing in processing step SB1 The value of the next bit address obtained in processing steps S6 and S7 is
It is determined whether there is a branch or not. Processing in processing steps S6 and S7
(Equation (1)) and the determination method (Equation (2)) are shown below. SN = SN + WN ... (1) Branch processing when SN ≥ (10) Hex ... (2) That is, the current operation crosses the current word boundary.
Or not exceed (read access of the next word data is
Is necessary or not). (II) Judgment processing of processing step SB2 In processing step SB2, as in (I) above, the DN
In steps S10 and S11, the
You. Here, the difference from (I) is that write access (S12) is performed when DN ≧ (10) Hex (3). You
That is, the expression (3) holds true at the current word boundary.
Indicates that the calculation processing in
Write access to the processing area XA
Seth. The operations described so far are actually performed, for example, in the processing area XA.
Bit start position na (DN) = (A) Hex, processing area XB
When the start position nb (SN) = (5) Hex, the fourth to
It is shown in FIG. These series of figures show only raster R0.
I forgot. An improvement plan for the above embodiment will be described below. this
Is different from the above-mentioned embodiment in that (1) a conventional My address managing address in word units.
It performs bit-by-bit arithmetic processing with a microprocessor.
Management / control is very complicated.
It is. (2) Data access of processing area XA and processing area XB
Since the timing is different, if you try to manage it,
It is an improvement over the complexity of the process. (3) The data of the target image area M1 and storage area M2
The data volume is usually large, from 100K to several MBytes. others
A series of processing flows shown in FIG.
Even if it is performed in Byte unit (8 bits) ⁶ Order
And the number of processing steps is 1
But it needs to be reduced, and this is an improvement. In view of the above points, the other embodiments described below have the following features.
Have a sign. (1) Management of internal arithmetic processing is basically bit-
Managed by dress. (2) Therefore, for example, a conventional word address adder
Plus 4bit for managing bit addresses
Is newly added. (3) In the bit address adder, the current bit
Adds the address and the bit width to be operated on. (4) The above bit address adder and conventional word
The interface with the address adder is
This is performed using the carry signal of the adder. (5) The carry signal is captured from the viewpoint of internal processing management.
Then the current bit management changes the current word in the next cycle
Can be seen as a warning signal that it will exceed management
You. That is, the carry signal from the bit address adder
Is the data required for the bit operation at the next word boundary.
Signal to read data from memory
Become. (6) On the other hand, as described above, the bit address adder
The word address adder is integrated in hardware.
Logically divided (by the carry signal interface)
Su) has been. (7) Because of the logical division as described above,
Paying attention to the bit address adder alone,
Works on click. Therefore, the bit address adder
Output is always a bit address, that is, a word boundary
Automatically represent the bit address within
become. (8) The carry signal extraction position described so far
By changing any two ⁿ Create bit management at boundaries
You can get out. (9) In the bit address adder, the
Since the bit width is added independently, any bit width operation
It can be easily changed at the point of time. Hereinafter, other embodiments described above will be described in detail with reference to the drawings.
I do. In FIG. 7, ADW is, for example, word address addition.
, MIF is the memory interface section,
Image area M1 and storage area M2, for example, word data
Read or write access, and FC
Functionally equivalent three functions (1) to (3) and the processing described above
Area X _A , X _B By the values SN and DN representing the bit address of
-Modify function to perform the action (a)-(b), ADB
For example, a 4-bit bit address adder, WNR
SNR is a register that stores the value of WN representing the arithmetic bit width.
Processing area X _B Stores the operation start bit position SN in
Register, DNR is processing area X _A Operation start bit in
The register that stores the location DN, BR is the above three 4 bits
Bit register consisting of WNR, SNR and DNR
And AC are the carry signals from the bit address adder ADB.
Signal, MA is obtained from the word address adder ADW, for example
The word-based address bus D is, for example, a word-based data bus.
It is a data bus. This address bus MA and data
Bus D accesses image area M1 and storage area M2
Bus BM is the bit register BR and bit address
It is a bit management unit composed of an adder. In addition, bit
The contents (WN, SN, DN) of the register BR are changed by the Modify function FC.
used. First, the operation of the bit management unit BM which is the point of the present invention
Is outlined below. (B) A register for storing the operation start bit position SN or DN
Either SNR or DNR, and (B) the register WNR storing the operation bit width WN is added by (C) the bit address adder ADB, and the next row is added.
The operation start bit position SN or DN for the operation
(D) Store again in the corresponding register SNR or DNR
You. As described above, the bit management unit BM operates with the operation bit width WN.
Addition to the calculation start bit position SN or DN
The next operation start bit position is determined by hardware.
You. It should be noted that the synthesis processing of the normal image is performed in two different areas.
A combining process between certain image data is performed. Therefore, each area
Are different from each other. others
Therefore, the register that stores the operation start bit position is individual (SN
R and DNR). Here, register SNR
Processing area X _B Dedicated register for the operation start bit position of
And the register DNR is the processing area X _A Operation start bit
It has a position-only register. Therefore, processing area X _A In
When the next operation start bit position DN is found,
The addition result DN is stored in the register DNR, and the processing area X _B of
When the next operation start bit position SN is obtained, register SN
The value SN is stored in R. On the other hand, the register WNR stores the processing area X _A , X _B But different yes
Even though the operation bit width WN takes the same value,
And This register WNR completes a series of processing.
Retain the same value until it is rewritten or intentionally rewritten
Keep doing. The bit address adder ADB has four bits as described above.
The value range that can be expressed is (0)
_HEX ~ (F) _HEX Becomes That is, bit address addition
ADB output is always a bit within word boundaries.
Indicates the position of the However, the Modify function FC is needed
The actual bit width information is
(1) _HEX ~ (F) _HEX , And bit positions
A value beyond the word boundary (10) _HEX Need range including
I do. For this reason, the Modify function FC sets the operation bit width WN to the
It functions as shown in FIG. As described above, in the bit management unit BM, a word boundary (4 bits
Calculation of the bit position (address) in the
Click to always represent only the bit address. On the other hand, the address is updated in a conventional word unit
The word address adder ADW sends the word
The notification of the update of the word address is required by some means. In the following, the word address adder ADW and the bit address
For updating the word address between the adders ADB
The interface method will be described. Word address addition
The arithmetic unit ADW updates the address in word units as described above.
Bit management unit as an interface method to do
BM bit address adder ADB crosses a word boundary.
And take a way to notify. That is, the bit address
The carry signal AC from the calculator ADB was used. But as mentioned earlier
As shown, the 4-bit bit address adder ADB is represented.
Possible values and registers WNR, SNR, DN of the same 4-bit configuration
All values that R can represent are (0) _HEX ~ (F) _HEX It is.
Therefore, as described above, the operation bit width WN and the operation start
In addition with the packet position SN or DN, the carry signal is not necessarily
Can't get AC. For example, WN = (F) _HEX SN =
(0) _HEX In the case of, the operation for one word (eighth
As shown in the figure, the operation bit width of 16 bits is specified)
To do so, the next process must cross the current word boundary
Which indicates that the word boundary is crossed as shown in equation (4).
No carry signal AC is output. WN + SN = (F) _HEX + (0) _HEX = (F) _HEX (4) Therefore, the bit address adder ADB performs the addition process.
Must be added as shown in equation (4).
I have to. (WN + 1) + SN = (F) _HEX + (1) _HEX + (0) _HEX = (10) _HEX … (4) In this way, by adding “1”, the necessary carry signal AC
Can be output. Therefore, it is not necessary to add this “1”.
It will be indispensable. The carry signal AC described above is used in the next operation cycle.
The bit position crosses or crosses the current word boundary
It can be used as a determination signal as to whether or not there is. sand
That is, the carry signal AC from the bit address adder ADB
(1) See the warning signal that new data is needed
Can be (2) Add word address using this signal AC
By updating the device ADW, the data of (1) above can be accessed.
Addresses to be generated at the same time. That is, from the bit address adder ADB
The carry signal AC of the processing area X as shown in FIG. _A ,
And X _B Of the memory interface MIF to the
It can be used as timing. Start calculation
Registers SNR and DNR that store bit positions SN and DN
(1) and (2) are different from each other.
Area X _A And X _B Can work on units. The embodiment of the present invention described so far is illustrated in FIG.
FIG. 10 shows a processing flow when applied to image processing. In FIG. 10, P1 includes up to the operation start bit position nb.
Processing area X _B Address B _O And set nb (nb is SNR
Set: SN = nb) Processing step, P2 starts calculation
Processing area X including bit position na _A Address A _O as well as
Processing steps to set na (na is set to DNR: DN = na)
Up, P3 is a Modify function FC that has the Modify function described above.
Processing step, P4 is the bit address adder ADB and
Processing area X using the word address adder ADW _B To
Processing step to find the next operation start bit position SN
And P5 are processing area X in the same way as P4 _A Next operation in
XP1 is a processing step for determining the start bit position SN.
Rear X _B Processing steps to read word data from
Up, XP2 is processing area X _A Read the operation result for
Processing step for write access, XP3 is processing area X
_A Processing step to read word data from
, PB1 is Raster R _O Determines the end of a series of processing in units of m
XB1 and XB2 are the presence or absence of carry signal AC
Determines the execution of the processing steps XP1, XP2, XP3
This is a processing step. In the above processing steps XB1 and XB2, the following judgment processing
I do. (1) The target range of the next operation is the current word boundary
It is determined whether it is inside or outside the boundary. (2) In processing step XB1, the current word boundary
(Case 1 in FIG. 9), the processing step XP1 is not executed,
Processing area X if within word boundary (Fig. 9 Case2) _B Or
Reads the word data necessary for the next operation
The processing step XP1 to be accessed is executed. (3) In processing step XB2, it is outside the word boundary (Fig. 9C
If ase3), the processing steps XP2 and XP3 are not executed. I
However, if it is outside the word boundary (Fig. 9, Case 4),
Area X _A Reads the next word data from
Access processing step XP3 is executed. (4) In Case 4, the processing area is
A X _A Execute processing step XP2 for write access to
Run. That is, processing area X _A Is as described above (Fig. 1)
Image area M1 corresponding to the CRT screen on a one-to-one basis,
This is the write access of the processed data (result).
Indicates an elephant area. On the other hand, in the register DNR
Processing area X _A Using DN to manage the operation start bit position of
The next start position, for example, the current word boundary
Exceeding that means that the processing for one word has been completed.
Show. The determination in the above processing steps XB1 and XB2
Is the carry from the bit address adder ADB as described above.
This is performed depending on the presence or absence of the signal AC. Furthermore, this carry signal
Signal AC is the signal when any register DNR or SNR is used.
Thus, the four cases shown in FIG. 9 can be easily distinguished.
Therefore, as shown in FIG.
Fig. 10
Processing steps consisting of processing steps XB1 and XP1 shown in
A process consisting of a group of steps X1 and processing steps XB2, XP2 and XP3
The logical step group X2 can be deleted. In FIG. 11,
P ₁ ~ _Five , PB1 are the same as the processing steps shown in FIG.
This is a processing step for performing processing. The operation of the present invention described so far is shown in FIGS. 12 to 14.
You. The initial values shown in these figures are for processing area X _B Smell
Calculation start bit position SN = (5) _HEX , Word address
B _O , Processing area X _A Calculation start bit position DN =
(A) _HEX , Word address A _O , And the operation bit width WN =
(3) _HEX Is shown. FIG. 12 shows FIG.
FIG. 13 shows case 1 and case 3, and FIG.
The figure shows case2. With the above configuration, the following effects can be achieved. (1) A new bit is added to the conventional word address adder ADW.
Calculation by adding the address adder ADB
Operation processing between data with different start bit positions SN or DN
Management and its control are simplified. (2) The carry signal A of the bit address adder ADB
Let C be the update signal for the word address adder ADW and two more
By providing separate registers SNR and DNR,
Word processing for the internal arithmetic processing
Rear X _A Or X _B Data access timing to
And it can be done easily. (3) Bit and word address management and external data
By implementing hardware access control for data
The flow is simplified and its processing steps are compared with the conventional
(Refer to Fig. 3 and Fig. 11)
Higher speed can be achieved. As described above, the embodiment described above has the following hardware.
A. (1) Bit address adder ADB (2) Two registers SNR and DNR The above hardware, for example, accesses external data
If the unit is word, 4-bit configuration or access unit
If the place is a byte, it has a 3-bit configuration,
Hardware increase is small. But this
The software for this, that is, the effect on processing
As described above, this is a very large effect. [Effect of the Invention] As is clear from the above description, according to the present invention,
The access unit of image data can be word unit.
The logical combination of the image data on the memory
Is possible. Therefore, such as microprocessor
An image is stored between the processing device and a memory for storing image data.
Eliminates the need for complicated circuits to generate data bit addresses
Become. In synthesizing images, the first image data is used as a reference.
Then, the position of the first image data is determined by the image data after synthesis.
Data is pre-determined as the location where data should be stored.
The operation of storing the image data of the
It is easy, and the processing required for storage becomes unnecessary, resulting in
The image synthesis processing becomes faster.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing image data processing targeted by the present invention;
FIG. 2, FIG. 3, FIG. 4, FIG. 5, and FIG. 6 are views showing an embodiment of the present invention, FIG. 7, FIG. 8, FIG.
FIG. 11, FIG. 12, FIG. 13, and FIG. 14 are views showing another embodiment of the present invention. ADB: bit address adder WNR: register SNR storing operation bit width WN ... register DNR storing operation start bit position SN ... register AC storing operation start bit position DN: carry signal

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Hiroaki Aozu               292 Yoshida-cho, Totsuka-ku, Yokohama-shi Co., Ltd.               Hitachi, Ltd. microelectronics machine               Instrument development laboratory (72) Inventor Kiichiro Urabe               1 Horiyamashita, Sono City Hitachi, Ltd.               Tokoro Kanagawa Factory                (56) References JP-A-53-83537 (JP, A)                 JP-A-58-178470 (JP, A)

Claims (1)

(57) [Claims] A first image data consisting of a set of a plurality of bits and a second image data consisting of a set of a plurality of bits are arbitrarily stored in a memory composed of a number of bits and divided into word units each having a predetermined number of bits. Memorize from bit position,
Logically combining the first image data and the second image data and storing the combined image data in the memory, wherein the first image data from the memory and the second image data from the memory The second image data to be combined with the first image data is sequentially read in units of the divided words including the image data, and the read image data is stored in a register in units of a plurality of words. The second image data in the word including the stored second image data is subjected to a bit position matching process based on the first image data in the word including the read first image data. By logically synthesizing the first image data in the word including the read first image data, an arbitrary bit position in which the first image data is stored And logically synthesizing the second image data having an arbitrary bit width, and sequentially storing the synthesized image data subjected to the logical synthesis processing at a word position of the memory from which the first image data is read, in units of the word. An image processing method characterized by the following. 2. The first image data is image data to be combined, and the second image data is
2. The image processing method according to claim 1, wherein said image data is composite image data. 3. 2. The image processing method according to claim 1, wherein the first image data and the second image data are pixel data. 4. 2. The image processing method according to claim 1, wherein the number of bits in a word unit is equal to the number of bits in a byte. 5. A first unit comprising a number of bits, divided into word units each having a predetermined number of bits,
A memory for storing image data of a plurality of bits and a second image data composed of a set of a plurality of bits from an arbitrary bit position; and a word obtained by dividing the first image data and the second image data into units. Sequentially input, store the input image data in a register in units of multiple words,
Bit position matching of the second image data in the word including the second image data stored in the register with reference to the first image data in the word including the input first image data By processing and logically synthesizing the first image data in the word including the input first image data, from an arbitrary bit position where the first image data is stored, to an arbitrary bit width. A data processing unit for logically synthesizing the second image data, the first image data from the memory, the first image from the memory, and the second image data to be synthesized with the data. The divided words including data are sequentially read out in units and manually input to the data processing unit, and the synthesized image data subjected to the logical synthesis processing from the data processing unit is read from the first image data. The image processing apparatus formed by and a memory access unit for sequentially storing units of the word to a word location of the memory was hung. 6. The first image data is image data to be combined, and the second image data is
6. The image processing apparatus according to claim 5, wherein the image data is composite image data. 7. The image processing apparatus according to claim 5, wherein the first image data and the second image data are pixel data. 8. 6. The image processing apparatus according to claim 5, wherein the number of bits in word units matches the number of bits in bytes.