JP2915003B2 - Method for manufacturing field effect transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a field effect transistor.

[Conventional technology]

A method of realizing a two-stage recess structure in a field-effect transistor is described in IEE, International Electron Device Meeting Preprints (19)
1988) pages 172 to 175 (IEEE, IEDM.1988, pp.172-1)
75) There is the technology described. In this conventional example, since the recess structure is formed by a wet etching method, there is a problem in controllability and uniformity of the recess shape after formation.

[Problems to be solved by the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the controllability and the instability of uniformity at the time of forming a two-step recess structure, which are the problems of the prior art.

[Means for solving the problem]

In order to achieve the above object, the present invention uses the following technical means.

1. A second, a third, and a fourth semiconductor layer are provided in this order on a first semiconductor layer to which a gate electrode is attached and which contains Al as a component, and the third semiconductor layer contains Al as a component. The semiconductor layer which has it is introduced.

2. Etching the fourth, third, and second semiconductor layers in this order, and performing recess etching in the vicinity of the gate electrode in two steps, using a dry etching method for etching the fourth and second semiconductor layers. .

At this time, the fourth semiconductor layer is selectively etched with respect to the third semiconductor layer. Further, the second semiconductor layer is selectively etched with respect to the first semiconductor layer that covers the underlying gate electrode.

Further, one or two layers on the surface of the three semiconductor layers, that is, the fourth semiconductor layer or this layer and the third semiconductor layer are removed so as to recede from the gate electrode.

[Action]

1. Of the first semiconductor layer on which the gate electrode is deposited and the second, third, and fourth semiconductor layers provided thereon,
The first and third semiconductor layers containing Al act as stopper layers when selectively etching the fourth semiconductor layer.

2. By selectively etching the fourth and second semiconductor layers, the uniformity of each step of the two-step recess and the processing controllability are remarkably improved.

〔Example〕

An embodiment in which the present invention is applied to an AlGaAs / GaAs 2DEGFET will be described below with reference to FIGS.

As shown in FIG. 1A, an undoped GaAs layer (4000 °) 2 and an undoped Al _0.3 Ga _0.7 As layer (20
Å) 3, Si-doped Al _0.3 Ga _0.7 As layer (2 × 10 ⁻¹⁸ cm ⁻³ , 300
Å) 4, undoped Al _0.3 Ga _0.7 As layer (100 Å) 5, Si-doped GaAs layer (2 × 10 ¹⁷ cm ^-3 , 700 Å) 6, Si-doped Al _0.15 Ga
_0.85 As layer (2 × 10 ¹⁷ cm ⁻³ , 50 mm) 7, Si-doped GaAs layer (2
× 10 ¹⁸ cm ^-3 , 1000Å) 8 is epitaxially grown.
The epitaxy is performed by the MBE method.

Next, as shown in FIG. 1B, a source electrode 10 and a drain electrode 9 are formed using a photolithography process and a vacuum evaporation method. Au (1000 金属) / Ni (100
Å) Alloy at 400 ° C for 1 minute using / AuGe (500Å).

Next, as shown in FIG. 1C, the opening of the photoresist 11 is formed by using a photolithography process.
Provided between 10 and the drain electrode 9. Subsequently, the Si-doped GaAs layer 8 is selectively etched through the opening. A dry etching method is used for the etching, and a mixed gas of CCl ₂ F ₂ and He is used as an etching gas.

Next, as shown in FIG. 1D, a window of a photoresist 12 is provided at a portion where the Si-doped GaAs layer 8 has been removed, approaching the source electrode 10 side. Subsequently, a part of the Si-doped Al _0.15 Ga _0.85 As layer 7 and a part of the Si-doped GaAs layer 6 are etched through the window of the photoresist 12. A mixed solution of H ₃ PO ₄ : H ₂ O ₂ : H ₂ O is used for etching. Subsequently, the remaining Si-doped GaAs layer 6 is selectively etched. For the etching, a dry etching method is used.

Next, as shown in FIG.
Al (5000 °) is vacuum-deposited through the window of FIG. 1 and then lifted off to form a gate electrode 13.

By the above method, an offset gate and a two-step recess structure can be formed. The second recess depth is always GaAs layer 6.
And the thickness of the Al _0.15 Ga _0.85 As layer 7 are equalized, so that the influence of the surface potential can be removed with a sufficient degree of uniformity even on a large-diameter wafer.
Accordingly, even when a positive gate voltage is applied to the 2DEGFET, the deterioration of the transconductance is suppressed, so that the output gain during large signal operation is improved by about 20%.

By the way, as described above, in order to completely eliminate the influence of the surface potential, the GaAs layer 6 and the Al _0.15 Ga _0.85 As layer 7 are required.
Is set so as to be substantially equal to the width of the depletion layer due to the surface potential. Actually, since it is desirable that the Al _0.15 Ga _0.85 As layer 7 is thin, it is approximately ignored and the thickness t of the GaAs layer 6 is set by the following equation.

Here, ε is the dielectric constant of the GaAs layer 6, N is the concentration, q is the elementary charge, V
s is the surface potential (about 0.7V).

In the above embodiment, the present invention is applied to an AlGaAs / GaAs HEMT.
Has been described, but the present invention relates to other 2DEGFE
Applicable to T. As an example, a 2DEGFET based on InAlAs / InGaAs
And an AlGaAs / InGaAs-based 2DEGFET.

〔The invention's effect〕

According to the present invention, since the two-step recess structure can be formed with good controllability and uniformity, the following effects can be obtained.

1. Variations in element characteristics can be reduced, and characteristics when the elements are integrated are improved.

The main purpose of providing the second step in the 2.2-step recess structure is to remove the influence of the surface potential, but by improving the etching controllability, the influence of the surface potential can be removed without excess and deficiency. The characteristics are improved.

[Brief description of the drawings]

FIGS. 1A to 1E are cross-sectional views of a process for processing an element portion for explaining an example in which the present invention is implemented in the manufacture of an AlGaAs / GaAs 2DEGFET. 1 ... GaAs semi-insulating substrate, 2 ... undoped GaAs layer,
3 ... Undoped Al _0.3 Ga _0.7 As layer, 4 ... Si doped Al
_0.3 Ga _0.7 As layer, 5... Undoped Al _0.3 Ga _0.7 As layer, 6
... Si-doped GaAs layer, 7 ... Si-doped Al _0.15 Ga _0.85 As
Layer 8, Si doped GaAs layer 9, drain electrode 10,
... source electrode, 11, 12 ... photoresist, 13 ... gate electrode.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Susumu Takahashi 1-280 Higashi Koikebo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-62-202564 (JP, A) JP-A-2 -101751 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 27/098 H01L 29/775-29/778 H01L 29 / 80-29/812

Claims (1)

(57) [Claims] 1. A semiconductor device comprising: a first semiconductor layer on which a gate electrode is deposited;
Al is contained in the component, and second, third and fourth semiconductor layers are formed in this order on the first semiconductor layer, and the second, third and fourth semiconductor layers are formed near the gate electrode. A method of manufacturing a field-effect transistor having a two-stage recess structure in which the fourth semiconductor layer or the layer and the third semiconductor layer are removed and the gate electrode is recessed. When etching the third and second semiconductor layers in this order, the fourth semiconductor layer is etched by selective dry etching with respect to the third semiconductor layer.
A method for manufacturing a field effect transistor, wherein the second semiconductor layer is etched by selective dry etching with respect to the first semiconductor layer.