JP2919644B2 - Method for manufacturing multilayer wiring board - Google Patents
Method for manufacturing multilayer wiring boardInfo
- Publication number
- JP2919644B2 JP2919644B2 JP15714291A JP15714291A JP2919644B2 JP 2919644 B2 JP2919644 B2 JP 2919644B2 JP 15714291 A JP15714291 A JP 15714291A JP 15714291 A JP15714291 A JP 15714291A JP 2919644 B2 JP2919644 B2 JP 2919644B2
- Authority
- JP
- Japan
- Prior art keywords
- resist layer
- inorganic filler
- solder
- wiring board
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 238000000034 method Methods 0.000 title claims description 19
- 239000011256 inorganic filler Substances 0.000 claims description 34
- 229910003475 inorganic filler Inorganic materials 0.000 claims description 34
- 238000004380 ashing Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 6
- 239000000945 filler Substances 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 51
- VTYYLEPIZMXCLO-UHFFFAOYSA-L Calcium carbonate Chemical compound [Ca+2].[O-]C([O-])=O VTYYLEPIZMXCLO-UHFFFAOYSA-L 0.000 description 16
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 229910000019 calcium carbonate Inorganic materials 0.000 description 8
- 239000002253 acid Substances 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 6
- 239000004925 Acrylic resin Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 238000010306 acid treatment Methods 0.000 description 3
- TZCXTZWJZNENPQ-UHFFFAOYSA-L barium sulfate Chemical compound [Ba+2].[O-]S([O-])(=O)=O TZCXTZWJZNENPQ-UHFFFAOYSA-L 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229920000178 Acrylic resin Polymers 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000003505 polymerization initiator Substances 0.000 description 2
- KCTAWXVAICEBSD-UHFFFAOYSA-N prop-2-enoyloxy prop-2-eneperoxoate Chemical compound C=CC(=O)OOOC(=O)C=C KCTAWXVAICEBSD-UHFFFAOYSA-N 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000000454 talc Substances 0.000 description 2
- 229910052623 talc Inorganic materials 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】本発明は多層配線基板の製造方
法、特に第２の配線層を無電界メッキにより形成する多
層配線基板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board, and more particularly to a method for manufacturing a multilayer wiring board in which a second wiring layer is formed by electroless plating.
【０００２】[0002]
【従来の技術】従来の多層配線基板の製造方法を図１０
乃至図１５を参照して説明する。図１０においては、ガ
ラスエポキシ等の絶縁基板（１１）の一主面に銅箔を貼
り付けて所望のパタ−ンにエッチングして形成した第１
の導電層（１２）が形成されている。2. Description of the Related Art A conventional method for manufacturing a multilayer wiring board is shown in FIG.
This will be described with reference to FIGS. In FIG. 10, a first surface formed by attaching a copper foil to one main surface of an insulating substrate (11) made of glass epoxy or the like and etching it into a desired pattern.
Of the conductive layer (12) is formed.
【０００３】図１１においては、基板全面にソルダ−レ
ジスト層（１３）を塗布する。ソルダ−レジスト層（１
３）は、多管能エポキシ樹脂（２０〜３０重量％）、エ
ポキシアクリレ−ト樹脂（１０〜１５重量％）、熱硬化
性アクリル樹脂（４０〜５０重量％）、重合開始剤、溶
剤および無機フィラーで組成され（特開昭６２−２５３
６１３号公報参照）、所望のパタ−ンに露光、現像する
ことにより任意の場所にコンタクト孔（１４）を形成し
ている。無機フィラー（１５）としては、結晶性あるい
は非晶性シリカ（ＳｉＯ2）、タルク（Ｍｇ3（Ｓｉ
Ｏ10）（ＯＨ）2）、沈降性硫酸バリウム（ＢａＳＯ4）
などが用いられるが、シリカは酸不溶性のため後の２つ
が酸可溶性の無機フィラー（１５）として用いられる。In FIG. 11, a solder-resist layer (13) is applied to the entire surface of a substrate. Solder resist layer (1
3) is a multitubular epoxy resin (20 to 30% by weight), an epoxy acrylate resin (10 to 15% by weight), a thermosetting acrylic resin (40 to 50% by weight), a polymerization initiator, a solvent and It is composed of an inorganic filler (JP-A-62-253).
No. 613), a contact hole (14) is formed at an arbitrary position by exposing and developing a desired pattern. As the inorganic filler (15), crystalline or amorphous silica (SiO 2 ), talc (Mg 3 (Si
O 10 ) (OH) 2 ), precipitated barium sulfate (BaSO 4 )
Although silica is used, the latter two are used as an acid-soluble inorganic filler (15).
【０００４】図１２においては、ソルダ−レジスト層
（１３）表面から露出した無機フィラ−（１５）を塩酸
あるいは硫酸などの酸を用いて溶かす。この結果、溶け
た無機フィラー（１５）の後にくぼみ（１６）が形成さ
れ、ソルダ−レジスト層（１３）の表面の粗化が行われ
る。図１３においては、ソルダ−レジスト層（１３）表
面に銅の無電界メッキにより第２の配線層（１７）を形
成する。本工程では、第２の配線層（１７）がくぼみ
（１６）内に入り込み、アンカ−効果により第２の配線
層（１７）の接着強度を強くしている。In FIG. 12, an inorganic filler (15) exposed from the surface of a solder resist layer (13) is dissolved using an acid such as hydrochloric acid or sulfuric acid. As a result, a depression (16) is formed after the dissolved inorganic filler (15), and the surface of the solder-resist layer (13) is roughened. In FIG. 13, a second wiring layer (17) is formed on the surface of the solder-resist layer (13) by electroless plating of copper. In this step, the second wiring layer (17) penetrates into the depression (16), and the adhesive strength of the second wiring layer (17) is increased by the anchor effect.
【０００５】なお斯上した多層配線基板の製造方法とし
ては、例えば特開昭５２−４４８８２号公報（Ｂ０５Ｄ
５／００）等で知られている。A method for manufacturing such a multilayer wiring board is disclosed in, for example, JP-A-52-44882 (B05D).
5/00).
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、従来の
多層配線基板の製造方法では、図１４に示すようにソル
ダ−レジスト層（１３）に混入した無機フィラー（１
５）は形状が粒形のため、大部分がソルダ−レジスト層
（１３）内に沈み、その表面に露出している無機フィラ
ー（１５）の密度が低下する。このため酸で溶かしても
図１５に示すように、ソルダ−レジスト層（１３）表面
に形成されるくぼみ（１６）が少なく、第２の配線層
（１７）の接着強度が十分でない問題点を有していた。However, in the conventional method of manufacturing a multilayer wiring board, as shown in FIG. 14, the inorganic filler (1) mixed in the solder-resist layer (13) is used.
In 5), since the shape is granular, most of the particles sink into the solder-resist layer (13), and the density of the inorganic filler (15) exposed on the surface is reduced. For this reason, as shown in FIG. 15, there is little depression (16) formed on the surface of the solder-resist layer (13), and the bonding strength of the second wiring layer (17) is not sufficient, as shown in FIG. Had.
【０００７】また無機フィラー（１５）として、タル
ク、沈降性硫酸バリウムを用いた場合、酸への溶け込み
が十分でなく、くぼみ（１６）の形成が不十分となり、
第２の配線層（１７）の接着強度が十分に得られない問
題点も有していた。[0007] When talc or precipitated barium sulfate is used as the inorganic filler (15), it does not sufficiently dissolve into the acid, and the formation of the depression (16) becomes insufficient.
There is also a problem that the adhesive strength of the second wiring layer (17) cannot be sufficiently obtained.
【０００８】[0008]
【課題を解決するための手段】本発明は斯る問題点に鑑
みてなされ、ソルダ−レジスト層表面をプラズマアッチ
ングした後、無機フィラーを酸で溶かすことにより、従
来の問題点を大幅に解決した多層配線基板の製造方法を
実現するものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and greatly solves the conventional problems by dissolving an inorganic filler with an acid after plasma etching the surface of a solder-resist layer. And a method for manufacturing a multilayer wiring board.
【０００９】[0009]
【作用】本発明に依れば、プラズマアッシングにより無
機フィラーを残存させてソルダ−レジスト層表面をエッ
チングするので、ソルダ−レジスト層表面近くの無機フ
ィラーがほとんど露出され、次の酸処理で酸と良く反応
して高密度にくぼみを形成できる点に特徴を有する。According to the present invention, since the surface of the solder-resist layer is etched by leaving the inorganic filler by plasma ashing, the inorganic filler near the surface of the solder-resist layer is almost exposed, and the acid is removed by the next acid treatment. It is characterized in that it can react well and form pits at high density.
【００１０】[0010]
【実施例】本発明による多層配線基板の製造方法を図１
乃至図９を参照して説明する。図１おいて、ガラスエポ
キシ、表面をアルマイト処理したアルミニウム等の絶縁
基板（１）の一主面に銅箔を貼り付けて所望のパタ−ン
にエッチングして形成した第１の導電層（２）が形成さ
れている。FIG. 1 shows a method of manufacturing a multilayer wiring board according to the present invention.
This will be described with reference to FIGS. In FIG. 1, a first conductive layer (2) formed by attaching a copper foil to one main surface of an insulating substrate (1) made of glass epoxy, aluminum whose surface is anodized, or the like and etching it to a desired pattern. ) Is formed.
【００１１】図２において、基板全面にソルダ−レジス
ト層（３）を塗布する。ソルダ−レジスト層（３）は、
多管能エポキシ樹脂（２０〜３０重量％）、エポキシア
クリレ−ト樹脂（１０〜１５重量％）、熱硬化性アクリ
ル樹脂（４０〜５０重量％）、重合開始剤、溶剤および
無機フィラーで組成されている（特開昭６２−２５３６
１３号公報参照）。このソルダ−レジスト層（３）はベ
−クされた後、所望のパタ−ンに露光、現像することに
より任意の場所にコンタクト孔（４）が形成される。こ
のコンタクト孔（４）はバイアホ−ル形状、すなわち上
方のみに開口し、下面には第１の導電層（２）を選択的
に露出している。In FIG. 2, a solder-resist layer (3) is applied to the entire surface of the substrate. The solder-resist layer (3)
Composition with multitubular epoxy resin (20-30% by weight), epoxy acrylate resin (10-15% by weight), thermosetting acrylic resin (40-50% by weight), polymerization initiator, solvent and inorganic filler (Japanese Patent Laid-Open No. 62-2536)
No. 13). After the solder resist layer (3) is baked, a contact hole (4) is formed at an arbitrary position by exposing and developing a desired pattern. The contact hole (4) has a via hole shape, that is, it is opened only upward, and the first conductive layer (2) is selectively exposed on the lower surface.
【００１２】図３において、ソルダ−レジスト層（３）
表面をＯ2プラズマアッシングする。本工程は、本発明
のもっとも特徴とする工程であり、Ｏ2プラズマアッシ
ングにより選択的に無機フィラー（５）を除くソルダ−
レジスト層（３）を表面から削っている。さらに図６か
ら図７を参照して詳述すると、図６に示すように無機フ
ィラー（５）がソルダ−レジスト層（３）内に混入され
ている。無機フィラー（５）としては、炭酸カルシュウ
ム（ＣａＣＯ3）を用い、その粒径は最大５μｍの範囲
内で、平均粒径は０．２μｍ以下とする。また無機フィ
ラー（５）は３０〜５５重量％の範囲内で混入してい
る。従って、無機フィラー（５）の大部分は図６のよう
にソルダ−レジスト層（３）内に存在し、ソルダ−レジ
スト層（３）の表面より露出しているものは少ない。次
に、図７に示すようにソルダ−レジスト層（３）の表面
からＯ2プラズマアッシングを行うので、無機フィラー
（５）は残存したままで、ソルダ−レジスト層（３）の
有機材料のみがアッシングされて削られていく。このた
めソルダ−レジスト層（３）のアッシング面には表面近
くにある無機フィラー（５）が必ず露出された状態とな
り、ソルダ−レジスト層（３）表面全面に高密度でかつ
均一に無機フィラー（５）が露出される。この状態で次
工程へ移る。In FIG. 3, a solder-resist layer (3)
The surface is subjected to O 2 plasma ashing. This step is the most characteristic step of the present invention, and the solder is selectively removed by O 2 plasma ashing to remove the inorganic filler (5).
The resist layer (3) is shaved from the surface. More specifically, referring to FIGS. 6 and 7, the inorganic filler (5) is mixed in the solder-resist layer (3) as shown in FIG. As the inorganic filler (5), calcium carbonate (CaCO 3 ) is used, and its particle size is within a maximum of 5 μm, and its average particle size is 0.2 μm or less. The inorganic filler (5) is mixed in the range of 30 to 55% by weight. Therefore, most of the inorganic filler (5) is present in the solder-resist layer (3) as shown in FIG. 6, and few are exposed from the surface of the solder-resist layer (3). Next, as shown in FIG. 7, since the O 2 plasma ashing is performed from the surface of the solder-resist layer (3), only the organic material of the solder-resist layer (3) remains while the inorganic filler (5) remains. Ashing and shaving. For this reason, the inorganic filler (5) near the surface is always exposed on the ashing surface of the solder-resist layer (3), and the inorganic filler (3) is densely and uniformly distributed over the entire surface of the solder-resist layer (3). 5) is exposed. In this state, the process proceeds to the next step.
【００１３】なお本工程では、Ｏ2プラズマアッシング
と同時にコンタクト孔（４）内の有機物残査を除去でき
るので、コンタクト孔（４）の洗浄工程を兼用できる。
図４において、ソルダ−レジスト層（３）表面から露出
した無機フィラ−（５）を塩酸あるいは硫酸などの酸を
用いて溶かす。この結果、溶けた無機フィラー（５）の
後にくぼみ（６）が形成され、ソルダ−レジスト層
（３）の表面の粗化が行われる。In this step, since the organic residue in the contact hole (4) can be removed at the same time as the O 2 plasma ashing, the step of cleaning the contact hole (4) can also be used.
In FIG. 4, the inorganic filler (5) exposed from the surface of the solder resist layer (3) is dissolved using an acid such as hydrochloric acid or sulfuric acid. As a result, the depression (6) is formed after the dissolved inorganic filler (5), and the surface of the solder-resist layer (3) is roughened.
【００１４】図８を参照すると、本工程の酸処理で、前
工程で露出された表面近くの無機フィラー（５）は溶か
されて、ソルダ−レジスト層（３）の表面には多くの無
機フィラー（５）の溶けて形成されたくぼみ（６）がで
きる。またＯ2プラズマアッシング時にソルダ−レジス
ト層（３）表面も無機フィラー（５）のために凹凸に削
られるので、表面の粗化に協力することになる。さらに
無機フィラー（５）として炭酸カルシュウムを用いた場
合、一般的に炭酸カルシュウムが炭酸ガスの発生源とし
て良く利用されることから、酸と良く反応してReferring to FIG. 8, in the acid treatment of this step, the inorganic filler (5) near the surface exposed in the previous step is dissolved, and a large amount of inorganic filler is formed on the surface of the solder-resist layer (3). The melt-formed depression (6) of (5) is formed. Also, during the O 2 plasma ashing, the surface of the solder-resist layer (3) is also shaved into irregularities due to the inorganic filler (5), so that it cooperates with the surface roughening. Furthermore, when calcium carbonate is used as the inorganic filler (5), calcium carbonate generally reacts well with an acid since calcium carbonate is often used as a source of carbon dioxide gas.
【００１５】[0015]
【数１】 (Equation 1)
【００１６】となる。ＣａＯは酸に良く溶け出して、表
面に露出した無機フィラー（５）の部分に確実にくぼみ
（６）を形成する利点を有する。図５において、ソルダ
−レジスト層（３）表面に銅の無電界メッキにより第２
の配線層（７）を形成する。本工程では、第２の配線層
（７）がくぼみ（６）内に入り込み、アンカ−効果によ
り第２の配線層（７）の接着強度を強くしている。## EQU1 ## CaO has the advantage of being well dissolved in the acid and reliably forming the depression (6) in the portion of the inorganic filler (5) exposed on the surface. In FIG. 5, the surface of the solder-resist layer (3) is secondly formed by electroless plating of copper.
The wiring layer (7) is formed. In this step, the second wiring layer (7) enters the recess (6), and the adhesive strength of the second wiring layer (7) is increased by the anchor effect.
【００１７】次に本発明を用いたときの接着強度の特性
について、図９を参照して説明する。図９では、無機フ
ィラー（５）として炭酸カルシュウムを用い、Ｘ軸にソ
ルダ−レジスト層（３）の固形成分に対する炭酸カルシ
ュウムの混入量を取り、Ｙ軸に第２の配線層（７）の接
着強度を取っている。具体的には、１cm幅の第２の配線
層（７）がどれくらいの力でソルダ−レジスト層（３）
から剥がれるかを実験している。また無機フィラ−
（５）の混入量は５５重量％を越えると、ソルダ−レジ
スト自体が膜を形成できなくなるので、それ以上の混入
は図９には示さない。ここで、図９から明白な点は、炭
酸カルシュウムの混入量が３０重量％のとき接着強度は
０．５Ｋｇ／ｃｍであり、５０重量％のときは０．７Ｋ
ｇ／ｃｍであり、無機フィラ−（５）を多く混入すれば
確実にくぼみ（６）が増加していることが分かる。Next, the characteristics of the adhesive strength when the present invention is used will be described with reference to FIG. In FIG. 9, calcium carbonate is used as the inorganic filler (5), the mixing amount of calcium carbonate with respect to the solid component of the solder-resist layer (3) is plotted on the X axis, and the adhesion of the second wiring layer (7) is plotted on the Y axis. Has taken strength. Specifically, the 1 cm width second wiring layer (7) is applied to the solder-resist layer (3).
I'm experimenting with whether it comes off. Also inorganic filler
If the mixing amount of (5) exceeds 55% by weight, the solder resist itself cannot form a film, so that no further mixing is shown in FIG. Here, it is apparent from FIG. 9 that the adhesive strength is 0.5 kg / cm when the amount of calcium carbonate mixed is 30% by weight, and 0.7 Kg / cm when the amount of calcium carbonate is 50% by weight.
g / cm, and it can be seen that when the inorganic filler (5) is mixed in a large amount, the depression (6) is surely increased.
【００１８】[0018]
【発明の効果】本発明に依れば、ソルダ−レジスト層
（３）表面をＯ2プラズマアッシングするので、表面近
くにある無機フィラー（５）を確実に露出することがで
き、次の酸処理でくぼみ（６）を高密度でかつ均一に形
成できるので、第２の配線層（７）の接着強度を大幅に
増加できる利点を有する。According to the present invention, the solder - since the resist layer (3) surface O 2 plasma ashing, it is possible to reliably expose the inorganic filler (5) near the surface, the following acid treatment Since the depressions (6) can be formed with high density and uniformity, there is an advantage that the adhesive strength of the second wiring layer (7) can be greatly increased.
【００１９】また本発明では、ソルダ−レジスト層
（３）を接着強度の強い層間絶縁膜として利用可能とす
るので、多層の配線構造を容易に実現できる利点を有す
る。さらに本発明では、Ｏ2プラズマアッシング時にコ
ンタクト孔（４）の有機物残査も除去できるので、コン
タクト孔（４）の洗浄工程を省略できる利点も有する。Further, in the present invention, since the solder-resist layer (3) can be used as an interlayer insulating film having high adhesive strength, there is an advantage that a multilayer wiring structure can be easily realized. Further, according to the present invention, since the organic matter residue in the contact hole (4) can be removed at the time of O 2 plasma ashing, there is an advantage that the step of cleaning the contact hole (4) can be omitted.
【図１】本発明に依る多層配線基板の製造方法を説明す
る断面図である。FIG. 1 is a sectional view illustrating a method for manufacturing a multilayer wiring board according to the present invention.
【図２】本発明に依る多層配線基板の製造方法を説明す
る断面図である。FIG. 2 is a cross-sectional view illustrating a method for manufacturing a multilayer wiring board according to the present invention.
【図３】本発明に依る多層配線基板の製造方法を説明す
る断面図である。FIG. 3 is a cross-sectional view illustrating a method for manufacturing a multilayer wiring board according to the present invention.
【図４】本発明に依る多層配線基板の製造方法を説明す
る断面図である。FIG. 4 is a cross-sectional view illustrating a method for manufacturing a multilayer wiring board according to the present invention.
【図５】本発明に依る多層配線基板の製造方法を説明す
る断面図である。FIG. 5 is a cross-sectional view illustrating a method for manufacturing a multilayer wiring board according to the present invention.
【図６】本発明に依る多層配線基板の製造方法のプラズ
マアッシングを説明する断面図である。FIG. 6 is a cross-sectional view illustrating plasma ashing in the method for manufacturing a multilayer wiring board according to the present invention.
【図７】本発明に依る多層配線基板の製造方法のプラズ
マアッシングを説明する断面図である。FIG. 7 is a cross-sectional view illustrating plasma ashing in the method for manufacturing a multilayer wiring board according to the present invention.
【図８】本発明に依る多層配線基板の製造方法のプラズ
マアッシングを説明する断面図である。FIG. 8 is a cross-sectional view illustrating plasma ashing in the method for manufacturing a multilayer wiring board according to the present invention.
【図９】本発明に依る多層配線基板の製造方法により形
成した第２の配線層の接着強度を説明する特性図であ
る。FIG. 9 is a characteristic diagram illustrating the adhesive strength of a second wiring layer formed by the method for manufacturing a multilayer wiring board according to the present invention.
【図１０】従来の多層配線基板の製造方法を説明する断
面図である。FIG. 10 is a cross-sectional view illustrating a conventional method for manufacturing a multilayer wiring board.
【図１１】従来の多層配線基板の製造方法を説明する断
面図である。FIG. 11 is a cross-sectional view illustrating a conventional method for manufacturing a multilayer wiring board.
【図１２】従来の多層配線基板の製造方法を説明する断
面図である。FIG. 12 is a cross-sectional view illustrating a method for manufacturing a conventional multilayer wiring board.
【図１３】従来の多層配線基板の製造方法を説明する断
面図である。FIG. 13 is a cross-sectional view illustrating a method for manufacturing a conventional multilayer wiring board.
【図１４】従来の多層配線基板の製造方法のプラズマア
ッシングを説明する断面図である。FIG. 14 is a cross-sectional view illustrating plasma ashing in a conventional method for manufacturing a multilayer wiring board.
【図１５】従来の多層配線基板の製造方法のプラズマア
ッシングを説明する断面図である。FIG. 15 is a cross-sectional view illustrating plasma ashing in a conventional method for manufacturing a multilayer wiring board.
１ 絶縁基板 ２ 第１の導電層 ３ ソルダ−レジスト層 ４ コンタクト孔 ５ 無機フィラー ６ くぼみ ７ 第２の導電層 REFERENCE SIGNS LIST 1 insulating substrate 2 first conductive layer 3 solder-resist layer 4 contact hole 5 inorganic filler 6 depression 7 second conductive layer
フロントページの続き (56)参考文献 特開 昭61−252698（ＪＰ，Ａ) 特開 昭58−39099（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H05K 3/46 H05K 3/10 - 3/26 H05K 3/38 Continuation of the front page (56) References JP-A-61-252698 (JP, A) JP-A-58-39099 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H05K 3 / 46 H05K 3/10-3/26 H05K 3/38
Claims (2)
ィラーが混入されたレジスト層を被覆し、 前記第１の配線層が露出する接続孔を形成し、 前記無機フィラーを残し、前記レジスト層を除去するよ
うに表面をプラズマアッシングすると同時に前記接続孔
内の不純物を除去し、 前記レジスト層より露出された前記無機フィラーを取り
除くことで、前記レジスト層表面の粗化を行い、 前記レジスト層上に金属より成る第２の配線層を形成す
る事を特徴とした多層配線基板の製造方法。 An inorganic film is provided on a substrate on which a first wiring layer is formed.
Filler is coated with a resist layer which is mixed, the first wiring layer to form a contact hole exposing, leaving the inorganic filler, the resist layer is removed
Plasma ashing the surface as well as the connection holes
And removing the inorganic filler exposed from the resist layer.
By removing, the surface of the resist layer is roughened to form a second wiring layer made of metal on the resist layer.
A method for manufacturing a multilayer wiring board, characterized in that:
材料より成る請求項１に記載の多層配線基板の製造方
法。2. The method according to claim 1, wherein the resist layer is made of a material that can be exposed and developed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15714291A JP2919644B2 (en) | 1991-06-27 | 1991-06-27 | Method for manufacturing multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15714291A JP2919644B2 (en) | 1991-06-27 | 1991-06-27 | Method for manufacturing multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH057081A JPH057081A (en) | 1993-01-14 |
| JP2919644B2 true JP2919644B2 (en) | 1999-07-12 |
Family
ID=15643109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15714291A Expired - Fee Related JP2919644B2 (en) | 1991-06-27 | 1991-06-27 | Method for manufacturing multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2919644B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10886230B2 (en) | 2016-09-30 | 2021-01-05 | Samsung Electronics Co., Ltd. | Fan-out semiconductor package |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5758472B2 (en) | 2013-11-05 | 2015-08-05 | 太陽インキ製造株式会社 | Curable composition for printed wiring board, cured coating film using the same, and printed wiring board |
| JP2018014446A (en) | 2016-07-22 | 2018-01-25 | イビデン株式会社 | Solder resist and printed wiring board |
| CN115623698A (en) * | 2022-12-16 | 2023-01-17 | 淄博芯材集成电路有限责任公司 | Processing method of leadless electroplating |
-
1991
- 1991-06-27 JP JP15714291A patent/JP2919644B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10886230B2 (en) | 2016-09-30 | 2021-01-05 | Samsung Electronics Co., Ltd. | Fan-out semiconductor package |
| US10892227B2 (en) | 2016-09-30 | 2021-01-12 | Samsung Electronics Co., Ltd. | Fan-out semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH057081A (en) | 1993-01-14 |
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