JP2921299B2 - Logic level conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic level conversion circuit for digital signals, and more particularly to a logic level conversion circuit for converting a pseudo ECL level digital signal in the form of a scrambled NRZ code or CMI code into a CMOS level digital signal.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional pseudo ECL level to CM
FIG. 3 is a circuit diagram illustrating an example of a logic level conversion circuit for converting to an OS level. Positive power supply Vcc and negative power supply Ve of ECL LSI1
e is connected to +5 V and 0 V, respectively, and an open emitter output (pseudo ECL output terminal) O1 is connected to a terminating resistor Rt.
Vcc and Vee are connected via Rt3 and Rt4, respectively. The value of the terminating resistors Rt3, Rt4 is, for example, 100
Ohm and 150 ohms are used, and the level of the pseudo ECL output terminal O1 is so-called pseudo ECL of Vcc5V-0.8V at logic "1" and Vcc5V-1.6V at logic "0".
Level. The positive power supply Vdd and the negative power supply Vss of the CMOS LSI 2 are connected to +5 V and 0 V, respectively. C
On the MOS LSI2 side, this pseudo ECL level is set to CMOS.
A differential amplifier (hereinafter, referred to as AMP) 3 and a low-pass filter (hereinafter, referred to as LPF) 4 are used for conversion into a level. That is,
The pseudo ECL output terminal O1 is connected to the positive input terminal of AMP3, and the pseudo ECL output terminal O is connected to the negative input terminal of AMP3.
The output of the LPF 4 for extracting one DC component is connected. Here, the digital signal to be handled is a signal having a characteristic not accompanied by information transmission by a DC component, such as a CMI code. With this configuration, conversion from a pseudo ECL level signal to a CMOS level signal is performed.

[0003]

The conventional logic level conversion circuit has a problem in that when the ECL LSI is not mounted, the converted CMOS output becomes an indefinite value. That is, when the input is open, a DC potential obtained by dividing the potential of the positive power supply Vcc by the terminating resistors Rt1 and Rt2 is applied to the positive input terminal of the differential amplifier, and the same potential is applied to the negative input terminal. Therefore, it cannot be specified whether the output of the differential amplifier becomes logic “0” or logic “1”, and generally changes randomly due to the surrounding noise.

[0004] The most problematic is the case of converting a clock signal. In a conventional circuit, when a clock signal is interrupted, an unstable clock is transmitted to a subsequent stage due to "flutter" due to noise, and a subsequent device may fall into an unexpected state.

[0005]

A logic level conversion circuit according to the present invention comprises a low-pass filter for extracting a DC level of a pseudo ECL level digital signal, and a differential amplifier.
In a logic level conversion circuit for converting the pseudo ECL level digital signal to a CMOS level digital signal, the logic level conversion circuit is connected to only a negative power supply of the differential amplifier and is connected to the E.
A termination circuit for terminating the CL-level digital signal is provided.

The terminating circuit connects first and second terminating resistors in series to be connected between a pseudo ECL output terminal of an ECL LSI and the negative power source, and a capacitor in parallel with the second terminating resistor. Are connected.

[0007]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the logic level conversion circuit of the present invention. This embodiment differs from the conventional example shown in FIG. 2 in a pseudo ECL level termination circuit.

In the termination circuit of this embodiment, termination resistors Rt1 and Rt2 are connected in series from a pseudo ECL output terminal O1 to a negative power supply Vee, and a capacitor C is connected in parallel with the termination resistor Rt2.
t. The value in which the terminating resistors Rt1 and Rt2 are connected in series determines the bias current of the pseudo ECL output. The capacitor Ct is for short-circuiting the resistor Rt2 in an AC manner. Thus, the terminating impedance of the terminating circuit is determined only by the resistor Rt1. For example,
For transmitting a signal at a speed of about 150 MHz, Rt1 = 50 ohms and Rt2 = 170 ohms are selected while matching the characteristic impedance to 50 ohms.

The operation of the logic level conversion circuit of this embodiment when the pseudo ECL level signal is interrupted and opened will be described. In this case, both the positive input terminal and the negative input terminal of AMP3 have the potential of the negative power supply Vss. A
Although MP3 has the same potential for both inputs, its output is generally fixed to logic "0" because its potential is the negative power supply Vss potential, which is a low potential exceeding the active operation range as a differential amplifier. You.

[0010]

As described above, the present invention provides a pseudo EC
Even when the L level signal becomes open, the converted C
The MOS level signal is determined to be logic "0", which has the effect of solving the problem that the signal in the prior art becomes unstable and "flutters", thereby adversely affecting the subsequent device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a logic level conversion circuit of the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional logic level conversion circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 ECL LSI 2 CMOS LSI 3 Differential amplifier (AMP) 4 Low-pass filter (LPF) Ct capacitor Rt1, Rt2, Rt3, Rt4 Terminating resistor O1 Pseudo ECL output terminal

Claims (2)

(57) [Claims] A low-pass filter for extracting a DC level of a pseudo ECL level digital signal; and a differential amplifier, wherein the pseudo ECL level digital signal is converted to a CMO signal.
A logic level conversion circuit for converting an SCL digital signal into an S level digital signal, the logic level conversion circuit including a terminating circuit connected to only a negative power supply of the differential amplifier and terminating the ECL level digital signal. 2. The termination circuit according to claim 1, wherein the first and second terminating resistors are connected in series and connected between a pseudo ECL output terminal of an ECL LSI and the negative power source, and a capacitor is connected in parallel with the second terminating resistor. 2. The logic level conversion circuit according to claim 1, wherein the logic level conversion circuit is connected.