JP2927293B2 - Dynamic semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a dynamic semiconductor memory device.

(Prior Art) Among MOS semiconductor memories, a dynamic RAM (DRAM) having one transistor and one capacitor has been most highly integrated. Recent DRAMs are equipped with a high-speed access mode such as a page mode, a nibble mode, and a static column mode in addition to the random access mode. On the other hand, serial access, which can access one row of data at high speed and serially, is also used in the field of image processing or computer / cache memory.
Strong demand from system field.

The conventional page mode is a mode in which the data of the selected one-line sentence can be accessed randomly and at high speed. FIG. 9 shows a timing chart of a read cycle in this page mode, and FIG. 10 shows a timing chart of a write cycle.
With the address strobe signal (▲ ▼) active, the column address strobe signal (▲
▼) to toggle, and column ▲ ▼
By taking in the address, a read or write operation can be performed at random in the column direction. Therefore, by using this page mode, serial access can be performed in which data of one line is serially accessed at high speed by serially giving an address from the outside.

However, in serial access using this page mode, the column address must be fetched from the outside each time in response to the toggle of ▲ ▼, so there is a limit in speed. Explaining the reason specifically with reference to FIGS. 9 and 10, the column address setup time t _ASC and the column address hold time t _CAH are set for the falling edge of ▲ ▼. Therefore, a margin on the timing required for the strobe of the column address is required.

On the other hand, nibble and
There is a mode. FIGS. 11 and 12 show timing charts of a read cycle and a write cycle in the nibble mode, respectively. The nibble mode is similar to the page mode described above in that high-speed access of consecutive bits in the column direction is performed only by the toggle of ▼. However, in nibble mode, ▲
From the second cycle onward, the fetch of the column address is not required. In this regard, it is faster than nibble mode, which is a great advantage.

However, the nibble mode has the greatest difficulty in that the number of bits that can be accessed is limited, and cannot be applied to serial access. The number of bits that can be accessed is limited for the following reasons. In the nibble mode, a plurality of data are collectively sent to the data latch register in the first cycle of ▲, and from there, ▲
High speed access is realized by sequentially transferring data to the output port by the toggle of ▼. Therefore, the number of data latch registers is limited to the number of bits that can be accessed. Number of registers and 1
If the number of rows of data is the same, one row of data can be accessed serially at high speed, but 4-bit nibbles are now common, mainly due to chip area constraints.

(Problems to be Solved by the Invention) As described above, in the conventional DRAM, in order to perform high-speed serial access to all data of one row, there is a problem in high-speed performance in the page mode, and in the nibble mode. There is a problem that the bits that can be accessed are limited in terms of chip area.

The present invention solves such a problem and provides a high-speed serial
An object of the present invention is to provide an accessible DRAM.

[Structure of the Invention] (Means for Solving the Problems) A dynamic semiconductor memory device according to the present invention includes: a memory array in which a plurality of dynamic memory cells are arranged in rows and columns in a matrix; A row decoder for selecting a row, a column address buffer for holding a column address, and a column for selecting a column in the memory array according to the column address held in the column address buffer.
In the serial access mode in which at least two bits or more of the decoder and the plurality of memory cells arranged in the selected row are successively accessed, counting is performed sequentially according to the toggle operation of the column address strobe signal.
A serial address counter for generating and supplying a continuous column address to the column address buffer, counting up a refresh address of the memory array, and supplying the refresh address to the row address buffer; Is provided.

In addition, the dynamic semiconductor memory device of the present invention
A memory array in which a plurality of dynamic memory cells are arranged in rows and columns in a matrix manner; a row decoder for selecting a row in the memory array;
A column decoder for selecting a column in the memory array in accordance with an address, and a column decoder in a serial access mode for continuously accessing at least 2 bits or more of a plurality of memory cells arranged in a selected row. Serially generating a count up in response to a toggle operation of an address strobe signal and supplying the count up to the column decoder, counting up a refresh address at the time of refreshing the memory array, and supplying the refresh address to the row decoder An address counter.

Further, the dynamic semiconductor memory device of the present invention has a register for holding a refresh address, and the serial address counter is preset by the refresh address held in the register at the time of refresh.

(Operation) According to the present invention, each time the ▲
There is no need to take in the column address from outside when toggling ▼. Therefore, the column address setup time t _ASC and column address hold time
A faster page mode operation can be realized without requiring a timing margin such as t _CAH . By generating a serial address by a serial address counter, a high-speed serial access mode can be realized. Moreover, the provision of the serial address counter causes a smaller increase in chip area as compared with the case of providing a data latch register for storing one row of data in the nibble mode. Further, since the serial address counter is shared by the counter in the serial access mode and the refresh counter in the refresh, the chip size can be prevented from increasing.

(Example) Hereinafter, an example of the present invention will be described.

FIG. 1 is a block diagram showing a main configuration of a DRAM to which the present invention is applied. Row address buffer 1 and column address buffer 2 for capturing an external address, clock generators 3 and 4 for driving these address buffers 1 and 2, column decoder 5 for decoding the captured address, and row A decoder 6, a memory cell array 7 in which memory cells of one transistor and one capacitor driven by these decoder outputs are arranged, a sense amplifier for exchanging data with the memory cell array 7, and
I / O gate 8, input buffer for latching input / output data
9, an output buffer 10, a substrate bias generation circuit 11, and a refresh counter 12 for self-refreshing the memory cell array. These main components are conventional DRAM
And does not change. In this example, in addition to these, the serial address
The counter 13 is built in. This serial address
The counter 13 is configured to count up in response to the toggle of ▲, and its output is input to the column address buffer 2.

FIG. 2 shows an embodiment in which the configuration of FIG. 1 is slightly modified. In this example, the output of the serial address counter 13 is directly input not to the input section of the column address buffer 2 but to the output section, that is, the input section of the column decoder 5. Except for this point, it is the same as the embodiment of FIG.

FIG. 3A shows a specific configuration example of the serial address counter 13 used in this example. This serial address counter is a shift register type counter having an equivalent circuit shown in FIG. 3 (b) and a clocked CMOS inverter as a symbol shown in FIG. 3 (c). Shows the first stage and the i-th stage. The conduction of the clocked CMOS inverter, which is a component of this counter,
As the clock for controlling non-conduction, the lowest address
The counter has a column address latch signal CLTC, ▲
The outputs of the lower address counters are respectively input to the counters of the other address orders.
By serially connecting such address counters, a serial address counter that generates an address for a predetermined number of bits, for example, one row, is configured. Cereal·
The address counters are reset transistors Q1, Q2, ...
And can be initialized by a reset signal CSET, ▲ ▼.

FIG. 4 is a timing chart showing the operation of the above serial address counter. The operation of the serial address counter will be described using this.
When ▼ falls and becomes active, the reset signal CSET
Are at "H" level, and ▲ ▼ is at "L" level, whereby the reset transistors Q1, Q2,... Of the serial address counter are turned off. Then, the row address is fetched by the drop of ▲, and after the elapse of time τ1, the column address is accepted when the latch signal CLTC of the column address becomes “H” level and ， ▼ becomes “L” level. Can be At this time, all the outputs A0s, A1s, A2s,... Of the serial address counter are set to “0”. After that, the signal CLTC is set to “H” level and ▲ ▼ is set to “L” by toggling ▲ ▼.
, A0s = 1, A1s = 0, A2s = 0,..., Then, when the latch signal CLTC goes to the “H” level and ▲ ▼ goes to the “L” level, A0s = 1, A1s = 1, A2s = 0,..., And are counted up by the toggle of CLTC, ▲ ▼.

Accordingly, the page mode is used by inputting the output of the serial address counter via a column address buffer as shown in FIG. 1 or directly to a column decoder as shown in FIG. A serial access mode can be realized.

According to this example, serial access can be performed without supplying an external column address in accordance with the column address strobe signal, thereby realizing a higher-speed serial access function than in the conventional page mode. Can be. Also, the number of bits for serial access is not limited as in the nibble mode.

Next, an example in which the present invention is applied to a DRAM having a pointer function will be described. Here, the pointer function is a so-called cueing function that enables serial access from an arbitrary address to a column address. Such a function is, for example, in an image memory, a dot in a horizontal direction.
This is useful for facilitating scrolling and the like.

FIG. 5 shows a serial address counter incorporated in such a DRAM. The overall configuration of the DRAM is the same as in FIG. 1 or FIG. Here, only the i-th stage is shown. The serial address counter is a so-called preset type counter, and includes a main counter 51 for sequentially generating a serial address, a slave counter 52 for latching data of the main counter 51 and controlling a next-stage main counter.
And a preset port 53 for presetting them to an external address.

FIG. 6 shows a clock generation circuit for generating a control clock CTi for the serial address counter. While the control clock signal ▲ ▼ entering the preset port 53 is at the “L” level, the first clock CT0 is not generated, and the control clock ▲ ▼ goes to the “H” level.
Latch signal CLTC generated in synchronization with the toggle of ▲ ▼
Clocks CT1, CT2,.

Next, the operation of the serial address counter of FIG. 5 will be described with reference to the timing chart of FIG. After the row address is fetched by the fall of the external control signal で, the latch signal CLTC goes to the “H” level at time t1 from the fall of ▼, and the reception of the column address is started. The latch signal CLTC falls to the “L” level again due to the drop of ▲, so that the column address is latched. In parallel with this, while the control signal ▲ ▼ until ▲ falls, the serial address counter responds to the external address by the data Aic, ▲ input to the preset port 53 while the control signal ▲ ▼ is at the “H” level. Preset. FIG. 7 shows a state in which the lowest address A0 is preset to "H" level and the next address A1 is preset to "L" level in the case of a 2-bit serial address counter. Thereafter, the latch signal ▲ ▼ operates in response to the toggle of ▲ ▼, whereby the clock CT0 becomes “H” level, and the next clock CT1 becomes “H” by this clock CT0 and the counter output S0s.
The clock enters the level, and so on. As a result, the serial address counter changes from the preset state (S0 = 1, S1 = 0) to S0 = 0, S1 = 1, then S0 = 1, S1
= 1.

The output of the preset type serial address counter is input to the column decoder via the column address buffer or directly to the column decoder in the same manner as in the previous embodiment, thereby realizing the serial access mode applying the page mode. Is done.

 According to this example, the same effect as the previous example can be obtained.

By the way, a DRAM generally has a built-in refresh counter for auto refresh as shown in FIG. 1 and FIG. Therefore, in practicing the present invention, it is conceivable to share a serial address counter and a refresh counter for serial access. In this case, the serial access operation is not performed continuously for n times but in the middle.
Since the operation may be performed between modes, a register for temporarily holding a refresh address is required.

FIG. 8 shows a schematic configuration of a counter for automatic refresh and serial access in a DRAM according to an embodiment of the present invention in consideration of such circumstances. Counter circuit 81
A refresh address register circuit 82 is provided in parallel with the above, so that data can be exchanged between them. The refresh address is always output through the refresh address register circuit 82, and the counter circuit 81 can preset the address latched by the refresh address register circuit 82. This makes it possible to interrupt the refresh cycle, execute the serial access mode, and then continue the interrupted refresh cycle.

By sharing the refresh counter and the serial address counter in this way, the chip area of the DARM can be effectively used.

[Effects of the Invention] As described above, according to the present invention, a DRAM capable of high-speed serial access mode operation can be obtained by incorporating a serial address counter in a chip. Moreover, since the serial address counter is shared by the counter in the serial access mode and the refresh counter in the refresh, the chip size can be prevented from increasing.

[Brief description of the drawings]

1 is a block diagram showing a configuration of a DRAM applied to the present invention, FIG. 2 is a block diagram showing a configuration of a DRAM of another example, and FIGS. 3 (a), (b) and (c) are built in the DRAM. Cereal
FIG. 4 shows an equivalent circuit of an address counter and a clocked CMOS inverter which is a component thereof. FIG. 4 is a timing chart for explaining the operation of the serial address counter. FIG. 5 is another serial address counter. FIG. 6 is an equivalent circuit diagram showing an example of the configuration of a clock generating circuit, FIG. 7 is a timing diagram for explaining the same operation, and FIG. 8 is an embodiment of the present invention. FIG. 9 is a block diagram showing a configuration example of a serial address counter shared with a refresh counter, FIG. 9 is a timing diagram showing a read cycle in a page mode of the DRAM, and FIG. FIG. 11 is a timing diagram showing a read cycle in nibble mode, and FIG. 12 is a timing diagram showing a write cycle. It is a timing diagram. 1 ... row address buffer, 2 ... column address buffer, 3, 4 ... clock generator, 5
...... column decoder, 6 ... row decoder, 7 ...
Memory cell array, 8: sense amplifier / I / O gate, 9
…… Input buffer, 10 …… Output buffer, 11 …… Substrate bias generation circuit, 12 …… Refresh counter, 13…
... Serial address counter.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-8588 (JP, A) JP-A-62-6482 (JP, A) JP-A-61-134989 (JP, A) 170994 (JP, A) JP-A-62-214577 (JP, A) JP-A-3-71484 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11C 11/407

Claims (5)

(57) [Claims] 1. A memory array in which a plurality of dynamic memory cells are arranged in rows and columns in a matrix, a row decoder for selecting a row in the memory array, and a column address for holding a column address. A buffer and a column address stored in the column address buffer.
A column decoder for selecting a column in the memory array according to an address; and a plurality of memory cells arranged in a selected row.
In a serial access mode in which at least two bits or more are successively accessed, the serial address is sequentially counted up according to a toggle operation of a column address strobe signal, and a continuous column address is generated to generate the column address.
A serial address counter that supplies an address buffer, counts up a refresh address at the time of refreshing the memory array, and supplies the refresh address to the row address buffer; and a register that holds the refresh address. A dynamic semiconductor memory device, wherein the serial address counter is preset by a refresh address held in the register at the time of refresh. 2. A memory array in which a plurality of dynamic memory cells are arranged in rows and columns in a matrix, a row decoder for selecting a row in the memory array, and a memory in the memory array according to a column address. And a column decoder for selecting a column of a plurality of memory cells arranged in a selected row.
In a serial access mode in which at least two bits or more are successively accessed, the serial address is sequentially counted up according to a toggle operation of a column address strobe signal, and a continuous column address is generated to generate the column address.
A serial address counter that supplies a refresh address to the row decoder when the memory array is refreshed and supplies a refresh address to the row decoder; and a register that holds the refresh address. A dynamic semiconductor memory device, wherein an address counter is preset by a refresh address held in the register at the time of refresh. 3. A memory array in which a plurality of dynamic memory cells are arranged in rows and columns in a matrix, a row decoder for selecting a row in the memory array, and a column address for holding a column address. A buffer and a column address stored in the column address buffer.
A column decoder for selecting a column in the memory array according to an address; and a plurality of memory cells arranged in a selected row.
In a serial access mode in which at least two bits or more are successively accessed, the serial address is sequentially counted up according to a toggle operation of a column address strobe signal, and a continuous column address is generated to generate the column address.
A serial address counter which supplies an address buffer, counts up a refresh address at the time of refreshing the memory array, and supplies the refresh address to the row address buffer. . 4. A memory array in which a plurality of dynamic memory cells are arranged in rows and columns in a matrix, a row decoder for selecting a row in the memory array, and a memory in the memory array according to a column address. And a column decoder for selecting a column of a plurality of memory cells arranged in a selected row.
In a serial access mode in which at least two bits or more are successively accessed, the serial address is sequentially counted up according to a toggle operation of a column address strobe signal, and a continuous column address is generated to generate the column address.
And a serial address counter that supplies a refresh address to the row decoder when the memory array is refreshed and supplies the refresh address to the row decoder. 5. The serial address counter according to claim 1, wherein said serial address counter is preset by an external column address in order to realize serial access from an arbitrary column address. Dynamic semiconductor memory device.