JP2931363B2 - Display control device and display control method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a display control device and a display control method,
More specifically, the present invention relates to a display control device and a display control method for a display device including a display element capable of holding a display state updated by application of an electric field, for example, using a ferroelectric liquid crystal as an operation medium for display update. .

[Related Art] Generally, a display device is connected to an information processing system or the like as information display means that performs a visual display function of information. A CRT is widely used as such a display device, and FIG. 9 shows an example of a display control device for a CRT connected to such an information processing device.

In the figure, 1 is an address bus driver, 2 is a control bus driver, 3 is a data bus driver,
Each of them is connected to a system bus 4 for signal connection between devices constituting the information processing system. 5 is a video memory for storing display data transferred via the data bus driver 3, 6 is a driver for transferring data between the display control device and the CRT, and 7 is a CRT.

The video memory 5 is configured by a dual-port DRAM (dynamic RAM), and display data is directly written. The display data written in the video memory 5 is sequentially read out by a CRTC (CRT controller) 8 and displayed on a CRT 7.

That is, when writing the display data, the CPU of the information processing system (not shown) accesses the address of the video memory 5 corresponding to the display area of the CRT 7. First, the access request signal is given to the memory controller 9 via the control bus driver 2, and this signal is sent to the CR.
It receives arbitration with a data transfer request signal or refresh request signal provided from TC8. Accordingly, when the CPU accesses the memory, an address selection signal is supplied from the memory controller 9 to the address selector 10, and an access address for writing data from the CPU is transferred to the video memory 5 via the address driver 1 and the address selector 10. Given to. Accordingly, a DRAM control signal from the memory controller 9 and display data via the data bus driver 3 are given to the video memory 5. Thus, the display data is written to the video memory 5.

On the other hand, the display on the CRT 7 is such that the CRTC 8 supplies a synchronization signal to the driver 6, and in accordance with the synchronization signal, the CRTC 8 supplies a data transfer request signal to the memory controller 9 and a data transfer address to the address selector 10. Is executed by

First, when the data transfer request signal is arbitrated by the memory controller 9 and an address selection signal is given from the memory controller 9 to the address selector 10 in response to the arbitration, the data transfer address from the CRTC 8 is transmitted to the video via the address selector 10. It is provided to the memory 5. The video memory 5 is supplied with a DRAM control signal from the memory controller 9 to execute a data transfer cycle. This data transfer cycle refers to the video memory 5
Is transferred to the shift register in the video memory 5 in units of lines (corresponding to the raster of the display screen), and one to several lines of data can be transferred to the shift register in one data transfer cycle. .

Then, the display data transferred to the shift register is
In accordance with the serial port control signal from the CRTC 8 applied to the video memory 5, the data is sequentially read from the shift register, output to the CRT 7, and displayed. The reading of display data from the video memory 5 and the accompanying display are performed line by line from the upper part to the lower part corresponding to the display area, and in one line, in a certain order from the left end to the right end. This is performed by a so-called full refresh operation.

As described above, in the case of the CRT display control, the CPU write operation to the video memory 5 and the CRT controller 8
The operation of reading and displaying the display data from the video memory 5 is independently executed.

In the case of the display control device for a CRT as described above, the writing of display data to the video memory 5 for changing display information and the like, and the operation of reading the display data from the video memory 5 and displaying the data are independent. Therefore, the program of the information processing system does not need to consider display timing and the like at all, and has an advantage that desired display data can be written at an arbitrary timing.

On the other hand, a CRT, in particular, requires a certain length of the display screen in the thickness direction, and therefore has a large overall volume, making it difficult to reduce the size of the entire display device. This also impairs the degree of freedom in using the information processing system using such a CRT as a display, that is, the degree of freedom in installation location, portability, and the like.

As a supplement to this point, a liquid crystal display (hereinafter, referred to as LCD) can be used. That is, according to the LCD,
The whole display device can be reduced in size (especially thinner). Among such LCDs, there is a display (hereinafter, referred to as FLCD: FLC display) using a liquid crystal cell of the above-described ferroelectric liquid crystal (hereinafter, referred to as FLC: Ferroelectric Liquid Crystal). The problem is that the liquid crystal cell has a display state preserving property with respect to application of an electric field. Therefore, when driving an FLCD, unlike a CRT or other liquid crystal display, there is time margin in the cycle of continuous refresh driving of the display screen, and apart from the continuous refresh driving, Partial rewrite driving that updates the display state of only the part corresponding to the change on the display screen becomes possible. Therefore, such an FLCD can be a large-screen display as compared with other liquid crystal displays.

Here, the FLCD has a sufficiently thin liquid crystal cell, and the molecules of the elongated FLC in the liquid crystal cell are oriented in a first stable state or a second stable state depending on the direction of application of the electric field, and the electric field is reduced. Even if it is cut, each alignment state is maintained. Due to such FLC molecules and bistability, FLCDs have memory properties. Details of such FLC and FLCD are described in, for example, Japanese Patent Application
2-76357.

[Problem to be Solved by the Invention] However, the FLCD having the above advantages is replaced with the above-mentioned CR.
When used as a display device of an information processing system under the same display control as T, the display update operation of the FLC is relatively slow, so the display must be immediately rewritten, for example, by cursor, character input, scrolling, etc. In some cases, it is not possible to follow a change in display information that must be performed.

On the other hand, in order to perform this processing by utilizing the fact that partial rewriting, which is one of the features of FLCD, is possible, the information processing system must provide information for identifying this processing. Although there is a configuration for performing the above, in order to realize the above-described partial rewriting drive on the display screen, a significant change in the control program in the information processing system has been required.

The present invention has been made based on the above-described viewpoint, and does not significantly change the software of an information processing system using a display device such as an FLC display capable of partially changing the display state of a pixel without significantly changing the operating temperature. It is an object of the present invention to provide a display control device and a method capable of performing optimal control in various cases while effectively utilizing the storability in an FLC display or the like according to environmental conditions or display contents and the like. I do.

Means for Solving the Problems In order to achieve the above object, the present invention provides a display device capable of partially changing the display state of a pixel (in the following embodiments,
In a display control device (also the CPU 11 and the FLCD interface 27) of the FLCD 26, refresh scanning means (address counter 3) for sequentially scanning scan lines constituting the display device at predetermined intervals.
8, a synchronization control circuit 39, a memory controller 40); a partial scanning unit (generation address control unit 70, memory control 40) for designating and scanning an arbitrary scan line of the scan lines constituting the display device; Setting means for setting a ratio between scanning by the refresh scanning means and scanning by the partial scanning means based on at least one of an environmental condition of the device and a type of display data displayed on the display device (ratio / cycle setting) Unit 53), and switching means (synchronous control circuit 39, memory controller 40) for switching between the refresh scanning means and the partial scanning means based on the ratio set by the setting means. .

The present invention also provides a display control method for a display device capable of partially changing a display state of a pixel, wherein the display control method is based on at least one of an environmental condition of the display device and a type of display data displayed on the display device. A scan by refresh scanning means for sequentially scanning scan lines constituting the display device at predetermined intervals; and a scan by partial scanning means for designating and scanning an arbitrary scan line of the scan lines constituting the display device. A ratio is set, and the refresh scanning unit and the partial scanning unit are switched based on the set ratio.

[Operation] According to the present invention, a refresh scan for sequentially scanning scan lines constituting a display screen at predetermined intervals and a partial scan (partial scan) for designating and scanning an arbitrary scan line of scan lines constituting a display screen Rewriting cycle), the ratio between the refresh scan and the partial scan is appropriately variably set based on at least one of the environmental conditions and the type of display data, and both are set based on the set ratio. , The optimal control can be performed in various cases while effectively utilizing the storability of the FLC display or the like in accordance with environmental conditions such as operating temperature or display contents. .

Examples Hereinafter, the present invention will be described in detail with reference to the drawings.

First Embodiment FIG. 1 is a block diagram of an entire information processing system incorporating a display control device according to an embodiment of the present invention.

In the figure, reference numeral 11 denotes a CP that controls the entire information processing system.
U and 12 are system buses consisting of an address bus, control bus, and data bus, and 13 is for storing programs,
The main memory 14 is used as a work area. A direct memory access controller (DMA) 14 transfers data between the memory and I / O devices without the intervention of the CPU 11.
AC), 15 is L for Ethernet (by XEROX)
LAN interface with AN (local network) 16, I / O device 17 for connecting I / O devices consisting of ROM, SRAM, RS232C interface, etc., 18 hard disk device, 19 floppy disk device, 20 Is a disk interface for the hard disk device 18 and the floppy disk device 19; 21A is a high-resolution printer such as a laser beam printer, an ink jet printer;
B is a scanner as an image reading device, 22 is an interface for the printer 21A and the scanner 21B, 23 is a keyboard for inputting characters and other characters such as numbers, etc., 24 is a mouse as a pointing device, 25
Is an interface for keyboard 23 and mouse 24,
Reference numeral 26 denotes an FLCD (FLC display) which can be configured using a display disclosed by the present applicant in, for example, JP-A-63-243993, and 27 denotes an FLCD interface for the FLCD 26.

In the information processing system including the various devices described above connected, the user of the system generally performs an operation while corresponding to various information displayed on the display screen of the FLCD 26. That is, external devices connected to the LAN 16, the I / O 17, the hard disk 18, the floppy disk 19, the scanner 21B, the keyboard 23, the characters supplied from the mouse 24, the image information, etc. Operation information related to the system operation is displayed on the display screen of the FLCD 26, and the user performs information editing and instructs the system while viewing this display. Here, each of the above-mentioned various devices constitutes a display information supply unit for the FLCD 26.

FIG. 2 shows an FLCD as an embodiment of the display control device of the present invention.
6 is a block diagram illustrating a configuration example of an interface 27. FIG.

In the figure, 31 is an address bus driver, 32 is a control bus driver, and 33 and 43 are data bus drivers. Address data from the CPU 11 is supplied from the address bus driver 31 to one input unit of the memory controller 40 and the address selector 35, and the memory 36 or the FIFO memory 36 is switched by the first switch S1.
It is selectively given to 37 and stored. That is, these memories 36 and 37 (hereinafter, FIFO (A) and FI
FO (B)) is a FIFO (First In First Out) memory for reading data in the order of writing, and the address data written in these memories 36 and 37 is
The data is selectively read by switching the second switch S2.

The address data read from these memories 36 or 37 and the address data from an address counter 38 described later are selectively supplied to the other input section of the address selector 35 by switching a third switch S3. The address counter 38 generates address data for refreshing the entire screen line by line.
The generation timing of the address data is determined by the synchronization control circuit 39.
Is controlled by The synchronization control circuit 39 also generates a switching control signal for the switches S1, S2, and S3 and a data transfer request signal to the memory controller 40 described later.

The control signal from the CPU 11 is given from the control bus driver 32 to the memory controller 40, and the memory controller 40 generates a control signal for the address selector 35 and a control signal for the video memory 41 described later. The address selector 35 is a memory controller
Based on the control signal from 40, the address selector 35
Select one of the two address data supplied to the input section and supplies it to the video memory 41.

The video memory 41 stores display data,
It is composed of a dual-port DRAM (dynamic RAM), and writes and reads out display data via the data bus driver 33. The display data written to the video memory 41 is transmitted to the FLCD via the driver receiver 42.
Transferred to 26 and displayed. In addition, the driver receiver 42 supplies a synchronization signal from the FLCD 26 to the synchronization control circuit 39.

Through the data bus driver 43, data for setting a ratio between partial rewriting and refresh driving, which will be described later, according to the type of image and the like is given to the control register 51.

The FLC panel 26A of the FLCD 26 is provided with a temperature sensor 26B for detecting its temperature, and the temperature control circuit 26C uses the FLC using a heater or the like based on the detected temperature.
The temperature of the panel 26A is controlled. The temperature control circuit 26C
Sets a flag value in the flag register 26E based on the detected temperature with reference to a table described later with reference to FIG. At this time, the controller that executes the control of FLCD26
26D switches the table referred to above according to the state of a temperature table changeover switch 26S provided on, for example, an outer case of the FLCD 26 and operable by a user. By providing a table according to this switch, the number of flags can be reduced, and the hardware configuration can be simplified. Note that a volume may be provided instead of the above switch, and a plurality of tables may be provided according to the value of the volume.

53 is a ratio / cycle setting unit, which is a control register
In accordance with the information such as the image type stored in 51 and the information on the detected temperature (temperature flag), the driving conditions of the FLC panel 26A (the ratio of the refresh cycle and the partial rewrite cycle described later and their repetition cycle) are set. A form having a memory storing a table for selection can be adopted. As a mode, a ROM can be used if it is not premised on rewriting table contents from the system side, and a RAM can be used if it is premised. Then, the operation of the synchronization control circuit 39 is controlled according to the table, and FL is controlled.
The C panel 26A can be driven appropriately.

In the above configuration, when the CPU 11 changes the display, the video memory 41 corresponding to the rewriting of the desired data is used.
Is given to the memory controller 40 via the address bus driver 31, and arbitration is performed between the memory access request signal of the CPU 11 and the data transfer request signal from the synchronization control circuit 39. When the CPU access side obtains the right, the memory controller 40
Switches the address selector 35 to select the address accessed by the CPU as the address to be given to the memory 41. At the same time, a control signal for the video memory 41 is generated from the memory controller 40, and data is read and written via the data bus driver 33. At this time, CP
The U access address is stored in the FIFO (A) 36 via the switch S1.
Alternatively, the data is stored in the FIFO (B) 37 and is used when transferring display data described later. As described above, the data access method in the display viewed from the CPU 11 is not different at all from the case of the above-described CRT.

When data is read from the video memory 41 and transferred to the FLCD 26, the synchronization control circuit 39 sends the data to the memory controller.
Data transfer request to 40, video memory
Address counter 38 or FI as address for 41
The FO side address is selected by the address selector 35, and a control signal for data transfer is generated from the memory controller 40, so that the data of the corresponding address is transferred from the memory cell to the shift register, and the control signal of the serial port is used. Output to the driver 42.

In the synchronization control circuit 39, the horizontal synchronization signal HSYN
Based on C, a timing is generated to alternately generate a cycle in which the screen is entirely refreshed line by line in units of a plurality of lines and a partial rewrite cycle in which the line accessed by the CPU 11 is rewritten. here,
The full refresh cycle is to sequentially rewrite downward from the top line (top line) on the display screen, and to the bottom line, return to the top line again and repeat rewriting. Things. The access line rewrite cycle (partial rewrite cycle) is to rewrite the line accessed by the CPU 11 within a predetermined time immediately before the cycle.

As described above, in this example, basically, the operation of sequentially refreshing the entire screen of the FLC display 26 and the operation of rewriting the line accessed by the CPU 11 to change the display content are time-divisionally performed. In addition, the repetitive synchronization of these operations and the time ratio of those operations within one cycle can be set according to the type of image data, temperature conditions, and the like.

First, a basic operation of the present example in which the refresh operation and the line rewrite operation are alternately performed in a time-division manner will be described with reference to FIG. Here, an example is shown in which a refresh cycle is performed in units of four lines and a rewrite cycle of an access line is performed in units of three lines.

In FIG. 3, REE / ▲ ▼ is a timing at which a full refresh cycle and an access line rewrite cycle are alternately generated. When “1”, the full refresh cycle is performed, and when “0”, the access line is rewritten. Indicates a rewrite cycle. Further, T _a time of the entire surface of the refresh cycle, T _b represents the time of rewriting cycles access lines. In this example, T _a : T _b
= 4: 3, but an optimal value can be selected depending on the required refresh rate and the like. That is, by increasing the proportion of T _a can raise the refresh rate, it is possible to improve the responsiveness of the partial changes by increasing the proportion of T _b. This aspect will be described later.

To explain the states of the FIFO (A) 36 and the FIFO (B) 37, when the switch S1 is connected to the FIFO (A) 36 side (state
A / = 1), the address of the line accessed by the CPU 11 is F
It is sampled and stored in the IFO (A) 36. On the other hand, when the switch S1 is connected to the FIFO (B) 37 side (A / =
0), line address accessed by CPU11 is FIFO
(B) Stored in 37. Switch S2 is FIFO (A)
When connected to the 36 side (A / = 1), the address stored in the FIFO (A) 36 is output, and the switch S2 switches the FIFO (B) 37
Side (A / = 0), the address stored in the FIFO (B) 37 is output.

When one refresh of the entire screen is completed and the FLCD 26 outputs the vertical synchronizing signal VSYNC or when the carry occurs in the address counter 38, the address counter 38 is cleared and the line output in the next full refresh cycle is Returning to the 0th line, the synchronization control circuit 39
"1", "2",
Counts up sequentially to “3”. During this period, when the addresses of the lines L1, L2, L3 are accessed by the CPU 11, the switch S1 is connected to the FIFO (A) 36, so that L1, L2, L3
Is stored here, and then switch S2 is set to FIFO
(A) At the time of connection to 36, the addresses of L1, L2, L3 are output from here, and L1, L2, L3 are selected as output lines.
Here, the switching signal of the switch S3 is given as REF / ▲ ▼ from the synchronization control circuit 39. In the line access cycle, FIFO (A) and FIFO (A) are used as output line addresses.
It is switched to (B) side.

At this time, since the switch S1 is connected to the FIFO (B) 37 side, the access address is stored in the FIFO (B) 37 side. When REF / ▲ ▼ becomes “1”, switch S3
Is switched to the address counter 38 side, and the refresh operation is performed from the line following the previous cycle. In FIG. 3, the lines "4", "5", "6", and "7", which are the continuation of the previous cycle, are output after the line L3 is output. In the same manner as described above, the above operation is repeated, but the reason for preparing two FIFOs is to sample memory-accessed addresses on one side and to output the sampled addresses on the other side simultaneously and efficiently. That's why. That is, during the address sampling period, the other FI
From the start of the output of the FO access line to the end of the full refresh cycle.After the end of the full refresh cycle, the rewrite cycle of the access line that outputs the address sampled in the immediately preceding sampling period is started, and at the same time, the address of the other FIFO is read. The sampling period will be started.

As described above, in the basic operation of this example, the refresh cycle and the line rewriting cycle are alternately repeated, and in FIG. 3, the repetition cycle is set to 7 lines as one unit and T _a : T
_b = 4: has been described as 3, in this example further type of data being environmental conditions and displays such as temperature, or even T _a and the refresh rate or the like which is required according to the difference of the display device material FLCD T The ratio with _b can be changed.
That, T _a (corresponding to the line number M within one refresh cycle, i.e. T _a = M × (period of HSYNC)) ratio of can be improved refresh rate if the large, for example, low temperature or the like FLC device A good display state can be obtained even when the response is low or when displaying an image image. Conversely, the ratio of T _b (corresponding to the number N of lines in one partial rewrite cycle, ie, T _b = N × (HSYN
If the period of C is increased, the responsiveness of a partial display change can be increased, and it is possible to cope with a case where the refresh rate does not need to be high, such as at a high temperature or when displaying characters such as characters. .

Further, in the present embodiment, the number of lines in the repetition period can also be set, so that the refresh cycle and the rate of partial rewriting can be changed more finely, and more fine optimization can be achieved. For example, if it is necessary to give priority to the refresh rate, or if you want to give it priority, set the number of lines in the repetition cycle to 40.
If T _a : T _b = 4: 1, the entire surface can be refreshed for 32 lines and the access lines can be rewritten for 8 lines. If partial rewriting can be prioritized or prioritized, the number of lines in the repetition cycle is set to 10 and T _a : T _b
Assuming that 3: 2, the access line can be rewritten four times by performing a full refresh for six lines.

FIG. 4 shows an example of the structure of data processed by the system shown in FIG. One unit of data is composed of a management area CA and a data area D, and data composed of character strings such as characters and numerals, and data such as line drawings, natural pictures, and photographs are developed in the data area. The management area CA is provided with an area CTRL of management information (for example, information such as a data size and a pitch in the case of character data) about the expanded data and an area HA of header information indicating an image type.

When the user inputs a document or the like using the keyboard 23, information indicating that the data is a character string or the like is provided in the area HA, and management information for editing or the like is stored in the area CTRL. Will be added. Scanner 21B
When the input is performed by using, information of the mode (character mode for reading a character string, photo mode for reading a photo, photo fine mode for clearly reading a photo, etc.) set at the time of the reading is used. In the header information area HA,
Other management information is expanded in the area CTRL. Then, the data to which the management area CA set as described above is added is registered in a hard disk or a floppy disk in the form of a file.

In this example, when displaying an image input from the scanner 21B or the like, a character input from the keyboard 23 or the like, or a file read from a hard disk or a proppy disk, information indicating an image type is extracted from the header information area, and As header information H in the control register 51 of FIG. Further, the user can rewrite the contents of the header information area HA, and the user can select the display quality.

FIG. 5 is a conceptual diagram showing a temperature flag table included in the temperature control circuit 26C shown in FIG. 2. As is apparent from FIG. 5, four types of flags each composed of two bits include:
The selection is made in accordance with the temperature detected by the temperature sensor 26B and the state of the switch 26S, and is set in the flag register 26E. The switch 26S is operated by the user as described above.
The state of 26S can be switched to A or B.

Figure 6 is an image type (character, line drawing, a natural image, photographs, photos Fine etc.) optimal allocation repetition period and refresh cycles / partial rewrite cycle in accordance with the header information H and the temperature information indicating the T _H (ratio) Setting section for selecting
53 shows a configuration example. As shown, the setting unit 53, image type-specific header information H1, H2, ..., HY and, information T _H 1 corresponding to the temperature _{flag, T H 2, ... T H} X (4 kinds in this embodiment ) (The number of lines in one refresh cycle)
And N value (number of lines in one partial rewrite cycle)
Is stored in the table.

Thus, any display control operation in accordance with the header information H and the temperature information T _H at that time during the (Figure 8) M
The value (N) is read out, and a counter (not shown) in the synchronization control circuit 39 counts the synchronization signal HSYNC accordingly,
Outputs EF / ▲ ▼. And such M value and N
Repetition period (= (M + N) × (HS
YNC cycle)) and the ratio (T _a : T _b = M: N).

7 (A) to 7 (C) relate to one embodiment of the present invention, respectively. FIG. 7 is a flowchart showing a control procedure by the CPU 11 in response to a user operation in the information processing system shown in FIG. Figure (D) shows the FLCD following the above control procedure.
6 is a flowchart showing an operation procedure of the interface 27.

FIG. 7 (A) shows an image input mode by the scanner 21B and a control procedure when this input data is displayed by the FLCD 26. In step S501, when a scanner icon on the display screen of the FLCD 26 is selected by, for example, operating the mouse 24 by the user, a window for displaying an input image at a predetermined position on the display screen is opened in step S502. Further, according to the image input by the scanner 21B in step S503, the user inputs characters, photos,
When the input mode is set from the photo fine, in step S504, the header information as described above with reference to FIG. 4 is selected as a default from a plurality of predetermined header values and is added thereto. At the same time, in step S505, this header information is set in the control register 51 shown in FIG.

Thereafter, in step S506, the input operation of the scanner 21B is started, and accordingly, in step S507, the input image data is temporarily stored in the main memory 13 in order to adjust the resolution of the scanner 21B and the FLCD 26.
This expands the image data in the video memory 51 and displays the image data.

Next, in step S509, it is determined whether or not the user has changed the display state by operating, for example, a control symbol displayed on the display screen using a mouse or the like to change the display image quality. In this case, another header value is selected from the plurality of header values according to this change in step S510, and this header information is set in the control register 51 in step S511. Step S509
If it is determined that the display state has not been changed, the process ends.

FIG. 7B shows a control procedure in a character input mode compatible with a word processor. For example, when this processing is started by a predetermined key operation on the keyboard 23, the step
In S521, the input paper is displayed at a predetermined position on the display screen. Accordingly, in step S522, a predetermined header value is selected from the plurality of header values by default and added to a predetermined area of the memory. Further, in step S523, the header value is set in the control register 51.

Thereafter, when a key input is performed in step S524, the key input data is expanded and displayed in the video memory 41 in step S525.

Next, in step S526, it is determined whether or not the display state has been changed by the user in the same manner as the control means of FIG. 7A. If the display state has been changed, the header value is changed in step S527. Then, the process returns to step S523 to set a header value in the control register 51 for display change. If the display state has not been changed, step S528
Then, it is determined whether or not the key input has been completed. If the key input has been completed, the process ends, and if not, the process returns to step S524.

FIG. 7C shows a control procedure of a file display mode for displaying a file stored in the hard disk 18 or the floppy disk 19.

When this process is started, the header information of the file is read in step S531, and the header information added to the file is set in the control register 51 in step S532. Subsequently, in step S533, the data in the file is stored in the memory 13 in order to adjust the resolution as described above, and then, in step S534, these data are developed and displayed in the video memory 41. Further, in steps S535 to S537, steps S509 to S511 in FIG.
A process similar to the process of is performed.

FIG. 7D shows the operation of the FLCD interface according to each control procedure shown in FIGS. 7A to 7C.

That is, in the FLCD interface 27, step S5
Or there is a change in the contents of the control register 51 at 41, if there is a change in temperature, receives the H values and / or T _H values had this change in step S542, M at step S543, The N value is reset. Therefore, step S
At 544, the operation of the synchronization control circuit 39 according to the M and N values is performed.

FIG. 8 shows an example of a display operation procedure performed by each unit of the apparatus shown in FIG.

First, in step S201, the initial state of the switches S1 and S2 is set. Here, the switch S1 is set to the FIFO (A) 36 side, and the switch S2 is set to the FIFO (B) 37 side. In step S202, the address counter 38 is cleared, and the refresh address is set to an initial value, for example, “0”. Next, in step S203, REF / ▲ is set to “1” so that the entire refresh cycle is performed. Also, a counter for counting the number of transfer lines in one refresh or partial rewrite cycle (here, one refresh cycle) is cleared, and the counter value LN is set to "0".

Next, in step S205, it is determined whether or not the period up to the last line is completed and carry is generated in the address counter (retrace period). If the period is during the period, the process returns to step S200A. If not, wait for HSYNC to come in step S206. When HSYNC arrives, the data on the line indicated by the refresh line address is
Transfer to 26. In step S208, it is determined whether or not the number M of lines to be transferred in one full refresh cycle (set by the setting unit 53) has been completed. If LN is smaller than M, the process proceeds to step S209 and the address counter 38 is counted up, and LN is incremented by +1 in step S210, and the process returns to step S206. This is repeated until the M lines are transferred. In the example shown in FIG.
Since it is 4, the loop of steps S206 to S210 is repeated four times.

When the transfer of the M line is completed, at step S211 REF /
▲ ▼ is set to “0” so that the access line rewrite cycle is performed. Also, switch S1 and switch
The connection state with S2 is reversed, and the roles of FIFO address sampling and line address output are reversed.
Next, in step S212, the counter value LN is set to "0" again in order to count the number of transfer lines during the access line rewrite cycle. In step S213, FIFO (A) 36 or
The sampled address is read from one of the FIFOs (B) 37.

In step S215, the process waits for the HSYNC to be received. If the HSYNC is received, the data of the line at the address read out earlier is transferred to the FLCD 26 in step S216. Next, in step S217, it is determined whether or not the transfer of the lines and N lines (set by the setting unit 53) has been completed. That is, if LN is smaller than N, the process proceeds to step S218, and LN is incremented by +1 to step S213.
This is repeated until the processing for N lines is completed. If N = 4, the loop of steps S213 to S218 is repeated four times. When the N lines are completed, the process returns to step S203 to execute the entire refresh cycle again.

As described above, the contents of the video memory 41 are displayed by repeating the full refresh cycle from step S203 to S208 and the access line rewriting cycle from step S211 to S217, and a carry occurs in the address counter 38. This is performed by returning the line of the entire refresh cycle to the head and initializing the signal.
On the other hand, the CPU 11 may read and write data from the video memory 41 independently of the display operation in order to obtain the displayed content.

As described above, reading data from the video memory 41 and transferring it to the FLCD 26 does not require command interpretation. Not only can it be configured with a relatively simple circuit, but also a graphic processor can be provided to interpret commands. This can be realized at lower cost than performing display control, and the performance can be improved while reducing the cost of the entire system.

(Others) Note that the present invention is not limited to the above-described embodiments, and it is needless to say that appropriate modifications can be made without departing from the spirit of the present invention.

For example, within the range of the number of partial rewrite lines set as in the above example, the actual number P of partial rewrite lines performed between refresh cycles is adjusted according to the number of lines accessed by the CPU 11 and the line access state. You may make it. According to this, by adjusting the dynamic T _b time according to the number of lines CPU11 has accessed, for example, eliminating waste line rewriting cycle when the CPU11 infrequently accessed, so as to improve the refresh rate It is possible to dynamically optimize the relationship between the following performance and the refresh rate.

In the above example, the repetition period and the ratio of the refresh cycle / partial rewrite cycle are set during the operation period based on the temperature information and the image type. However, the timing of the setting can be appropriately determined. It may be performed during the line period. Further, not only the temperature information but also other environmental conditions may be considered. If sufficient, the above setting may be performed based on one of the environmental condition such as temperature information and the setting condition of the image type.

[Effects of the Invention] As described above, according to the present invention, a refresh scan for sequentially scanning scan lines constituting a display screen at predetermined intervals and an arbitrary scan line of the scan lines constituting the display screen are designated. And a partial scan (partial rewrite cycle) in which the ratio between the refresh scan and the partial scan is appropriately variably set based on at least one of the environmental conditions and the type of display data. Since both are appropriately switched based on the setting and the ratio, according to the environmental conditions such as the operating temperature or the display contents, etc., the optimal use in various cases is achieved while effectively utilizing the storability of the FLC display and the like. Control can be performed.

Therefore, changes in environmental conditions,
The display on the screen can be made to follow the movement of the figure and the cursor with high responsiveness, and a good display utilizing the characteristics of the FLC can be obtained. In addition, compatibility between CRT and FLC from the viewpoint of the system is maintained.
In addition, since it is realized with a simple circuit configuration, it is possible to perform inexpensive and high-speed display control.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing apparatus incorporating a display control device according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of an FLCD interface as an embodiment of the present invention. FIG. 4 is a timing chart for explaining the basic operation of the FLCD interface shown in FIG. 2, FIG. 4 is a block diagram showing an example of the structure of data processed by the information processing system shown in FIG. 1, and FIG. FIG. 6 is a conceptual diagram showing a configuration example of a setting unit shown in FIG. 2, and FIG. 7 is control by a CPU of the information processing system shown in FIG. 8 is a flowchart showing an example of a display operation procedure performed by each unit of the apparatus shown in FIG. 2, and FIG. 9 is a block diagram showing a configuration of a conventional CRT interface. FIG. 11 ... CPU, 12 ... System bus, 13 ... Main memory, 14 ... DMA controller, 15 ... LAN interface, 16 ... LAN, 17 ... I / O device, 18 ... Hard disk device, 19 ... ... Floppy disk drive, 20 ... Disk interface, 21A ... Printer, 21B ... Scanner, 22 ... Printer interface, 23 ... Keyboard, 24 ... Mouse, 25 ... Key interface, 26 ... FLCD (FLC display) ), 26A ... panel, 26B ... temperature sensor, 26C ... temperature control circuit, 26D ... controller, 26E ... flag register, 26S ... changeover switch, 27 ... FLCD interface, 31 ... address driver, 32 ... Control bus driver, 33, 43 ... Data bus driver, 35 ... Address selector, 36 ... FIFO (A) memory, 37 ... FIFO (B) memory, 38 ... Address counter, 39 ... Synchronous control circuit, 40 ... Memory controller, 41 ... Video memory, 42 ... Driver receiver, S1, S2, S3 ... Switch, 51 ... Control register, 53 ... Ratio / period Setting section.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-61-149933 (JP, A) JP-A-63-65425 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G02F 1/133 G09G 3/36 G09G 3/20 H04N 5/66

Claims (6)

(57) [Claims] 1. A display control device for a display device capable of partially changing a display state of a pixel, comprising: refresh scanning means for sequentially scanning scanning lines constituting the display device at predetermined intervals; A partial scanning unit for designating an arbitrary scanning line of the scanning lines to be scanned, and the refresh scanning unit based on at least one of an environmental condition of the display device and a type of display data displayed on the display device. Setting means for setting a ratio between scanning and scanning by the partial scanning means, and switching means for switching between the refresh scanning means and the partial scanning means based on the ratio set by the setting means. Characteristic display control device. 2. The display control device according to claim 1, wherein said environmental condition is a temperature condition. 3. The display control device according to claim 1, wherein said ratio is the number of scanning lines. 4. A display control method for a display device capable of partially changing a display state of a pixel, comprising: at least one of an environmental condition of the display device and a type of display data displayed on the display device. The ratio of the scanning by the refresh scanning means for sequentially scanning the scanning lines constituting the display device at predetermined intervals and the scanning by the partial scanning means for designating and scanning an arbitrary scanning line of the scanning lines constituting the display device And switching between the refresh scanning unit and the partial scanning unit based on the set ratio. 5. The display control method according to claim 4, wherein said environmental condition is a temperature condition. 6. The display control method according to claim 4, wherein said ratio is the number of scanning lines.