JP3229341B2 - Display control device and display control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device and a display control method, and more particularly, to a display control device, for example, which uses a ferroelectric liquid crystal as an operating medium for updating a display and maintains an updated display state by applying an electric field. The present invention relates to a display control device and a display control method for a display device having a possible display element.

[0002]

2. Description of the Related Art In general, a display device is used in an information processing system or the like as information display means for performing a visual expression function of information, and a CRT display device is widely known as such a display device. .

In the display control of the CRT display device, the writing operation of the system side CPU to the video memory as the display data buffer, and the reading and display operations of the display data from the video memory by the CRT controller, for example, are executed independently. You.

In the display control of the CRT as described above, the operation of writing display data to a video memory for changing display information and the operation of reading the display data from the video memory and displaying are independent. The program on the information processing system side does not need to consider display timing and the like at all, and has an advantage that desired display data can be written at an arbitrary timing.

On the other hand, the CRT, in particular, requires a certain length in the thickness direction of the display screen, so that the volume of the CRT as a whole increases, and it is difficult to reduce the size of the entire display device.
This also impairs the degree of freedom in using such an information processing system using a CRT as a display, that is, the degree of freedom in installation location, portability, and the like.

A liquid crystal display (hereinafter, referred to as LCD) can be used as a display device to compensate for this. That is, according to the LCD, it is possible to reduce the size (particularly, the thickness) of the entire display device. Such LCDs include a ferroelectric liquid crystal (hereinafter, FLC: Ferroelectric Liquid Crystal).
(Hereinafter, referred to as an FLCD: FLC display) using a liquid crystal cell. One of the features of the display is that the liquid crystal cell has a display state preserving property when an electric field is applied. That is, in the FLCD, the liquid crystal cell is sufficiently thin, and the elongated FLC molecules therein are oriented in the first stable state or the second stable state depending on the direction of application of the electric field, and the electric field is removed. However, the respective alignment states are maintained. Due to such bistability of FLC molecules, FLCDs have memory properties. Details of such FLC and FLCD are described, for example, in Japanese Patent Application No. 62-76357. Although the FLCD has the above-mentioned memory characteristics, the display update operation of the FLC is relatively slow, so that the display, such as cursor movement, character input, scrolling, etc., whose display must be rewritten immediately, is required. It may not be possible to follow changes in information.

An FLCD having such contradictory characteristics is:
To derive from or supplement these properties,
Various driving modes are possible for the display. That is, as with the CRT and other liquid crystal displays, the refresh cycle in which the scanning lines on the display screen are sequentially and continuously driven has a relatively long margin in the drive cycle. In addition to the refresh driving, partial rewriting driving for updating the display state of only a portion (line) corresponding to a change on the display screen, and interlacing driving for thinning out scanning lines on the display screen can be performed.
Then, by the partial rewriting drive and the interlace drive, it is possible to improve the followability to the change of the display information.

On the other hand, if such an FLCD can be used as a display device of an information processing system with compatibility with a CRT, the flexibility of the system can be increased and its value can be increased.

[0009]

As described above, since various driving modes are possible in the FLCD, display information (characters,
It is important that an appropriate driving mode is selected in accordance with the type of display (line image, natural image, etc.) and the type of display change (still image, moving image, scroll, etc.).

For example, scrolling display in the above-described display change mode requires relatively quick rewriting (display change) on the entire display screen and display information such as characters displayed at this time. It is necessary to secure an image quality that can clearly recognize the image. Therefore, it is necessary to select an optimal driving mode for this scroll display. For this purpose, the display control device must first recognize the scroll display.

However, when the FLCD is used as the display device of the information processing system while having compatibility with the CRT, the CPU on the system side exclusively transfers display data relating to display change and its address to the display device side. Only. Therefore, there is a problem how to reliably recognize the scroll based on the transfer of the display data and the address.

The present invention has been made based on the above-described viewpoint, and an object of the present invention is to provide a display control capable of reliably detecting scroll display from supplied display data and address data thereof. It is to provide a device.

[0013]

For this purpose, the present invention uses a display device having a display screen on which a plurality of display elements are arranged, and updates the display on the display screen based on display data. In the control device, storage means for storing the supplied display data, detection means for detecting a scroll display on the display screen based on the display data supplied from the storage means, and scroll display detected by the detection means And a driving unit for performing a display drive corresponding to the scroll display.

In a display control method for updating a display on the display screen based on the display data using a display device having a display screen on which a plurality of display elements are arranged, the display data supplied is stored. Based on the address at the time of storing in the means, a scroll display on the display screen is detected, and when the scroll display is detected,
Switching to display drive corresponding to the scroll display is provided.

[0015]

According to the above arrangement, in scroll display, the area and the number of display elements to be changed are relatively large with respect to the display elements on the entire display screen. Appears as a change in the supplied display data or the address of the display data, so that it is possible to detect that the display change mode is scroll display based on these display data. Then, based on this detection, it is possible to perform a display drive in a mode most suitable for scroll display.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an information processing system using an FLC display device having a display control device according to an embodiment of the present invention as a display device for displaying various characters and image information.

In FIG. 1, reference numeral 11 denotes a CPU for controlling the entire information processing system; 13, a main memory for storing a program to be executed by the CPU 11 and used as a work area for this execution; DMA controller (Direct Memory Access Controller) that transfers data between the main memory 13 and the various devices that make up this system without
troller (hereinafter referred to as DMAC). 15 is Ethernet
LAN interface between LAN (local area network) 16 such as (by XEROX) and this system.
It is an input / output device (hereinafter referred to as I / O) that has ROM, SRAM, RS232C interface, etc. Various external devices can be connected to the I / O 17. Reference numerals 18 and 19 denote a hard disk device and a floppy disk device, respectively, as external storage devices, and reference numeral 20 denotes a disk interface for performing signal connection between the hard disk device 18 and the floppy disk device 19 and the present system. 21 is an inkjet printer capable of recording at relatively high resolution,
A printer which can be constituted by a laser beam printer or the like, and 22 is a printer interface for performing signal connection between the printer and the present system. 23 is a keyboard for inputting character information such as various characters, control information, etc., 24 is a mouse as a pointing device, 25 is a keyboard 23 and a key interface for connecting signals between the mouse 24 and this system. is there. Reference numeral 26 denotes an FLC display device (hereinafter, also referred to as FLCD) whose display is controlled by an FLCD interface 27 as a display control device according to one embodiment of the present invention. It has a display screen as a medium. Reference numeral 12 denotes a system bus including a data bus, a control bus, and an address bus for connecting signals between the above-described devices.

In the information processing system including the various devices described above connected, generally, the user of the system
The operation is performed while corresponding to various information displayed on the display screen of the FLCD26. That is, external devices connected to the LAN 16 and the I / O 17, the hard disk 18, the floppy disk 19, the scanner 21B, the keyboard 23, the characters supplied from the mouse 24,
Image information and the like, and operation information related to the user's system operation stored in the main memory 13 are displayed on the display screen of the FLCD 26, and the user performs information editing and instructs the system while watching this display. Here, each of the above-mentioned various devices constitutes a display information supply unit for the FLCD 26.

(First Embodiment) FIG. 2 is a block diagram showing details of the FLCD interface 27 according to the first embodiment of the present invention.

In the figure, 31 is an address bus driver,
32 is a control bus driver, and 33, 43, 44 and 45 are data bus drivers, each of which is connected to each bus of the system bus 12. The absolute address data when the CPU 11 accesses the system-side video RAM (hereinafter, also referred to as VRAM) for rewriting the display contents is stored in the address bus driver.
It is provided to the access monitor circuit 50 via 31. The absolute address (data) input to the access monitor circuit 50 is
It is converted into a line address (data) corresponding to the scanning line on the display screen, and according to the write signal supplied from this circuit, the FIFO (A) memory 36 or the FIFO (B)
It is selectively written to the memory 37. This FIFO (A) or FI
The selection of FO (B) is made according to the switching of the switch S1. FIFO (A) 36 and FIFO (B) 37 are FIFO (First In First Out) memories from which data is read in the order of writing, and the lines written to these FIFO (A) 36 and FIFO (B) 37 The address data is selectively read according to the switching of the second switch S2. Further, the access monitor circuit 50 supplies line address data to a rewrite area determination circuit 51 described later with reference to FIG.

Further, the access monitor circuit 50 outputs the data to the sampling counter 34 when the CPU 11 determines the address data for accessing the memory 41 during a predetermined period and a different address is accessed, and the counter 34 outputs this data. The number of data is counted. This count value is given to the synchronization control circuit 39 and can be used to determine the ratio between partial rewriting and refresh driving.

The absolute address supplied to the FLCD interface 27 of the present embodiment via the address bus driver 31 is also input to the address selector 35, and the
U11 can access the video memory 41.

The address data read from the FIFO (A) 36 or the FIFO (B) 37 and the address data from the address counter 38 via an address conversion table 53 described later are
In response to the switching of the third switch S3, each is selectively supplied to one input unit of the address selector 35 via an address conversion table 53 and an address conversion circuit 47 described later. The address counter 38 increments the line address of the video memory 41 by "1" and generates address data for refresh driving the entire display screen. The timing of generation of the address data is controlled by the synchronization control circuit 39. Controlled.

This synchronization control circuit 39 is connected to the switches S1, S
A switching control signal for 2 and S3 and a data transfer request signal to the memory controller 40 described later are also generated. The timing of the data transfer request signal generation and the switching timing of the switches S1, S2 and S3 by the synchronization control circuit 39 are controlled by the horizontal synchronization signal (HSYNC) generated by the FLCD 26 every time display driving for one line of the display screen is performed.
It is made according to.

A control signal from the CPU 11 is supplied to a memory controller 40 via a control bus driver 32. The memory controller 40 responds to the control signal by an address selector 35 and a video memory 41.
Control. That is, the memory controller 40 includes a memory access request signal output from the CPU 11 when rewriting data in the video memory 41, and a data transfer request signal output from the synchronization control circuit 39 when displaying data in the video memory 41. The output from the address selector 35 is switched accordingly, and one of the two address data supplied to the input section of the address selector 35 is selected and supplied to the video memory 41.

The video memory 41 stores display data, and is composed of a dual-port DRAM (dynamic RAM). The display data supplied via the data bus driver 33 is written to a location specified by the address from the address selector 35, and the video data
In the display data stored in the FLCD 26, the display data specified by the address from the address selector 35 is read out and displayed on the FLCD 26 via the driver receiver 42.
Further, the driver receiver 42 gives the horizontal synchronization signal HSYNC from the FLCD 26 to the synchronization control circuit 39.

Further, via the data bus driver 43,
Data for setting the ratio between the partial rewriting and the refresh driving is supplied to the synchronization control circuit 39.

The FLC panel of the FLCD 26 is provided with a temperature sensor 26a for detecting its temperature.
The output signal of 26a is sent to CPU1 via data bus driver 44.
Forwarded to 1.

In the configuration shown in FIG. 2, when the CPU 11 changes the display, the address of the video memory 41 corresponding to the rewriting of the desired data is stored in the memory controller.
Given to 40. In response, the memory controller 40
Now, the memory access request signal of CPU11 and the synchronization control circuit
Arbitration with the data transfer request signal from 39 is performed. When the access on the CPU 11 side obtains the right, the memory controller 40
Then, switching is performed so as to select an address from the address driver 31 as an address to be given to the video memory 41, that is, an address currently accessed by the CPU 11. At the same time, a control signal from the memory controller 40 to the video memory 41 is generated, and reading and writing of data via the data bus driver 33, that is, data rewriting of the video memory 41 is performed. At this time, the address data accessed by the CPU 11 is stored in the FIFO (A) 36 or the FIFO (B) 37 via the access monitor circuit 50 and the switch S1, and is used at the time of transfer of display data described later. As described above, the display data access method viewed from the CPU 11 is not different from that of the CRT.

On the other hand, when reading data from the video memory 41 and transferring the data to the FLCD 26 for display, a data transfer request is issued from the synchronization control circuit 39 to the memory controller 40, and the address of the switch S3 is In response to the switching, the address on the address counter 38 or the FIFO side is selected by the address selector 35 after passing through the address conversion circuit 47. At the same time, a control signal for data transfer is generated by the memory controller 40, the display data of the line of the corresponding address is transferred from the memory cell of the video memory 41 to the shift register, and the driver signal is transmitted by the control signal of the serial port.
Output to 42.

As described above, the synchronization control circuit 39
By switching the switch S3 based on the horizontal synchronization signal HSYNC from the CPU 11, a cycle for refreshing the entire display screen or a partial rewrite cycle for rewriting the line accessed by the CPU 11 is generated. Also,
The synchronization control circuit 39 can switch the switch S3 according to a drive mode selection signal from a rewrite area determination circuit 51 described later with reference to FIG. Here, the full refresh cycle refers to a cycle for sequentially displaying and driving the lines constituting the display screen line by line, and this is accessed according to the address sequentially incremented by the address counter 38 as described later. This is possible when the lines change one line at a time. The partial rewrite cycle of the access line is to rewrite the line accessed by the CPU 11 within a predetermined time immediately before the cycle.

The address conversion table 53 includes a table for directly outputting address data input from the address counter 38 and an interlace table for converting these data into addresses that can be displayed in an interlace mode. One is selected according to a selection signal from the rewrite area determination circuit 51 described in detail in 3.

The interlace table includes a plurality of tables for the interlace mode in which the number of thinning lines is constant, and a plurality of tables for the interlace mode in which the number of thinning lines changes irregularly. In the scroll display, as will be described later, the interlace table is not selected, and a non-interlace table in which the address input from the address counter 38 via the switch S3 is output as it is is selected.

The address conversion circuit 47 returns the line address data corresponding to each scanning line on the display screen to the address data for accessing the video memory 41.

As described above, the address data for accessing the video memory 41 for performing the display basically includes the address data for refreshing the entire screen of the FLC display 26 in accordance with the switching of the switch S3, The address data for rewriting the partial line accessed by the CPU 11 to change the display content is output in a time-division manner. The rewriting area determination circuit 51 outputs a predetermined address in addition to the partial rewriting and refresh addresses. Can be set in an interlace mode address suitable for the display state of

FIG. 3 is a circuit diagram of the rewrite area judging circuit shown in FIG.
FIG. 51 is a block diagram showing the details of 51.

Address data for the CPU 11 to access the video memory 40 for rewriting (display change) is input to the rewriting area determination circuit 51 as line address data via the access monitor circuit 50. Also, reference data for setting the conversion table is input via the data bus driver 45B shown in FIG. A plurality of reference data are set in the register 514 in the order of input.

The line address input to the circuit 51 is
The difference is input to the latch 511 and also to the difference detection circuit 512, and the difference from the address data one timing before, which is the output from the latch 511, is detected. This difference indicates the difference between the addresses input before and after this circuit, and
In the case of, it means that continuous scanning lines on the display screen are rewritten. The difference detection circuit 512
When the difference is 1, a signal is output, and the counter 513 counts the output signal. However, this count is counted only when there is continuous output from the difference detection circuit 512 at a predetermined timing, and when the output is stopped, the count value is cleared.

The comparison circuit 515 compares the continuously counted value of the counter 513 with each of the plurality of data stored in the register 514, and determines the range of the plurality of data in which Detect if there is. Then, a conversion table selection signal corresponding to the range to which the count value belongs is output to the address conversion table 53 and the synchronization control circuit 39.

[0041] The data set in the register 514, for example N _1, N _2, N ₃ and _{(N 1> N 2> N} 3), whereby the range comprised, N ₁ or more, N
₁ or less N ₂ or more, N ₂ or less N ₃ or more, can be N ₃ or less.

In this case, for example, when the total number of scanning lines on the display screen of the FLCD 26 is 1312, N ₁ =
If 1000, when the count value of the counter 513 is in the range is greater than N ₁ can detect and display the CPU11 performs is scrolled. That is, in the case of scroll display, the CPU 11 accesses the video memory 41 with address data that rewrites all the scanning lines on the display screen sequentially from the top to the bottom one by one.
Therefore, if the difference of the line data to be accessed is 1 continuously 1000 times or more, it can be detected that the display is scroll display. Therefore, the comparison circuit 515 outputs a conversion table selection signal corresponding to this to the conversion table 53 and the synchronization control circuit 39. In response, the synchronization control circuit
39 switches the switch S ₃ to the address counter 38 side, also, the conversion table 53, the conversion table address data from the address counter 38 is output as it is selected.

Thus, it is possible to reliably detect on the FLCD 27 that the display specified by the CPU 11 on the system side is a scroll display, and the display optimal for the scroll display, that is, the scanning lines are sequentially displayed. The display by the accessed refresh driving becomes possible. As a result, variations in characters and the like in the scroll display are prevented, and these characters can be easily recognized.

When the count value of the counter 513 is in the range of the smallest value N ₃ or less, for example, it is detected that the input character is displayed, and the comparison circuit 515 converts the selection signal according to this into a conversion table. 53 and the synchronization control circuit 39. Unlike the above case, the synchronization control circuit 39 performs partial rewriting and address rewriting based on the address on the FIFO side in a time division manner at a rate corresponding to the data M and N set via the data bus driver 43 shown in FIG. Conversion table 53 on counter 38 side
So that a refresh drive based on the address through the is performed, switches the switch S _3. The time division driving mode will be described in detail with reference to FIG.

[0045] When the count value of the counter 513 is in the range of N ₁ or less N ₃ or more, interlace table corresponding to the range of the conversion table in 53 respectively is selected,
The switch S ₃ is switched to the address counter 38 side by the synchronization control circuit 39.

As described above, according to the above configuration,
Scroll display and other characteristic display modes can be selectively detected according to the size of the area where the CPU accesses the display screen.

FIG. 4 is a timing chart of each signal in the case of the time-division driving. A basic operation of alternately performing a refresh operation and a line rewrite operation in a time-division manner will be described with reference to FIG.

Here, an example is shown in which the refresh cycle is performed in units of four lines and the access line rewrite cycle is performed in units of three lines.

In FIG. 4, REE / ACS is a timing at which a full refresh cycle and a rewrite cycle of an access line are alternately generated. When "1", a full refresh cycle is performed, and when "0", an access refresh cycle is performed. Indicates a line rewrite cycle. Further, T _a time of the entire surface of the refresh cycle, T _b represents the time of rewriting cycles access lines. In this example,
Although T _a : T _b = 4: 3, an optimum value can be selected according to a required refresh rate or the like. That is, it is possible to increase the refresh rate by increasing the ratio of T _a, it is possible to improve the responsiveness of the partial changes by increasing the proportion of T _b.

The state of the FIFO (A) 36 and the FIFO (B) 37 will be described. When the switch S1 is connected to the FIFO (A) 36 side (the state A / B of the switch S1 = "1"), the CPU 11 Are sampled and stored in the FIFO (A) 36. On the other hand, when the switch S1 is connected to the FIFO (B) 37 side (A / B = "0"), the line address accessed by the CPU 11 is stored in the FIFO (B) 37. Also, switch S2 is FIFO
(A) When connected to the 36 side (switch S2 status A / B =
“1”), the address stored in the FIFO (A) 36 is output,
When the switch S2 is connected to the FIFO (B) 37 side (A / B =
"0"), the address stored in the FIFO (B) 37 is output.

One refresh of the entire screen is completed,
When the FLCD 26 outputs the vertical synchronizing signal VSYNC or when a carry occurs in the address counter 38, the address counter 38 is cleared, and the line output in the next full refresh cycle returns to the 0th line. As described above, the address counter 38 controls the synchronization control circuit 39 to output the horizontal synchronization signal.
The count is sequentially incremented to "1", "2", and "3" in accordance with the synchronization signal generated each time HSYNC is counted. The synchronization signal generated by the synchronization control circuit 39 is transmitted to the data bus driver 43. The signal is output according to the parameters M and N input to the synchronization control circuit 39 via the control circuit 39. That is, the parameters M and N determine the ratio between the refresh cycle and the partial rewrite cycle in a certain period, and the synchronization signals are output for the number of lines of the refresh cycle determined by the parameters, and are not output during the partial rewrite. On the other hand, when the addresses of the lines L1, L2, and L3 are accessed by the CPU 11, if the switch S1 is connected to the FIFO (A) 36, the addresses of the lines L1, L2, and L3 are stored here. When switch S2 is connected to FIFO (A) 36
The addresses of L1, L2 and L3 are output from here, and L1, L2 and L3 are selected as output lines. Here, the switching signal of the switch S3 is given as RFF / ACS from the synchronization control circuit 39,
In the line access cycle in which RFF / ACS is "1", the output is switched to the output from the FIFO (A) or FIFO (B) side as the output line address. When REF / ACS becomes "1", the switch S3 is switched to the address counter 38 side, and
The address counter 38 sequentially starts counting up in response to the synchronization signal output from the synchronization control circuit 39 in synchronization with the horizontal synchronization signal HSYNC, and performs the refresh operation from the line following the previous cycle. In FIG. 4, for example, "4", "5",
Lines “6” and “7” are output. In the same manner as above, the above operation is repeated, but the reason for preparing two FIFOs is to consistently and efficiently perform sampling of an address accessed by memory on one side and outputting the sampled address on the other side at the same time. To do that.
That is, the address sampling period is from the start of output of the access line of the other FIFO to the end of the refresh cycle, and after the end of the refresh cycle, when the rewrite cycle of the access line that outputs the address sampled in the immediately preceding sampling period is started. at the same time,
The address sampling period of the other FIFO is started.

As described above, in the basic operation, the refresh cycle and the line rewriting cycle are alternately repeated. In FIG. 4, the repetition cycle is set to seven lines as one unit.
T _a: T _b = 4: has been described as 3, and T _a further by the type of data to be environmental conditions and displays such as temperature, or even refresh rate, etc. which are required according to the difference of the display device material FLCD it is possible to change the ratio of T _b.

FIG. 5 shows the access monitor circuit shown in FIG.
FIG. 50 is a block diagram showing details of a reference numeral 50.

In FIG. 5, reference numeral 501 denotes a comparison circuit, which outputs a match signal when the access address of the CPU 11 input via the address driver 31 matches the event trigger address stored in the first register 46A. The event trigger address means a predetermined address that the CPU 11 always accesses when moving the cursor.

An address conversion circuit 502 converts an absolute address accessed by the CPU 11 into a line address. That is, the address input to the access monitor circuit via the address bus driver 31 is an absolute address in the system-side VRAM, and is converted into a line address corresponding to the display screen of the FLCD 26.

A comparison circuit 503 determines whether the access address of the CPU 11 is in the display area or the work area of the system-side VRAM, and when the access address is in the display area, this fact is indicated. Output.

That is, when the CPU 11 accesses the VRAM on the system side during display control, it accesses not only the display area but also the work area. As a result, the access address of the CPU input to the access monitor circuit 50 includes the address of the work area. Therefore, the comparison circuit
At 503, the input address is determined, and only when this address is in the display area of the VRAM, is written into the FIFO (A) 36 or FIFO (B) 37 as described later. The configuration of the comparison circuit 503 may be, for example, a comparison circuit that determines whether the upper two digits of the VRAM address are 10 or less. In this case, when the upper two digits of the address input to the comparison circuit 503 are 10 or less, it is output that the address is a display area address.

Reference numeral 505 denotes a latch comparison circuit.
3, the address data from the address conversion circuit 502 is fetched and compared with the fetched and latched address data during the same sampling period. If the comparisons do not match, the newly latched address data is latched and output to the FIFO memory 36 (37). At the same time, an output indicating access to a different line is output. This prevents access to the overlapping line in the video memory 41. The output indicating the access to the different line is also transferred to the sampling counter 34, and the sampling counter 34 counts this output.

Reference numeral 504 denotes a FIFO control circuit, and a comparison circuit 501
A reset signal is output in response to the coincidence signal from the CPU, and the write pointer of the FIFO memory 36 (37) is set to the head of the FIFO memory. As a result, address data to be subsequently input to the FIFO memory is stored from the beginning, and is output first when output. The FIFO control circuit 504 is also provided with an output indicating the display area from the comparison circuit 503 and a latch comparison circuit.
A write signal is output to the FIFO memory 36 (37) in response to the AND of the output indicating that access to a different line from the 505 is performed, and writing of address data input through the latch circuit 505 to this memory is permitted. .

(Second Embodiment) FIG. 6 is a block diagram showing a configuration of an FLCD 27 according to a second embodiment of the present invention. 6, the same elements as those shown in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

The present embodiment is different from the first embodiment in that the rewrite area determination circuit 51A sets the display drive mode based on the number of accesses of the CPU 11 counted by the sampling counter.

FIG. 7 is a circuit diagram of the rewrite area judging circuit shown in FIG.
FIG. 51B is a block diagram showing a detailed configuration of 51A.

The count data C counted by the sampling counter 34 within a predetermined time is input to the first comparison circuit 517 and the second comparison circuit 518. Register 516 contains the data
A plurality of sets of RL and data RM are set via the data bus driver 45B shown in FIG. These data RL and RM are
This is data for setting a range in which RL is the upper limit and RM is the lower limit. A plurality of sets are set for a plurality of display drive modes such as scroll drive, interlace, and time division drive. For example, these data sets (RL, RM) as (N _1, N _2), may be set to _{(N 2, N 3),} (N 3, N 4). In the first comparison circuit 517 and the second comparison circuit, the data RL and RM are compared with the count value C, and in each comparison, C ≦ RL
When the condition of C ≧ RM is satisfied, the output of each circuit is set to “1”. As a result, AND gate 519
Of the A, 519B and 519C, the output of the AND gate corresponding to the range that the count value satisfies becomes “1”, and according to this output, the conversion table 53 selects the corresponding table, and the synchronization control circuit 39 Corresponding processing is performed. The selection and processing corresponding to each of the display driving modes of the scroll driving, the interlacing, and the time-sharing driving according to the range that the count value C satisfies are the same as those in the first embodiment.
The description is omitted because it is the same as that of the embodiment.

With the above configuration, when the count value C satisfies the relatively large value range (N ₁ , N ₂ ), the CPU 11
Can be detected that the display indicated by scrolling is scrolling, and accordingly, the scroll driving described in the first embodiment,
That is, display by non-interlace refresh driving can be performed.

When the count value C satisfies the relatively small value range (N ₃ , N ₄ ), it is determined that the display is relatively small in rewriting, and the partial rewriting and the refresh driving described in the first embodiment are performed. Can be displayed by time-division driving. Further, the count value C is in an intermediate range (N ₂ , N
_{If 3} ) is satisfied, display in the interlace mode is possible.

(Third Embodiment) FIG. 8 is a block diagram showing a configuration of an FLCD interface 27 according to a third embodiment of the present invention. The configuration shown in FIG. 8 is substantially the same as the configuration shown in FIG.

In this example, the event detection circuit 51 shown in FIG.
In B, based on the count value C of the sampling counter 34 within a predetermined time, it is detected that the display indicated by the CPU 11 is a specific display (event). That is,
In the event detection circuit 51B, for example, a plurality of data stored in a register corresponding to a plurality of events and a count value C
Are compared by a comparison circuit, and when they match, it can be detected as an event corresponding to the data.
Then, the detection signal to that effect is stored in the address conversion table 532.
And outputs it to the synchronization control circuit 39, whereby it is possible to perform an appropriate display according to the detected event.

FIG. 9 is a flowchart schematically showing the operation of the event detection circuit 51B. That is, the data N1, N2, N3,... Nn set in the registers in steps S91, S92, S93,.
At S97,... S98, the detected event is set. That is, a signal indicating that the event is detected is output to the conversion table 53 and the synchronization control circuit 39.

If, for example, a relatively large set value is set as data to be set in the register of the event detection circuit 51B relative to the total number of scan lines on the display screen, scroll display as an event can be detected. If the number of lines, which is a relatively small value and corresponds to the character height, is set as data, the display of input characters can be detected. Then, it is possible to select an optimal display driving mode according to the detected event.

(Fourth Embodiment) FIG. 10 is a block diagram showing another configuration of the access monitor circuit 50 shown in FIG. 5 according to a fourth embodiment of the present invention.

The difference from the access monitor circuit 50 of FIG. 5 according to the first embodiment is that if the address accessed by the CPU 11 in the VRAM matches the data stored in the register 46A in advance, the first comparison circuit 501 The detection signal is output to the address conversion table 53 and the synchronization control circuit 39 shown in FIG. 2, so that an optimum display for this event is possible.

The data stored in the register 46A can be the address of an icon displayed on the display screen. For example, if there is an icon "input paper" for inputting characters, move the cursor to the position of this icon, and click
Is stored in the register 46A, that is, the address at which the icon "input paper" is displayed. As a result, the address accessed by the CPU 11
When the address matches the stored address, it can be detected that the display is related to character input.

By the way, as a display change mode (mode) that can be considered in the case of this character input, display of characters and the like, movement of a cursor, and scrolling in accordance with depression of a key can be considered. Therefore, if the detection of the display related to the character input in this case is combined with the detection of the display change mode (event) in the first to third embodiments, a more reliable display mode (event) can be realized. Detection can be performed.

FIG. 11 is a flowchart schematically showing the operation of the address conversion circuit according to this embodiment.

As shown in step S111, the CPU 11 stores address data corresponding to the event in the register 46A in advance. In step S112, the CPU 11
Access the display area of. In step S113, the CPU 11
Of the addresses accessed by CPU 11 when the click is made,
In step S114, it is determined whether or not the addresses match. If they match, the event detection signal is turned on. If they do not match, this signal is turned off.

In the case of the event detection signal relating to the input display, the display drive mode is not directly selected, and the function of making this selection more reliable is performed. Thus, a configuration in which a display driving mode such as time-division driving, refresh driving, or interlacing is directly selected may be adopted.

Further, as shown in the first and second embodiments, a plurality of data can be stored in the register 46A so that one event can be detected from among a plurality of events.

[0078]

As is apparent from the above description, according to the present invention, when scroll display is performed, the area and the number of display elements for changing the display with respect to the display elements on the entire display screen are relatively large. Since such a change in the area or the like appears as a change in the supplied display data or an address of the display data, it is possible to detect that the display change mode is scroll display based on the display data. Then, based on this detection, it is possible to perform a display drive in a mode most suitable for scroll display.

As a result, it is possible to prevent the image quality from deteriorating during scroll display, and to clearly recognize the character display during scroll.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing system incorporating a display control device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an FLCD interface according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing details of a rewrite area determination circuit shown in FIG. 2;

FIG. 4 is a timing chart for explaining time-division driving in the FLCD interface shown in FIG. 2;

5 is a block diagram showing a detailed configuration of the access monitor circuit shown in FIG.

FIG. 6 is a block diagram showing a configuration of an FLCD interface according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing details of a rewrite area determination circuit shown in FIG. 6;

FIG. 8 is a block diagram showing a configuration of an FLCD interface according to a third embodiment of the present invention.

9 is a flowchart showing an operation of the event detection circuit shown in FIG.

FIG. 10 is a block diagram illustrating details of an address conversion circuit according to a fourth embodiment of the present invention.

FIG. 11 is a flowchart schematically showing an operation of the address conversion circuit shown in FIG. 10;

[Explanation of symbols]

 11 CPU 12 Address bus 13 Main memory 14 DMA controller 15 LAN interface 16 LAN 17 I / O device 18 Hard disk drive 19 Floppy disk drive 20 Disk interface 21 Printer 22 Printer interface 23 Keyboard 24 Mouse 25 Key interface 26 FLCD (FLCD display) 26a Temperature sensor 27 FLCD interface 31 Address bus driver 32 Control bus driver 33,43,44,45A, 45B Data bus driver 34 Sampling counter 35 Address selector 36 FIFO (A) memory 37 FIFO (B) memory 38 Address counter 39 Synchronization control circuit 40 Memory controller 41 Video memory 42 Driver receiver S1, S2, S3 Switch 46A, 46B register 47 Address conversion circuit 50 Access monitor circuit 51,51A Rewrite area judgment circuit 51B Event detection circuit 53 Address conversion table 501,601 Comparison Road 502, 602 address conversion circuit 503 and 603 comparator circuit 504 FIFO control circuit 505, 605 latching comparator circuit 511 latches 512 difference detecting circuit 513 counter 514 register 515 comparator circuit 516 register 517 first comparator circuit 518 the second comparator circuit 519A, 519B, 519C AND gate

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Kenzo Ina 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (56) References JP-A-3-256096 (JP, A) JP-A-5 -35237 (JP, A) JP-A-2-9991 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 5/34 G09G 3/20

Claims (5)

(57) [Claims] 1. A display control device that uses a display device having a display screen on which a plurality of display elements are arranged and updates display on the display screen based on display data, wherein the supplied display data is stored. Storage means to perform, based on the display data supplied from the storage means, a detection means for detecting a scroll display on the display screen, when the scroll display is detected by the detection means,
A display control device comprising: driving means for performing display driving corresponding to the scroll display. 2. The display control device according to claim 1, wherein said detection means detects scroll display based on an address of said storage means. 3. The display drive mode according to claim 1, wherein the display drive includes a plurality of display drive modes, and when a scroll display is detected, a display drive mode corresponding to the scroll display is selected. Display control device. 4. The display control device according to claim 1, wherein said display element is a ferroelectric liquid crystal display element. 5. A display control method for using a display device having a display screen on which a plurality of display elements are arranged and updating display on the display screen based on the display data, wherein the supplied display data is stored. A display control method, comprising: detecting a scroll display on the display screen based on an address when the scroll display is stored; and switching to a display drive corresponding to the scroll display when the scroll display is detected.