JP2933449B2 - Automatic gain control circuit and data storage device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control circuit for amplifying an input signal to a predetermined amplitude, and more particularly to an automatic gain control circuit used for a read circuit of a data storage device.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a write / read circuit of a conventional data storage device, and FIG. 6 is a time chart showing signal waveforms of main parts thereof.

Referring to FIG. 5 and FIG. 6, a plurality of magnetic heads 301 for writing and reading and a
1 write / read circuit (hereinafter abbreviated as R / W circuit) 30
2, the capacitor C101, and the capacitor C101
, And an AGC 305 connected to a read signal output terminal of the R / W circuit 302 and an input terminal.

The AGC 305 has a squelch function of inputting a squelch signal for switching output signal transmission / non-transmission, and includes a voltage control amplifier (hereinafter abbreviated as VCA), a rectifier circuit and an amplifier. Then, the head switching signal 408 is transmitted to any one of the plurality of magnetic heads 301.
The write / read switching signal 407 is a signal for selecting the operation of the R / W circuit 302 to be a write operation or a read operation, and the write signal 406 is a signal for selecting the operation of the R / W circuit. When the R / W circuit 302 performs the read operation, the read signal 402 corresponds to the recording current information flowing through the magnetic head selected by the head switching signal 408 when the write operation is performed.
The signal reproduced by the head selected by the head switching signal 408 is amplified.

Here, when the R / W circuit 302 switches from the write operation to the read operation, a DC voltage step occurs. When the DC voltage step is superimposed on the read signal 402, the capacitor C101 is charged and a DC component is generated. , AGC30
This adversely affects the operation of No. 5. That is, since the voltage step is applied directly to the AGC 305, the AGC 30
5 operates so as to correspond to the amplitude fluctuation corresponding to the voltage step.

At this time, in order to remove the DC component of the read signal 402, a differentiating circuit composed of a CR circuit is constituted by the capacitor C101 and the AGC input resistor inserted in series with the signal transmission line. Is set large so that it is difficult to follow an instantaneous amplitude fluctuation of the read signal 402 due to external noise or the like.

[0007]

In the write / read circuit of the conventional data storage device as described above, the magnetic field is changed by a transient response when switching from the write operation to the read operation by the write / read switching signal 407 and the head switching signal 408. When the transient response at the time of switching the head is superimposed on the read signal 402, the capacitor C101 is charged and a direct current component is generated.
Operation will be adversely affected.

That is, since the time constant of the differentiating circuit constituted by the capacitor C101 and the input resistance of the automatic gain control circuit 305 is set large, the discharging time is long, and it takes time to remove the DC component of the input signal 403. However, even if the automatic gain control circuit 305 enters the output signal transmission state due to the squelch signal 405, it takes a long time until it works effectively.

[0009]

SUMMARY OF THE INVENTION An automatic gain control circuit according to the present invention is an automatic gain control circuit for amplifying a read signal used for a read circuit of a data storage device to a predetermined amplitude. A voltage controlled amplifier having a squelch function for switching, a rectifier circuit for rectifying and smoothing an output signal of the voltage controlled amplifier, a comparison between an output value of the rectifier circuit and a reference voltage value, and a signal corresponding to the difference voltage An output circuit, a removal circuit that removes a high-frequency component of the input read signal, a comparison circuit that compares an output value of the removal circuit with a predetermined threshold value, and outputs a signal corresponding to the magnitude thereof. A clamp circuit for holding a non-amplified signal input terminal voltage of the voltage-controlled amplifier at a specific voltage in accordance with a voltage value of the input signal, and releasing the voltage holding operation.

[0010]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram partially showing a block diagram showing an embodiment of the present invention. Referring to FIG. 1, an automatic gain control circuit (AGC) 304 of the present invention connects a capacitor C101, one terminal of the capacitor C101 and an output terminal of the clamp circuit 104 to a non-amplified signal input terminal, and outputs an output signal. A voltage control amplifier (hereinafter abbreviated as VCA) 101 having an output terminal of the amplifier 105 and a gain control voltage input terminal connected thereto, and A rectifier circuit 106 connected to an input terminal; an amplifier 105 connected to an output terminal of the rectifier circuit 106 to one input terminal and applying a DC voltage to the other;
Is connected to the input terminal and the output terminal is connected to the first terminal of a voltage comparison circuit (hereinafter abbreviated as COMP) 103.
A low-pass filter (hereinafter abbreviated as LPF) 102 connected to the input terminal; a + V volt voltage applied to the second terminal;
COMP103 which applied a voltage of -V volt to the terminal of
And a clamp circuit 104 to which the output terminal of the COMP 103 is connected, and a wave amplified signal input terminal of the VCA 101, which is connected to one terminal and the other is provided with a grounded resistor R101.

FIG. 2 is a timing chart showing signal waveforms at main points in FIG. The input signal 201 is a read signal that includes a DC voltage step at the time when the DC voltage signal c is denoted by the symbol “a”, and at the same time has an alternating voltage signal “b”. That is,
At time point a, the means for transmitting the input signal 201 has switched from the non-transmission state of the signal to the transmission state.

When the squelch signal 207 is at "H" level, the VCA 101 stops output transmission and fixes the amplification gain to a predetermined value. The rectifier circuit 106 outputs a voltage value corresponding to the amplitude voltage of the VCA output signal 206. Then, the amplifier 105 compares the voltage value with a predetermined set voltage VTH.
And a voltage corresponding to the difference voltage is calculated as VCA101.
To the gain control voltage terminal. VCA 101 amplifies VCA input signal 202 with a gain corresponding to the output voltage of amplifier 105. By the above operation, the AGC output signal is controlled to have an amplitude corresponding to the voltage VTH.

The LPF 102 is for suppressing the high-frequency component of the VCA input signal 202, and its cutoff frequency is set sufficiently lower than the signal frequency, but the response speed of the LPF output signal 203 as an output signal is also low. Don't set it too low because you have to consider it.

COMP 103 is an LPF output signal 203
And outputs an "H" level signal when the voltage is higher than + V volts or lower than -V volts. Otherwise, an "L" level signal is output. Clamp circuit 10
4 is a VCA input signal 2 to which the clamp circuit output terminal is connected when the COMP output signal 204 is at “H” level.
02 is forcibly set to 0 V and the state is maintained. When the COMP output signal 204 is at the "L" level, the bias voltage holding function is released.

The capacitor C101 is provided to prevent a voltage fluctuation due to the alternating voltage signal b present in the input signal 201 from appearing in the VCA input signal 202. When the input signal 201 is in a steady state such as the DC voltage signal c or the alternating voltage signal b, the DC offset voltage of the VCA input signal 202 becomes 0V. When the input signal 201 having the voltage step Vof is applied at the time point a, a voltage step occurs in the VCA input signal 202 similarly.

Referring to the example shown in FIG. 2, when the LPF output signal 203 becomes smaller than -V volt, COMP
The output signal 204 becomes “H” level, and the clamp circuit 1
04 turns ON, the VCA input terminal voltage becomes 0V
, The offset voltage of the VCA input signal 202 is quickly returned to 0V. Also, when the LPF output signal 203 becomes greater than -V volts,
The MP output signal 204 becomes “L” level, and the clamp circuit 104 is turned off. Thereby, the voltage holding is released.

After the rapid 0V return operation, the squelch signal 205 becomes "L" level (time, τ hours after a,
When the VCA 101 enters the operation mode, there is no DC offset voltage in the VCA input signal 202, and a fast automatic gain control pull-in operation can be achieved.

FIG. 3 is a block diagram showing a read circuit of a data storage device using the automatic gain control circuit of the present invention.

Referring to FIG. 3, in the present embodiment, a plurality of magnetic heads 301 for writing and reading and a
1 read / write circuit 302 and capacitor C101
And an AGC 304 connected to a read signal output terminal and an input terminal of the magnetic head write / read circuit 302 via the capacitor C101.

A head switching signal 408 is a signal for selecting one of the plurality of magnetic heads 301 to perform writing or reading, and a write / read switching signal 407.
Is a signal for selecting the operation of the R / W circuit 302 to be a write operation or a read operation.
When the W circuit 302 performs a write operation, the head switching signal 40
8, the read signal 402 is obtained by amplifying a signal reproduced by the head selected by the head switching signal 408 when the R / W circuit 302 performs a read operation. is there.

When the R / W circuit 302 switches from the write state to the read state at time d, the read signal 402
A voltage step occurs, and a head reproduction signal appears. Signal on output side of capacitor C101 and input signal 4
03 is the clamp circuit 10 shown in FIG.
The offset voltage quickly approaches 0 V by the operation of (2). Thus, when the AGC 304 starts operating with the squelch signal 405, the offset voltage of the input signal 403 becomes almost 0 V, and the AGC 304 pull-in time can be shortened.

[0023]

As described above, the present invention detects a change in bias voltage due to a transient response that occurs when a write / read switching signal is switched, and forcibly increases the bias voltage while the change exceeds a predetermined voltage. By returning the voltage to 0 V, the convergence of the transient response can be accelerated, and the pull-in time of the automatic gain control circuit can be reduced. As a result, there is an effect of enabling a high-speed switching operation.

By providing the automatic gain control circuit of the present invention in the data storage device in the read circuit, it is possible to provide a data storage device in which the switching speed of the magnetic head, the write / read switching speed, and the data read speed are increased. This control does not require an interface with an external control circuit, and has the effect of being applicable to all types of data storage devices.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing signal waveforms of main parts of FIG.

FIG. 3 is a diagram showing an embodiment of an R / W circuit of a data storage device using the automatic gain control circuit of the present invention.

FIG. 4 is a diagram showing signal waveforms of main parts in FIG. 3;

FIG. 5 is a diagram showing an example of an R / W circuit of a data storage device using a conventional automatic gain control circuit.

FIG. 6 is a diagram showing signal waveforms of main parts in FIG. 5;

[Explanation of symbols]

 Reference Signs List 101 voltage control amplifier (VCA) 102 low-pass filter (LPF) 103 voltage comparator (COMP) 104 clamp circuit 105 amplifier 106 rectifier circuit C101 capacitor R101 resistor 301 magnetic head 302 write / read circuit (R / W circuit) 304, 305 Automatic gain control circuit (AGC)

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-57-30111 (JP, A) JP-A-4-163703 (JP, A) JP-A-63-160404 (JP, A) JP-A-4- 8007 (JP, A) Actually open 58-176460 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03G 3/20-3/34 G11B 20/10 321 G11B 5/09 321

Claims (2)

(57) [Claims] 1. An automatic gain control circuit for amplifying an input read signal to a predetermined amplitude, comprising: a voltage control amplifier having a squelch function for switching output signal transmission / non-transmission; and rectifying an output signal of the voltage control amplifier. Rectifier circuit for performing a smoothing operation, an amplifier for comparing an output value of the rectifier circuit with a reference voltage value, and outputting a signal corresponding to the difference voltage, and a removing circuit for removing a high frequency component of the input read signal. A comparison circuit that compares the output value of the removal circuit with a predetermined threshold value and outputs a signal corresponding to the magnitude thereof; and a non-amplified signal input terminal of the voltage control amplifier corresponding to the voltage value of the input signal. An automatic gain control circuit, comprising: a voltage holding circuit at a specific voltage; and a clamp circuit for canceling the voltage holding operation. 2. A data storage device comprising the automatic gain control circuit according to claim 1.