JP2937136B2 - Semiconductor integrated circuit noise reliability verification method and verification system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and system for verifying noise reliability of a semiconductor integrated circuit, and more particularly to a method for verifying noise reliability of a semiconductor integrated circuit.
For design information in the handcraft design method (transistor-based layout design) of a synchronous circuit (Synchronous Circuit) of MOS (Complementary Metal Oxide Semiconductor), the waveform blunting (Slew Rate) that causes the circuit to malfunction due to the influence of noise is considered. The present invention relates to a method and system for verifying noise reliability of a semiconductor integrated circuit for verifying a large design location.

[0002]

2. Description of the Related Art Conventionally, a method or system for verifying the noise reliability of a semiconductor integrated circuit of this type has been proposed in the design stage to suppress malfunctions due to noise received by the circuit by using a circuit simulator or a higher-speed delay simulator. The simulation was performed in the case of receiving noise, and the design was performed so as not to malfunction due to the noise. Specifically, a test pattern is given to the input terminal of the circuit, and a simulation is performed in consideration of the occurrence of noise.
They verified whether the value output to the output terminal of the circuit matched the expected value obtained in a normal case. If the output value does not match the expected value, it means that the logic state of the circuit has been changed due to the influence of noise. In such a case, the designer has specified a circuit portion considered to be affected by noise from the test pattern, and has made a design change so as not to malfunction due to the noise. This is the case, for example, in 1989, ASIC
Design Handbook, Science Forum Inc., p. 182 ”,“ 1987 LSI Design and Manufacturing Technology, Denki Shoin Co., Ltd., p. 147 ”.

[0003]

The prior art described above is
When performing comprehensive verification on a large-scale circuit, an enormous amount of test pattern creation and enormous simulation time is required. As a result, there is a problem that the circuit malfunctions due to noise under conditions that are not prepared as test patterns.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a reliable and reliable verification that can quickly and comprehensively verify a design portion having a large waveform dullness which causes a malfunction of a circuit under the influence of noise in a design stage of a large-scale semiconductor integrated circuit. It is to provide a method and a verification system.

[0005] When a design portion having a large waveform dullness is affected by noise, the delay time is significantly increased. by this,
Correct logic transfer cannot be performed within the clock cycle, which causes malfunction. According to the present invention, a highly reliable semiconductor integrated circuit that does not malfunction due to the influence of noise can be designed by comprehensively obtaining a design portion having a large waveform dullness and performing an appropriate design change.

[0006]

[0007]

According to a first aspect of the present invention, there is provided a method for verifying a design portion having a large waveform dullness which causes a malfunction of a circuit due to the influence of noise on design information of a CMOS synchronous circuit in a handcraft design method. Calculating the maximum value of the output waveform dullness of the partial circuit of the circuit under verification indicated by the design information, and determining the maximum value of the output waveform dullness in violation of the limit value of the previously allowable waveform dullness. Is obtained.

[0008]

A second invention is a method for verifying a design portion having a large waveform dullness which causes a malfunction of a circuit under the influence of noise with respect to design information of a CMOS synchronous circuit in a handcraft design method, The following steps
(a) to (d). (a) Detect netlist information of a partial circuit from information corresponding to a transistor-level netlist of a circuit to be verified indicated by the design information. (b) From the netlist information of the partial circuit, an input pattern of the partial circuit at which the output waveform of the partial circuit has the greatest bluntness is obtained. (c) Transient analysis is performed from the information of the netlist of the partial circuit and the information of the input pattern, and the maximum value of the output waveform dullness of the partial circuit is obtained.
(d) Finding the partial circuit in which the determined maximum value of the output waveform dullness does not satisfy the limit value of the waveform dullness allowed for noise.

[0010]

A third aspect of the present invention is a system for verifying a design part having a large waveform dullness which causes a malfunction of a circuit due to the influence of noise on design information of a CMOS synchronous circuit in a handcraft design method, The following means
(a) to (d). (a) a partial network detection means for detecting the information of the netlist of the partial circuit from the information corresponding to the transistor-level netlist of the circuit to be verified indicated by the design information, (b) An input pattern generating means for obtaining an input pattern of the partial circuit in which the output waveform of the partial circuit has the largest bluntness from the information of the netlist; and (c) transient analysis from the information of the netlist of the partial circuit and the information of the input pattern. And (d) the obtained maximum value of the output waveform dullness satisfies the limit value of the waveform dullness allowed for noise. Error determining means for finding the partial circuit that does not exist.

In the second noise reliability verification method and verification system according to the present invention, a partial network detection means (11 in FIG. 6)
Means that the transistor is VDD from the design information of the semiconductor integrated circuit.
Detects partial circuit information for channel connection from to. The input pattern generation means (22 in FIG. 6) obtains the input pattern of the partial circuit where the output waveform bluntness of the partial circuit is greatest from the partial circuit information. The transient analysis means (23 in FIG. 6)
A transient analysis is performed from the information of the partial circuit and the input pattern, and a maximum value of the output waveform dullness of the partial circuit is obtained. Error determination means
(24 in FIG. 6) determines whether the maximum value of the output waveform dullness of the partial circuit does not violate the allowable value of the allowable waveform dullness.

[0013]

Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a flowchart showing an operation of the first embodiment, and FIGS. 3 to 5 are diagrams of the first embodiment. It is operation | movement explanatory drawing.

Referring to FIG. 1, according to a first embodiment of the present invention, a storage device 1 for storing information, a data processing device 2 operated by program control, and an output device 3 such as a display device or a printing device are provided. It is comprised including.

The storage device 1 includes a full network storage unit 4, a partial network storage unit 5, a maximum resistance storage unit 6, and a load capacity storage unit 7.
, A time constant storage unit 8, a time constant limit value storage unit 9, and a verification result storage unit 10.

The all-network storage unit 4 stores information corresponding to a transistor-level netlist of the integrated circuit in advance. The transistor-level netlist is a description of a logic circuit based on connection relations of transistors, resistors, capacitors, and the like, and model parameters, values, and the like of each. Generally, a transistor-level netlist can be obtained from layout design data (mask pattern) by software such as LPE (Layout Parameter Extractor). The partial network storage unit 5 stores the VD
It stores information on transistors connected to channels from D to VSS, the wiring capacitances driven by these transistors, the wiring resistance, and the netlist of the partial circuit consisting of the transistors. The maximum resistance storage unit 6 stores information on the maximum resistance when the partial circuit operates. The load capacity storage unit 7 stores information on the load capacity of the partial circuit. Time constant storage unit 8
Stores information on the time constant of the partial circuit. The time constant limit value storage unit 9 stores information on a time constant limit value allowed for noise. The verification result storage unit 10 stores partial circuits that violate the limit value of the time constant allowed for noise, information of the time constant, and the like.

The data processing device 2 includes a partial network detection means 1
1, maximum resistance calculation means 12, load capacity calculation means 13,
It has a time constant calculating means 14 and an error determining means 15.

The partial network detecting means 11 includes a whole network storing unit.
The information of the netlist of the partial circuit stored in 4 is detected and stored in the partial network storage unit 5. The maximum resistance calculating means 12 calculates the maximum resistance when the partial circuit operates based on the information of the netlist of the partial circuit stored in the partial network storage unit 5 and stores the maximum resistance in the maximum resistance storage unit 6. The load capacity calculation means 13 calculates the load capacity of the partial circuit from the information of the net list of the partial circuit stored in the partial circuit network storage unit 5 and stores it in the load capacity storage unit 7. Time constant calculation means 1
4 calculates the time constant of the partial circuit from the information on the maximum resistance stored in the maximum resistance storage unit 6 and the information on the load capacitance stored in the load capacitance storage unit 7 and stores it in the time constant storage unit 8 . The error determination means 15 includes information on the time constant of the partial circuit stored in the time constant storage section 8 and the time constant limit value storage section 9.
When the time constant of the partial circuit exceeds the limit value, the information of the partial circuit and its time constant are stored. Stored in the unit 10.

The output device 3 displays a partial circuit violating the limit value of the time constant allowed for noise stored in the verification result storage unit 10 and information on the time constant.

Next, the operation of the first embodiment of the present invention will be described with reference to FIGS.

The partial network detection means 11 is a full network storage unit.
4 detects the information of the netlist of the partial circuit from the information corresponding to the transistor-level netlist of the integrated circuit stored in 4 and stores it in the partial network storage unit 5 (STEP
1). The maximum resistance calculating means 12 calculates the maximum resistance when the partial circuit operates based on the information of the netlist of the partial circuit stored in the partial network storage unit 5 and stores the maximum resistance in the maximum resistance storage unit 6. The load capacity calculation means 13 includes the partial network storage 5
Then, the load capacity of the partial circuit is calculated from the information of the netlist of the partial circuit stored in the storage unit, and stored in the load capacity storage unit 7 (STEP 2). The time constant calculation means 14 calculates the time constant of the partial circuit from the information on the maximum resistance stored in the maximum resistance storage unit 6 and the information on the load capacitance stored in the load capacitance storage unit 7, and 8 (STEP 3). The error determination means 15 includes information on the time constant of the partial circuit stored in the time constant storage unit 8 and the limit value of the time constant allowed for noise stored in the time constant limit value storage unit 9. Compare with the information (STEP 4). If the time constant of the partial circuit exceeds the allowable time constant limit value, information on the partial circuit and its time constant is stored in the verification result storage unit 10 (STEP 5). Here, if all the partial circuits to be verified have not been verified,
Return to STEP 1 (STEP 6). The output device 3 is a verification result storage unit.
The partial circuit that violated the limit value of the time constant allowed for the noise stored in 10 and the information of the time constant are displayed (STEP 7).

Next, the operation of one example of the first embodiment of the present invention will be described in more detail.

Referring to FIG. 3, for example, in the all-network storage unit 4, there is a partial circuit including transistors M1, M2, M3, and M4 that are channel-connected from VDD to VSS. Other partial circuits consisting of M5 and M6, M7 and M
There is also a subcircuit consisting of 8, M9 and M10. The partial network detection means 11 reads M1, M2, M3,
The information of the netlist of the partial circuit including M4 and the wiring capacitance and wiring resistance driven by the transistors and the transistors M5 and M6 is detected and stored in the partial network storage unit 5 (ST
EP 1). Still referring to FIG. The maximum resistance calculation means 12
The transistors M1, M1 stored in the partial network memory 5
The maximum resistance Rmax is calculated from the information of M2, M3, M4 and the wiring resistance, and stored in the maximum resistance storage unit 6. Transistor ON
The value of the resistor can be calculated from the type, size, and configuration (number of vertically stacked transistors) of the transistor. Find the combination that maximizes the ON resistance of the transistor among the operation patterns of the partial circuit, and further add the wiring resistance to obtain the maximum resistance Rma
Find x. In this example, when the transistors M3 and M4 with two stacked stages are turned on, the resistance becomes the maximum.
The load capacity calculating means 13 calculates the load capacity Cmax from the information of the transistors M1, M2, M3, M4, the wiring capacity driven by these transistors and the transistors M5, M6 stored in the partial network storage unit 5, and It is stored in the capacity storage unit 7 (STEP 2). The load capacitance Cmax is determined by the transistors M1, M2, M3, M4
The sum of the diffusion layer capacitance and the wiring capacitance and the gate capacitance of the transistors M5 and M6. The time constant calculating means 14 calculates the maximum resistance Rmax when the partial circuit stored in the maximum resistance storage unit 6 operates and the load capacitance Cmax of the partial circuit stored in the load capacitance storage unit 7 based on the information. To calculate the time constant T of the partial circuit and store it in the time constant storage unit 8 (STEP 3). Still referring to FIG. 5, error determination means 1
5 is the time constant of the partial circuit stored in the time constant storage unit 8.
The information on T is compared with the information on the limit value T limit of the time constant allowed for noise stored in the time constant limit value storage unit 9 (STEP 4). Since the time constant T of the partial circuit exceeds the allowable time constant limit value T limit, the information of the partial circuit and the time constant T is stored in the verification result storage unit 10 by the error determination means 15 (STEP 5). Since all the partial circuits to be verified have not been verified, return to STEP 1 (STEP 1
6). After verifying all the partial circuits to be verified, output device 3
Thus, the partial circuit violating the limit value of the time constant allowed for the noise stored in the verification result storage unit 10 and the information of the time constant are displayed (STEP 7).

In the above-described first embodiment of the present invention, the magnitude of waveform blunting is evaluated by a time constant. Therefore, the maximum resistance calculating means 12, the load capacity calculating means 13, and the time constant calculating means 14 can be realized by simple calculations. For this reason, there is an effect that verification can be performed at a very high speed even for a large-scale circuit.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 6 is a block diagram showing a second embodiment of the present invention, FIG. 7 is a flowchart showing an operation of the second embodiment, and FIGS. 8 to 10 are diagrams of the second embodiment. It is operation | movement explanatory drawing.

Referring to FIG. 6, according to a second embodiment of the present invention, a storage device 16 for storing information, a data processing device 17 operated by program control, and an output device 3 such as a display device or a printing device. And

The storage device 16 includes a full network storage unit 4, a partial network storage unit 5, an input pattern storage unit 18, a waveform blunt storage unit 19, a waveform blunt limit value storage unit 20, a verification result storage unit. Department
21.

The entire network storage unit 4 and the partial network storage unit 5 are the same as those already described in the first embodiment of the present invention.

The input pattern storage section 18 stores information on the input pattern of the partial circuit when the output waveform of the partial circuit has the greatest bluntness. The waveform blunting storage unit 19 stores information on the maximum value of the waveform blunting of the partial circuit. The waveform dulling limit value storage unit 20 stores information on a waveform dulling limit value allowed for noise. The verification result storage unit 21 stores information on a partial circuit violating the limit value of waveform blunting allowed for noise and information on the maximum value of the output waveform blunting.

The data processing device 17 includes a partial network detecting means.
11, an input pattern generation unit 22, a transient analysis unit 23, and an error determination unit 24.

The partial network detection means 11 is the same as that already described in the first embodiment of the present invention.

The input pattern generation means 22 determines a partial circuit having the largest output waveform dullness from the partial circuit netlist information stored in the partial network storage unit 5.
One set of input patterns is obtained and stored in the input pattern storage unit 18. The transient analysis unit 23 performs a transient analysis using a circuit simulator or a delay simulator from the information of the netlist of the partial circuit stored in the partial network storage unit 5 and the information of the input pattern stored in the input pattern storage unit 18. Then, the maximum value of the output waveform dullness of the partial circuit is obtained and stored in the waveform dulling storage unit 19. The error determination unit 24 determines the maximum value of the output waveform bluntness of the partial circuit stored in the waveform blunting storage unit 19 and the waveform blunting allowable for the noise stored in the waveform blunting limit value storage unit 20. If the maximum value of the output waveform dullness of the partial circuit exceeds the limit value, the information of the partial circuit and the maximum value of the output waveform dullness are stored in the verification result storage unit 21. .

The output device 3 displays information on the partial circuits stored in the verification result storage unit 21 and the maximum value of the output waveform dullness and the like.

Next, the operation of the second embodiment of the present invention will be described with reference to FIGS.

The partial network detecting means 11 includes a whole network storing unit.
The information of the netlist of the partial circuit stored in 4 is detected and stored in the partial network storage unit 5 (STEP 1). The input pattern generation unit 22 obtains a set of input patterns of the partial circuit in which the output waveform of the partial circuit becomes the largest from the information of the net list of the partial circuit stored in the partial network storage unit 5, and stores the input pattern. It is stored in the unit 18 (STEP 8). The transient analysis unit 23 performs a transient analysis using a circuit simulator or a delay simulator from the information of the netlist of the partial circuit stored in the partial network storage unit 5 and the information of the input pattern stored in the input pattern storage unit 18. The maximum value of the output waveform dullness of the partial circuit is obtained, and the waveform dulling storage unit 19 is obtained.
(STEP 9). The error determination unit 24 determines the maximum value of the output waveform bluntness of the partial circuit stored in the waveform blunting storage unit 19 and the waveform blunting allowable for the noise stored in the waveform blunting limit value storage unit 20. (STEP 10). When the maximum value of the waveform bluntness of the partial circuit exceeds the limit value of the waveform bluntness allowed for the noise, information on the partial circuit and the maximum value of the waveform blunting thereof is stored in the verification result storage unit 21. (STEP 11). here,
If you have not verified all the subcircuits to be verified,
Return to 1 (STEP 12). The output device 3 includes a verification result storage unit 21
The partial circuit violating the limit value of the waveform blunting allowed for the noise stored in the sub-circuit and information on the maximum value of the output waveform blunting are displayed (STEP 13).

Next, the operation of one example of the second embodiment of the present invention will be described in more detail.

Referring to FIG. 8, for example, the partial network detecting means 11 stores the M1, M2, M3, M4
And the wiring capacity and wiring resistance driven by those transistors and the information of the netlist of the partial circuit including the transistors M5 and M6 are detected and stored in the partial network storage unit 5 (STEP
1). Still referring to FIG. 9, the input pattern generation means 22
Is from VDD stored in the partial network storage 5 to VSS
Transistors M1, M2, M
3. From the information of M4, first detect the combination that maximizes the resistance of the transistor that turns on. In the combination in which the resistance of the transistor is maximum, the waveform bluntness is maximum.
The ON resistance value of a transistor can be calculated from the type, size, and configuration (the number of vertically stacked transistors) of the transistor. When the type of transistor that turns on with the maximum resistance is the P-channel type, the input pattern applied to the gate of the transistor is fall, and when the type is N-channel, it is rise. Since M3 and M4 are N-channel types, the input pattern is rise. For the input waveform dulling, a maximum allowable value is used. This is because when the input waveform becomes dull, the output waveform becomes dull. The input pattern generation means 22 generates an input pattern in this way and stores it in the input pattern storage unit 18.
(STEP 8). The transient analysis unit 23 performs a transient analysis using a circuit simulator or a delay simulator from the information of the netlist of the partial circuit stored in the partial network storage unit 5 and the information of the input pattern stored in the input pattern storage unit 18. Do. At this time, the diffusion layer of the load transistor is the transistor type.
Clamp and VSS Clamp for N channel.
M5 is VDD Clamp and M6 is VSS Clamp. Further, the voltage waveform of the gate of the transistor serving as a load is observed, and the waveform with the largest waveform bluntness is stored in the waveform blunting storage unit 19. The waveform dullness at the gates of M5 and M6 is T5 and T6, respectively, and since T5> T6, T5 is stored in the waveform dulling storage unit 19 (STEP 9). Still referring to FIG. 10, the error determination means 24 includes information on the maximum value T5 of the output waveform dullness of the partial circuit stored in the waveform dulling storage unit 19,
The waveform dulling limit value storage unit 20 compares the allowable waveform dulling limit value T limit with respect to the noise stored in the storage unit 20 (STEP 10). Maximum value of output waveform dullness of partial circuit T5
Is the allowable value of the waveform bluntness for noise T limi
Since t exceeds t, the information of the partial circuit and the maximum value T5 of the output waveform dullness is stored in the verification result storage unit 21 by the error determination means 24 (STEP 11). Since all the partial circuits to be verified have not been verified, the process returns to STEP 1 (STEP 12). After verifying all the partial circuits to be verified, the output device 3 violates the limit value of the waveform blunting allowable for the noise stored in the verification result storage unit 21 and the maximum value of the output waveform blunting. Is displayed (STEP 13).

In the above-described second embodiment of the present invention, the transient analysis means 23 performs a transient analysis using a circuit simulator, a delay simulator, or the like, and obtains waveform dullness. For this reason, there is an effect that higher-precision verification can be performed as compared with the first embodiment of the present invention. Further, the partial circuit detected by the partial circuit network detecting means 11 is extremely small, and the input pattern generated by the input pattern generating means 22 is only a minimum necessary combination (only one set of patterns). Therefore, the processing time of the transient analysis in the transient analysis means 23 is extremely short. Therefore, there is an effect that high-speed verification can be performed even for a large-scale circuit.

[0041]

As described above, according to the present invention, a partial circuit is detected from a netlist of a circuit to be verified, and the time constant or the magnitude of waveform dullness is verified for each partial circuit. In the design stage of a large-scale semiconductor integrated circuit, there is an effect that high-speed and comprehensive verification can be performed on a design portion having a large waveform dullness that causes a circuit malfunction due to the influence of noise.

Further, there is no need to create test patterns and their expected values unlike the method of the prior art, so that the number of work steps is reduced and the verification efficiency is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the first exemplary embodiment of the present invention.

FIG. 3 is a diagram for explaining an operation of the first exemplary embodiment of the present invention.

FIG. 4 is a drawing subsequent to FIG. 3 for explaining the operation of the first exemplary embodiment of the present invention.

FIG. 5 is a drawing subsequent to FIG. 4 for explaining the operation of the first exemplary embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 7 is a flowchart illustrating an operation of the second exemplary embodiment of the present invention.

FIG. 8 is a drawing for explaining the operation of the second exemplary embodiment of the present invention.

FIG. 9 is a drawing subsequent to FIG. 8 for explaining the operation of the second exemplary embodiment of the present invention.

FIG. 10 is a drawing subsequent to FIG. 9 for explaining the operation of the second exemplary embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 storage device 2 data processing device 3 output device 4 full network storage unit 5 partial network storage unit 6 maximum resistance storage unit 7 load capacity storage unit 8 time constant storage unit 9 time constant limit value storage unit 10 verification result storage unit 11 Partial network detection means 12 Maximum resistance calculation means 13 Load capacity calculation means 14 Time constant calculation means 15 Error determination means 16 Storage device 17 Data processing device 18 Input pattern storage unit 19 Waveform blunt storage unit 20 Waveform blunt limit value storage unit 21 Verification Result storage unit 22 Input pattern generation unit 23 Transient analysis unit 24 Error determination unit

Claims (3)

(57) [Claims] (1) A CMOS method in a handcraft design method.
Circuit malfunction due to noise on the design information of the period circuit
How to verify design points with large waveform dullness
A part of a circuit to be verified indicated by the design information.
The maximum value of the output waveform dullness of the circuit is obtained, and the obtained output
Limit value of waveform blunting where the maximum value of force waveform blunting is allowed in advance
Seeking said partial circuit violating
A method for verifying noise reliability of a semiconductor integrated circuit. 2. The method of CMOS in a handcraft design method.
Circuit malfunction due to noise on the design information of the period circuit
How to verify design points with large waveform dullness
Method comprising the following steps (a) to (d):
A method for verifying noise reliability of a semiconductor integrated circuit. (a) The transistor of the circuit under verification indicated by the design information
From the information corresponding to the level netlist,
Detects the information in the list. (b) from the netlist information of the partial circuit,
The input pattern of the partial circuit in which the output waveform dullness is greatest
Ask for (c) the netlist information of the partial circuit and the input pattern
Transient analysis is performed from the information of the
Find the maximum value of the dullness. (d) The obtained maximum value of the output waveform dullness corresponds to the noise.
Not satisfying the limit value of the waveform dullness allowed
Find a partial circuit. 3. The method of CMOS in a handcraft design method.
Circuit malfunction due to noise on the design information of the period circuit
To verify design points with large waveform dullness
A stem having the following means (a) to (d):
Characteristic noise reliability verification system for semiconductor integrated circuits
M (a) The transistor of the circuit under verification indicated by the design information
From the information corresponding to the level netlist,
Sub-network detecting means for detecting information of the packet list, (b) From the detected netlist information of the partial circuit
The portion where the output waveform bluntness of the partial circuit is greatest
Input pattern generation means for obtaining an input pattern of the circuit; (c) the netlist information of the partial circuit and the input pattern
Transient analysis is performed from the information of the
Transient analysis means for determining the maximum value of the dullness, (d) The obtained maximum value of the output waveform dullness corresponds to the noise.
Not satisfying the limit value of the waveform dullness allowed
Error determination means for obtaining a partial circuit.