JP2937880B2 - Clamp circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit used in a television receiver, a video tape recorder (VTR) or the like, and more particularly to a clamp circuit for controlling a clamp level corresponding to a video signal.

[0002]

2. Description of the Related Art Generally, such a clamp circuit is used to quickly stabilize a video signal to a predetermined voltage level (clamp level).

FIGS. 10 (a) and 10 (b) are a block diagram of a clamp circuit and a video signal waveform diagram, respectively, showing an example of such a conventional art. As shown in FIG. 10A, the clamp circuit 15 includes an analog clamper 16 for clamping a video signal from the input signal terminal IN, and an integrator 19, and performs reference level feedback. In particular, the clamped video output is supplied to the A / D converter 17.
A / D converted to a digital signal by the output terminal OU
While being output to T, the A / D-converted digital signal and the digital clamp set value S are compared by the digital level comparator 18, and the comparison result is output to the integrator 19.

That is, the clamp circuit 15 obtains a clamp level by integrating an A / D conversion output using an integrator 19.

[0005] As shown in FIG.
When the time for outputting the clamp level is taken on the X-axis and the voltage is taken on the Y-axis, the A / D conversion output for the video signal IN is compared with a set value and then integrated by the integrator 19 to obtain the clamp voltage The level CL converges in an early period.

The advantage of the above-described clamp circuit 15 is that the digital level comparator 18 has a digital clamp level S.
, The reference potential of the clamp level can be set from the digital signal.

However, such a simple clamp circuit cannot be used in today's complicated television receivers. That is, when only the AC component is transmitted by the capacitive coupling of the luminance signal of the video signal, the signal voltage of the pedestal, black and white levels of the luminance signal changes depending on the magnitude of the luminance signal. Therefore, in a television receiver or the like, the DC level is reproduced by clamping the pedestal level of the luminance signal. In this television receiver or the like, the pedestal level is clamped with higher accuracy and stability. There is a need to do. As a conventional example for solving such a problem, for example, Japanese Patent Laid-Open Publication No.
No. 36409 and the like.

FIG. 11 is a clamp circuit diagram showing another example of the related art. As shown in FIG. 11, the clamp circuit 20 is an example using a reference level correction method, in which a video signal from an input terminal IN is subjected to an A / D converter 23 via a capacitor C3 and an input buffer 22 to receive an A / D signal. After the / D conversion, the A / D converted signal is processed by the digital video signal processing circuit 24 to correct the reference level. This clamp circuit 20 includes the A / D converter 2
3, a clamp level detecting section 25 for receiving the output of the third level and detecting the level, a clamp level setting section 26 for setting a predetermined level based on the output of the level detecting section 25,
A differential amplifier 21 having the output of the level setting section 26 as one input (− side), and a synchronous reproduction circuit 27 which receives the output of the above-described A / D converter 23 and reproduces a horizontal synchronization signal.
A burst lock detector 28 for detecting a burst lock by the synchronous reproducing circuit 27, and a switch SW2 and a resistor R3 controlled by the synchronous reproducing circuit 27 to feed back the output of the differential amplifier 21 to the input buffer 22. Be composed. This differential amplifier 21
Indicates that the output of the voltage level setting circuit 29 and the output of the clamp level setting unit 26 described above are minus (-) through the resistor R1.
Side, and on the plus (+) side, an inverting amplifier 30 to which a fixed level is inputted by the voltage level setting circuit 29 and the capacitor C1, and connected between the (−) side terminal and the output terminal of the inverting amplifier 30. A switch SW1 controlled by the output of the burst lock detection unit 28 and a resistor R2.

In this clamp circuit 20, when the output of the A / D converter 23 is higher than the reference level set by the voltage level setting circuit 29, the clamp level is lowered. It works to raise. Therefore, the clamp circuit 20 including the differential amplifier 21 repeats such an operation several times, so that the clamp level can be converged in an early period.

FIGS. 12 (a) to 12 (c) are a signal waveform diagram when the clamp level is lowered and raised in FIG. 11 and a signal waveform diagram for explaining the convergence period. First, as shown in FIG.
This is when the output obtained by A / D conversion of the input signal IN by the A / D converter 23 is higher than the reference level set by the voltage level setting circuit 29. Therefore, the clamp circuit 20 in this case works to lower the clamp level.

As shown in FIG. 12B, in this case, as described above, the output obtained by A / D converting the input signal IN by the A / D converter 23 is set by the voltage level setting circuit 29. When it is lower than the reference level. Therefore, the clamp circuit 20 in this case works to increase the clamp level.

Further, as shown in FIG. 12 (c), the clamp circuit 20 raises and lowers the clamp level CL with respect to the input signal IN so that the clamp level converges in an early period. ing.

The convergence period of the clamp level is shorter than the convergence period of FIG. 10B.

[0014]

The above-mentioned conventional clamp circuit can stabilize the clamp level in a short period of time, but the clamp width (the time required for the clamp level to converge) is fixed. For this reason, for example, when a video signal of special playback in triple-speed playback of a VTR or the like is input, there is a drawback that the clamp level cannot be stabilized during a fixed clamp width.

That is, for a special video signal at the time of triple-speed reproduction of a VTR or the like, the clamp width can be varied by a mode detector or the like on the VTR side. Even when the video signal is input, the state of the video signal cannot be recognized, so the clamp level is pulled in for the same period as when a normal video is input. Therefore, even when a special video signal is input, the clamp width of the television receiver must be fixed at a width that does not affect the video signal itself.

In short, in the conventional clamp circuit, since the pull-in period is not constant depending on the state of the video signal, the clamp width has to be fixed in the pull-in period in consideration of the margin. Moreover, in order to pull in the clamp level within a fixed period, an amplifier having a high amplification factor or the like is used for a circuit for converging the clamp level.

An object of the present invention is to provide a clamp circuit capable of changing a pull-in period of a clamp level in order to obtain a sufficient clamp level in processing such a video signal.

[0018]

A clamp circuit according to the present invention detects a falling edge or a rising edge of a horizontal synchronizing signal and starts outputting a clamp level.
An edge detector for detecting the rising or falling edge of the video signal and terminating the output of the clamp level; and a maximum of the start and end of the clamp level output based on the horizontal synchronization signal. A maximum / minimum width guarantee circuit for guaranteeing a period and a minimum period;
A selector for self-determining and selectively outputting any one of a period from the start to the end of the clamp level output of the second edge detector and a clamp level output period guaranteed by the maximum / minimum width guarantee circuit; A clamp pulse generator for generating a clamp pulse for the video signal in accordance with the selected output, wherein a period during which the clamp level is output is controlled corresponding to the video signal.

Further, the clamp circuit of the present invention sets a first reference level for observing a change in the voltage level of the video signal, and generates a differential pulse when a voltage level exceeding the first reference level is detected. Setting a differential pulse generator for detecting the rising or falling edge of the differentiated pulse and starting the output of the clamp level, and setting a second reference level for observing a change in the voltage level of the video signal. An edge detector for terminating the output of the clamp level when a voltage level exceeding the reference level is detected, and a maximum / maximum period for guaranteeing the maximum and minimum periods of the start and end of the clamp level output based on the horizontal synchronization signal. A small-width assurance circuit; a period from the start to the end of the clamp level output by the differential pulse generator and the edge detector; A selector for self-determining and selecting and outputting any one of the clamp level output periods in the minimum width guarantee circuit; and a clamp pulse generator for generating a clamp pulse for the video signal by the selected output. A period during which the clamp level is output is controlled so as to correspond to the video signal.

Further, the clamp circuit of the present invention compares the digital data obtained by A / D conversion of the video signal with first and second reference levels set in advance, and the digital data exceeds the first reference level. A digital comparator for starting the clamp level output when the level exceeds the second reference level, and terminating the clamp level output when the level exceeds the second reference level. A maximum / minimum width assurance circuit for guaranteeing a period, and a self-determination of any one of a period from the start to the end of the clamp level output in the digital comparator and a clamp level output period in the maximum / minimum width guarantee circuit. And a clamp pulse for generating a clamp pulse for the video signal by the selected output. And a generator configured a period for outputting the clamp level to control the video signal corresponding to.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a clamp circuit for explaining an embodiment of the present invention. As shown in FIG.
The clamp circuit 2 according to the present embodiment is an example that is connected between the analog circuits 1A and 1B and starts a clamp period at a rising edge of a horizontal synchronization signal (Hsync) S2 received together with the analog video signal S1.

This clamp circuit 2 has an analog circuit 1A
For receiving a video signal S1 and a horizontal synchronizing signal S2, detecting start and end edges from the horizontal synchronizing signal S2, respectively, and outputting a clamp level output start control signal S3 and a clamp level output end control signal S4. First and second edge detectors 3 and 4, a maximum width and minimum width guarantee circuit 5 for receiving the horizontal synchronization signal S2 and outputting a maximum width and minimum width guarantee period signal S5 of the clamp width, and these signals S3
To S5, and outputs a selected signal as a clamp level control signal S6, a switch 8 controlled by the clamp level control signal S6, and a normal amplifier 9 having a low amplification factor. 1B
And a clamp pulse generator 7 for determining a period of generation of a clamp pulse for the pulse. Here, considering the signals S3 to S5 input to the selector 6, the signals S3 and S5
When the clamp width set in step 4 is S5min <clamp width <S5max, the clamp width set by the signals S3 and S4 is selected, and otherwise, the clamp width of the signal S5 is selected.

In controlling the clamp level output period corresponding to the video signal S1, the clamp circuit 2
The rising edge of the horizontal synchronization signal S2 is detected by the first edge detector 3, and is output as a level output start signal S3. In the second edge detector 4, the video signal S
A timing when 1 exceeds the reference level is detected, and a level output end signal S4 is output. On the other hand, the maximum width / minimum width guarantee circuit 5 outputs the maximum width / minimum width guarantee period signal S5 based on the horizontal synchronizing signal S2 only for a period T0 similar to the conventional fixed guarantee period. Based on these signals S3 to S5, the selector 6 outputs a clamp level control signal S6 that is turned on only during the clamp pulse pull-in period T1. Therefore, the clamp pulse generator 7 turns on the switch transistor 8 for the pull-in period T1, so that the clamp pulse is output to the next-stage analog circuit 1B.

Hereinafter, the more specific operation of the above-described clamp circuit 2 will be described with reference to waveform diagrams, separately for a case where there is no noise and a case where there is noise.

FIGS. 2A and 2B are signal waveform diagrams when the video signal in FIG. 1 has no noise and is superimposed, respectively. First, as shown in FIG.
If no noise is superimposed on the video signal S1 (here, the luminance signal is omitted) for which the reference level is set to the first level, the first
The edge detector 3 confirms that the video signal S1 has been input by the horizontal synchronization signal S2, detects the rising edge of the horizontal synchronization signal S2, and outputs the above-described level output start signal S3 to the selector 6. . This allows
The selector 6 outputs the clamp pulse control signal S6 to the clamp pulse generation circuit 7, turns on the switch 8, and starts pulling in the clamp level. Also, the second edge detector 4 confirms that the video signal S1 has been input by the horizontal synchronization signal S2, and when the video signal S1 exceeds a preset reference level, the selector 6
To output the above-described level output end signal S4. Further, the maximum width / minimum width guarantee circuit 5 starts an internal counter (not shown) by the horizontal synchronizing signal S2, and outputs the guarantee period signal S5 to the selector 6 during the guarantee period T0.
Therefore, the selector 6 only needs to compare whether or not to output the clamp pulse control signal S6 before and after the fixed guarantee period T0. In short, the period T
When 1 is larger than the guarantee period T0, this period T1 is set as the clamp width.

On the other hand, as shown in FIG. 2B, the signals S3 to S5 are omitted here because they have the same waveform as that of FIG. 2A, but the noise N is superimposed on the video signal S1. In particular, when noise N or the like enters the clamp detection period and exceeds the reference level, in order to prevent the pull-in period of the clamp level from becoming shorter than the conventional guarantee period T0, the maximum width and the minimum width are guaranteed in advance. The minimum clamp period control signal S5 of the counter value set in the circuit 5 is output to the selector 6. This makes it possible to accurately detect that the video signal S1 has exceeded the reference level even if there is noise N.

FIG. 3 is a signal waveform diagram when there is no luminance signal in the video signal in FIG. 1 for a long time. As shown in FIG. 3, when the luminance signal is not detected from the video signal S1 for a long period even when the video signal S1 is received, when the pull-in of the clamp level is terminated by the reference level, a clamp pulse is generated in the video signal S1. Because of the influence, the clamp period control signal S5 of the maximum counter value set in the maximum width and minimum width guarantee circuit 5 is output to the selector 6. That is, the clamp level control signal S6 output from the selector 6 turns on the switch of the clamp pulse generator 7 in response to the clamp period control signal S3 to start pulling in the clamp pulse, and the clamp period control signal S4
Is larger than the minimum counter value of the maximum width minimum width guarantee circuit 5 and smaller than the maximum counter value of the maximum width minimum width guarantee circuit 5, the switch 8 of the clamp pulse generator 7 is turned off by the clamp period control signal S4. Thus, the retraction of the clamp level is completed.

When the clamp period control signal S4 is smaller than the minimum counter value of the maximum width minimum width guarantee circuit 5, the clamp period control signal S5 outputting the minimum counter value of the maximum width minimum width guarantee circuit 5 is output. When the clamp period control signal S4 is larger than the maximum counter value of the maximum width minimum width guarantee circuit 5, the clamp period control signal S5 outputting the maximum counter value of the maximum width minimum width guarantee circuit 5 The switch 8 of the clamp pulse generator 7 is turned off to terminate the pull-in of the clamp level.

As described above, in the present embodiment, the rising edge of the horizontal synchronizing signal S2 is detected to start the clamp level output, and the clamp level output is made corresponding to the level difference between the video signal S1 and the reference level. Has been terminated. In addition, since the limit of the maximum value and the minimum value is added to the clamp level output period, the selector 6 can select the clamp level output period controlled from the video signal S1 or the maximum value or the minimum value period.

In the above-described embodiment, the rising of the horizontal synchronizing signal S2 is detected. However, the same can be realized by detecting the falling.

FIG. 4 is a configuration diagram of a clamp circuit for explaining another embodiment of the present invention. As shown in FIG. 4, the clamp circuit 2 in the present embodiment is an example of being connected between the analog circuits 1A and 1B and starting a clamp period at a rising edge of the analog video signal S1. This embodiment is different from the above-described embodiment in that the edge detector 3 for detecting the rising edge of the horizontal synchronizing signal S2 is used instead of the level difference between the video signal S1 and the reference level. And a differential pulse detector 10 for performing a differential process.

When the differential pulse detector 10 confirms that the video signal S1 has been input by the horizontal synchronizing signal S2, the clamp circuit 2 differentiates the analog video signal S1 with respect to a signal exceeding the first reference level. Perform processing. When the first rising edge of the differentiated pulse obtained by this differentiation process is detected, a clamp level output start control signal S3 is output to the selector 6. Further, the edge detector 4 confirms that the video signal S1 has been input by the horizontal synchronization signal S2, and terminates the clamp level output when the video signal S1 exceeds a second reference level set in advance. The control signal S4 is output. Further, the maximum width / minimum width guarantee circuit 5 starts an internal counter by the horizontal synchronization signal S2, and outputs the maximum width / minimum width guarantee period signal S5.
Is output to the selector 6. Based on these signals S3 to S5, the selector 6 outputs a clamp level control signal S6. Therefore, the clamp pulse generator 7 generates a clamp pulse in the range from the minimum width to the maximum width, and outputs the generated clamp pulse to the analog circuit 1B at the next stage.

FIGS. 5A and 5B are signal waveform diagrams when the video signal in FIG. 4 has no noise and is superimposed, respectively. As shown in FIG. 5A, when there is no noise in the video signal S1, two selector levels are set for the video signal S1, and the selector 6 sets the clamp level control signal having the minimum width to the maximum width. S6 can be output.

As shown in FIG. 5B, the noise N is superimposed on the video signal S1 during the clamp detection period and the second
When the reference level exceeds the reference level, in order to prevent the pull-in period of the clamp level from becoming shorter than before, the minimum maximum width of the counter value previously set in the maximum width minimum width guarantee circuit 5 is set. Small width guarantee period signal S
5 is output to the selector 6. Thereby, even when the noise N is superimposed, it is possible to prevent the pull-in period from being reduced.

FIG. 6 is a signal waveform diagram when there is no luminance signal in the video signal in FIG. 4 for a long time. As shown in FIG. 6, when the luminance signal is not detected for a long period of time even when the video signal S1 is input, if the pull-in of the clamp level is terminated by the second reference level, the clamp signal affects the video signal S1. Therefore, the maximum maximum width minimum width guarantee period signal S5 set in the maximum width minimum width guarantee circuit 5 is output to the selector 6. On the other hand, the selector 6 receives the clamp level output start control signal S3, outputs the clamp level control signal S6, turns on the switch 8 of the clamp pulse generator 7, and starts pulling in the clamp level. When the clamp level output end control signal S4 is larger than the minimum counter value of the maximum width / minimum width guarantee circuit 5 and smaller than the maximum counter value of the maximum width / minimum width guarantee circuit 5, it is clamped by the clamp level output end control signal S4. The switch 8 of the pulse generator 7 is turned off to terminate the pulling of the clamp level. Also,
When the clamp level output end control signal S4 is smaller than the minimum counter value of the maximum width minimum width guarantee circuit 5, the maximum width minimum width guarantee period signal S5 outputting the minimum counter value of the maximum width minimum width guarantee circuit 5 is used. When the clamp level output end control signal S4 is larger than the maximum counter value of the maximum width / minimum width guarantee circuit 5, the maximum width / minimum width guarantee circuit 5
Of the clamp pulse generator 7 by the maximum width minimum width guarantee period signal S5 which outputs the maximum counter value of
Is turned off to terminate the pull-in of the clamp level.

As described above, in the present embodiment, the differential processing is performed on the level difference between the video signal S1 and the first reference level, and the edge of the differential pulse S3 as the clamp level output start control signal is detected. Then, the clamp level output is started, and the clamp level output is ended according to the level difference between the video signal S1 and the second reference level. In addition, since the limit of the maximum value and the minimum value is added to the clamp level output period, the selector 6 can select the clamp level output period controlled from the video signal S1 or the maximum value or the minimum value period.

Further, in the above-described embodiment, the rising of the video signal S1 is detected, but the same can be realized by detecting the falling.

FIG. 7 is a block diagram of a clamp circuit for explaining still another embodiment of the present invention. As shown in FIG. 7, a clamp circuit 2 in the present embodiment is connected between an analog circuit 1 and a digital circuit 11 and feeds back an output signal S7 of an A / D converter 12 provided in the digital circuit 11. Is an example of controlling the clamp period. Clamp circuit 2 of the present embodiment
Receives the horizontal synchronizing signal S2, inputs the maximum width and minimum width guarantee circuit 5 that outputs the maximum width and minimum width guarantee period signal S5, and inputs the horizontal synchronizing signal S2 and the conversion output S7 of the A / D converter 12. A digital comparator 13 for comparing the converted output S7 with each reference level; a selector 6 which receives the comparison output of the comparator 13 and the maximum width / minimum width guarantee period signal S5 and outputs a clamp level control signal S6; And a clamp pulse generator 7 which is controlled by a clamp level control signal S6 to determine a period of generation of a clamp pulse for the digital circuit 11.

In the clamp circuit 2, the analog video signal S1 is input from the analog circuit 1 to the digital circuit 11 for performing video signal processing.
At 1, the signal is converted by the A / D converter 12 into an n-bit digital signal S7. The horizontal synchronizing signal S2 output from the analog circuit 1 is input to the maximum width / minimum width guarantee circuit 5 and the digital comparator 13, and the digital comparator 1
3, the horizontal synchronizing signal S2 causes the video signal S
1 is input, the digital signal S7
Is determined. Moreover, this digital comparator 1
In No. 3, two reference levels are set in advance by digital values.

In particular, when the digital comparator 13 determines that the digital signal S7 is larger than the first reference level, it outputs the rising edge to the selector 6 as a comparison output. Further, when it is determined that the digital signal S7 is higher than the second reference level (second reference level> first reference level), the rising edge is similarly output to the selector 6 as a comparison output. Note that the maximum width / minimum width guarantee circuit 5 that outputs the maximum width / minimum width guarantee period signal S5 starts an internal counter by the horizontal synchronization signal S2 as in the above-described embodiment.

FIGS. 8A and 8B are signal waveform diagrams when the video signal in FIG. 7 has no noise and is superimposed, respectively. As shown in FIG. 8A, when there is no noise in the video signal S1, the first
And the second reference level, the selector 6
Can output the clamp level control signal S6 from the minimum width (conventional width) to the maximum width.

As shown in FIG. 8B, the noise N is superimposed on the video signal S1 during the clamp detection period and the second
When the reference level exceeds the reference level, in order to prevent the pull-in period of the clamp level from becoming shorter than before, the minimum maximum width of the counter value previously set in the maximum width minimum width guarantee circuit 5 is set. Small width guarantee period signal S
5 is output to the selector 6. Thereby, even when the noise N is superimposed, it is possible to prevent the pull-in period from being reduced.

FIG. 9 is a signal waveform diagram when the video signal in FIG. 7 has no luminance signal for a long time. As shown in FIG. 9, when the luminance signal is not detected for a long period of time even when the video signal S1 is input, when the pull-in of the clamp level is terminated by the second reference level, the clamp signal affects the video signal S1. Therefore, the maximum value of the counter set in the maximum width minimum width guarantee circuit 5 is output to the selector 6 as the maximum width minimum width guarantee period signal S5.

On the other hand, the selector 6 receives the rising edge of the digital output S7 detected based on the first reference level, and thereby receives the clamp level control signal S6.
And the switch 8 of the clamp pulse generator 7 is turned on to start pulling in the clamp level. However, the rising edge detected by the second reference level is smaller than the minimum counter value of the maximum width and minimum width guarantee circuit 5. When the value is larger and smaller than the maximum counter value of the maximum width and minimum width guarantee circuit 5, the switch 8 of the clamp pulse generator 7 is turned off at the rising edge detected by the second reference level, and the pull-in of the clamp level ends. Let it. When the rising edge detected by the second reference level is smaller than the minimum counter value of the maximum width / minimum width guaranteeing circuit 5, the minimum counter value of the maximum width / minimum width guaranteeing circuit 5 is used. Is larger than the maximum counter value of the maximum width minimum width guarantee circuit 5, the maximum width minimum width guarantee period signal S which outputs the maximum counter value of the maximum width minimum width guarantee circuit 5 is output.
In step 5, the switch 8 of the clamp pulse generator 7 is turned off to terminate the pull-in of the clamp level.

As described above, in the present embodiment, in controlling the clamp level output period corresponding to the video signal S1, the video signal S1 obtained by digitally converting the signal S7
The clamp output is controlled in accordance with the level difference between the output level and the first reference level. Further, in order to add a limit of the maximum value and the minimum value to the clamp level output period, the selector 6 can select the clamp level output period controlled from the video signal S1 or the period of the maximum value or the minimum value.

In the above-described embodiment, the rising of the signal is detected. However, the same can be realized by detecting the falling.

In short, as is apparent from the above-described embodiments, the present invention directly inputs a video signal to a detector and detects a clamp period, whereby an abnormal video signal different from a normal one is detected. Even when an input is made, it is possible to secure a clamp width for obtaining a stable clamp level.

[0049]

As described above, the clamp circuit of the present invention detects the rising of the horizontal synchronizing signal and the rising of the video signal received together with the video signal, or the level difference of the video digital signal, and detects the maximum width and the minimum width. By adding an output period using a selector before and after the period signal guaranteed by the guarantee circuit, the clamp width can be changed by the video signal and a sufficient clamp level can be drawn in, so that a stable clamp can be obtained. There is an effect that a sufficient period for adjusting the clamp level can be obtained when obtaining the level.

Further, the clamp circuit of the present invention eliminates the need to use an amplifier having a high amplification factor by extending the period of pulling in the clamp level from the clamp pulse generating circuit by the selector, thereby simplifying the circuit configuration. In addition, it can be formed at low cost, and has an effect that a highly accurate clamp can be performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a clamp circuit for describing an embodiment of the present invention.

FIG. 2 is a signal waveform diagram in a case where the video signal in FIG. 1 has no noise and in a case where the video signal is superimposed.

FIG. 3 is a signal waveform diagram when a video signal in FIG. 1 has no luminance signal for a long time.

FIG. 4 is a configuration diagram of a clamp circuit for explaining another embodiment of the present invention.

FIG. 5 is a diagram illustrating signal waveforms when the video signal in FIG. 4 has no noise and is superimposed.

6 is a signal waveform diagram when a video signal in FIG. 4 has no luminance signal for a long time.

FIG. 7 is a configuration diagram of a clamp circuit for explaining still another embodiment of the present invention.

8 is a signal waveform diagram in a case where the video signal in FIG. 7 has no noise and is superimposed.

9 is a signal waveform diagram when the video signal in FIG. 7 has no luminance signal for a long time.

FIG. 10 is a diagram showing a block configuration of a clamp circuit and a video signal waveform showing an example of the related art.

FIG. 11 is a clamp circuit diagram showing another example of the related art.

12 is a diagram showing signal waveforms for lowering and raising the clamp level in FIG. 11 and signal waveforms for explaining a convergence period.

[Explanation of symbols]

 1, 1A, 1B Analog circuit 2 Clamp circuit 3, 4 Edge detector 5 Maximum width / minimum width guarantee circuit 6 Selector 7 Clamp pulse generator 8 Switch 9 Amplifier 10 Differential pulse detector 13 Digital comparator S1 Analog video signal S2 Horizontal Synchronization signal S3 Clamp level output start control signal S4 Clamp level output end control signal S5 Maximum width minimum width guarantee period signal S6 Clamp level control signal

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-331978 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N 5/18

Claims (3)

(57) [Claims] A first edge detector for detecting a falling edge or a rising edge of a horizontal synchronizing signal and starting output of a clamp level;
Alternatively, a second edge detector for detecting a falling edge and terminating the output of the clamp level, and a maximum / minimum width for guaranteeing a maximum period and a minimum period of start and end of the clamp level output based on the horizontal synchronization signal Guarantee circuit,
One of a period from the start to the end of the clamp level output of the first and second edge detectors and a clamp level output period guaranteed by the maximum / minimum width guarantee circuit are self-determined and selectively output. A clamp circuit, comprising: a selector; and a clamp pulse generator that generates a clamp pulse for the video signal in response to the selection output, and controls a period for outputting the clamp level in accordance with the video signal. 2. A first reference level for observing a change in a voltage level of a video signal is set. When a voltage level exceeding the first reference level is detected, a differential pulse is generated, and a rise of the differential pulse is generated. Alternatively, a differential pulse generator for detecting the falling edge and starting the output of the clamp level, and a second reference level for observing a change in the voltage level of the video signal are set, and a voltage exceeding the second reference level is set. An edge detector for terminating the output of the clamp level when a level is detected; a maximum / minimum width guarantee circuit for guaranteeing the maximum and minimum periods for starting and ending the clamp level output based on a horizontal synchronization signal; The period from the start to the end of the clamp level output by the pulse generator and the edge detector, and the clamp by the maximum / minimum width guarantee circuit. A selector for self-determining and selectively outputting any one of the level output periods; and a clamp pulse generator for generating a clamp pulse for the video signal based on the selected output. A clamp circuit, wherein the control is performed in response to the video signal. 3. A digital signal obtained by A / D-converting a video signal is compared with first and second reference levels set in advance, and when the digital data exceeds the first reference level, a clamp level output is output. A digital comparator for starting and terminating the clamp level output when exceeding the second reference level, and a maximum / maximum period for guaranteeing the maximum and minimum periods of the start and end of the clamp level output based on the horizontal synchronization signal. A small-width guarantee circuit, and a selector for self-determining and selecting and outputting one of a period from a start to an end of a clamp level output in the digital comparator and a clamp level output period in the maximum / minimum width guarantee circuit. And a clamp pulse generator for generating a clamp pulse for the video signal in accordance with the selected output. A clamp circuit for controlling a period during which a bell is output in accordance with the video signal.