JP2941156B2 - Line pattern drawing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

(Table of Contents) Industrial application field Conventional technology (FIGS. 20 to 24) Problems to be Solved by the Invention Means for Solving the Problems (FIG. 1) Operation (FIG. 1) First Embodiment First Embodiment Description of Examples (FIGS. 2 to 14) ・ Description of Second Embodiment (FIGS. 2, 15 to 19)

[0002]

The present invention relates are different host computer or we enter the model, the printing operation in response to signals of different formats is applied in general printer devices such as performed, the line pattern on the drawing how.

[0003]

2. Description of the Related Art For example, in order to draw a line such as an underline or an overline by a printer connected to an electronic computer, a control unit of the printer is generally similar to a bitmap font (character information). In addition, the above line information is held as a bit pattern, and printing can be performed by logically drawing the line information in a bit map memory.

FIG. 20 is a block diagram showing a printer employing a general line pattern drawing method. The printer shown in FIG. 20 has a main control section (control section) for controlling internal processing operations. ) 101, an interface unit 102 for exchanging data with the outside, and a bitmap memory (BMM) for logically drawing print data
103, a line pattern drawing unit 104 that logically draws a line pattern in the bitmap memory 103, a bit pattern storage unit 105 that stores a line pattern as bit information, and contents drawn in the bitmap memory 103. And a print control unit 106 for controlling the printing of the print data.

Here, it is assumed that data stored in the bitmap memory 103 has one dot of image data per bit, a bit indicating a solid line is “1”, and a bit indicating a blank portion is “0”. I do. In the bit pattern storage unit 105, for example, all 32 bits as shown in FIG.
And a blank portion bit pattern in which 8-bit solid lines (shaded portions) and 8-bit blank portions are alternately arranged as shown in FIG. I have.

With this configuration, for example, based on a data signal input to the main control unit 101 via the interface 102, for example, as shown in FIG. When drawing a line pattern of a dash-dot line pattern in which one cycle is constituted by a solid line of dots and a blank portion of 8 dots, a solid line bit pattern and a blank portion bit pattern stored in the bit pattern storage unit 105 are drawn. The pattern drawing unit 104 draws data alternately on the bitmap memory 103. As a result, the print control unit 106 prints the line pattern drawn in the bitmap memory 103 as shown in FIG.

[0007]

However, in the case where the above-described method is adopted, when a line pattern having a long cycle such as one cycle of 128 dots as shown in FIG. 24 (a) to 2
4 (d), many bit patterns must be stored in advance, and the bit pattern storage unit 105
However, there is a problem that the capacity of the device becomes large.

When a bit pattern is drawn in the bit map memory 103 by the line pattern drawing unit 104, data is written in units of 8 bits or multiples of the bit due to its nature. There is also a problem that it is difficult to draw a line pattern having an arbitrary cycle, such as a one-dot chain line, in which only one cycle of the line pattern is configured in units of 8 bits or multiple bits thereof. is there.

[0009] The present invention has been in view conceived of such a problem, along with minimizing the bit pattern previously held, the line pattern drawing how to enable the drawing of the line pattern having an arbitrary cycle The purpose is to provide.

[0010]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, reference numeral 1 denotes a solid bit pattern 1A in which all bits of a predetermined number of bits are "1";
This is a bit pattern storage means for storing in advance a blank portion bit pattern 1B in which a blank portion bit having a fixed length is set to "1" and other portions are set to "0".

Reference numeral 2 denotes a line pattern logical drawing means for logically drawing a line pattern in the bit map memory 9 for each bit pattern having a predetermined number of bits as one unit. It is a counting means for counting the number of bits of the obtained bit pattern. When the determination unit 3 of the line pattern logic drawing unit 2 determines that the bit pattern from the bit pattern storage unit 1 is a solid line portion of the line pattern according to the count value from the counting unit 8, In the logic drawing section 4, the solid line bit pattern is logically drawn as it is in the bit map memory 9, and the counting means 8 counts up by a predetermined number of bits.

On the other hand, when the determination unit 3 of the line pattern logic drawing unit 2 determines that the bit pattern from the bit pattern storage unit 1 is a portion including a blank portion of the line pattern according to the count value from the counting unit 8. Is
The shift unit 5 shifts the blank bit of the blank bit pattern according to the count value of the counting unit 8, and the exclusive OR operation unit 7 performs an exclusive OR operation between the shifted blank bit pattern and the solid line bit pattern. The bit pattern is logically drawn in the bit map memory 9 by taking a logical sum, and the counting means 8 counts up by a predetermined number of bits.

Thus, a line pattern having a blank portion of a fixed length can be logically drawn on the bit map memory 9 synchronously (claim 1). Further, in accordance with the count value of the counting means 8, the shift unit 5 shifts the blank bit of the blank bit pattern for each blank to create two or more blank bit patterns corresponding to each blank. The OR operation unit 6 calculates the OR of these two or more blank part bit patterns, and the exclusive OR operation unit 7 calculates the exclusive OR of the result of the OR operation and the solid line bit pattern. Pattern
The logic drawing unit 4 performs logical drawing on the bitmap memory 9 and counts up the counting unit 8 by a predetermined number of bits. Logic drawing can be performed on the map memory 9 (claim 2).

Further, in the above case, if the count value of the counting means 8 exceeds the number of cycle bits corresponding to the cycle of the line pattern, the number of cycle bits can be subtracted from the count value of the counting means 8 ( (Claim 3) Further, the count value of the counting means 8 can be corrected by the correcting means 10 at every arbitrary cycle of the line pattern (Claim 4).

[0015]

According to the present invention, when a line pattern having a blank portion of a fixed length is synchronously drawn, a solid line bit pattern 1A in which all bits of a predetermined number of bits are "1";
The blank portion bit pattern 1B , in which the blank portion bit of the fixed length is set to “1” and the other portions are set to “0”, is stored in the bit pattern storage means 1 in advance.

The counting means 8 counts the number of bits of the bit pattern logically drawn in the bit map memory 9. In the line pattern logic drawing means 2, for the solid line portion of the line pattern, the solid line bit pattern is logically drawn as it is in the bit map memory 9 , and the counting means 8 is counted up by a predetermined number of bits. For the portion including the bit, the blank portion bit of the blank portion bit pattern is shifted according to the count value of the counting means 8, and then the bit obtained by taking the exclusive OR of the shifted blank portion bit pattern and the solid line bit pattern The pattern is logically drawn in the bit map memory 9 and the counting means 8 counts up by a predetermined number of bits.

Thus, a line pattern is logically drawn in the bitmap memory 9 for each bit pattern having a predetermined number of bits as one unit, and then the logically drawn line pattern is printed in the bitmap memory 9. In addition, for a portion including two or more blank portions in a bit pattern of a predetermined number of bits, according to the count value by the counting means 8,
The blank bit of the blank bit pattern is shifted for each blank portion to generate two or more blank bit patterns corresponding to each blank portion, and the result of the logical sum of these two or more blank bit patterns is calculated. The bit pattern obtained by taking the exclusive OR with the solid line bit pattern is logically drawn in the bit map memory 9 and the counting means 8 counts up by a predetermined number of bits.

Further, when the count value of the counting means 8 exceeds the number of cycle bits corresponding to the cycle of the line pattern, the number of cycle bits can be subtracted from the count value of the counting means 8 and any number of line patterns can be set. It is also possible to correct the count value by the counting means 8 for each cycle of.

[0019]

(A) Description of First Embodiment First, a first embodiment of the present invention will be described. FIG. 2 is a block diagram showing a printer apparatus applied to the embodiment of the present invention. In FIG. 2, reference numeral 11 denotes a main control unit for controlling internal processing operations, and 12 denotes data exchange with the outside of the apparatus. An interface 13 is a bitmap memory (BMM) for logically drawing print data.

Reference numeral 16 denotes a line pattern drawing unit. The line pattern drawing unit 16 draws a line pattern logically in the bit map memory 13. For example, a line pattern drawing unit 16 Logical drawing is performed as a pattern. Reference numeral 17 denotes a bit pattern storage unit. The bit pattern storage unit 17 stores a solid line bit pattern and a blank part bit pattern for logically drawing a line pattern in the line pattern drawing unit 16.

For example, when a line pattern composed of a solid line of 68 dots, a blank portion of 13 dots, a solid line portion of 13 dots, and a blank portion of 13 dots as shown in FIG. Is a solid line bit pattern in which all bits of 32 bits as shown in FIG. 5A are set to “1”, and a blank bit pattern is
In the 32 bits shown in (b), a blank portion of a fixed length (13 bits in this case) is set to “1”, and the rest is set to “0”.

Reference numeral 18 denotes a drawing counter. The drawing counter 18 counts the period of a line pattern logically drawn in the bit map memory 13 by the number of bits. 16 is output. Since the line pattern can be written from an arbitrary phase, the count value as an initial value can be set arbitrarily.

In this case, the line pattern is 3
Bit map memory 13 for each 2-bit bit pattern
Since the logical drawing is performed, the count value of the drawing counter 18 is also counted up (incremented) by “32”. Reference numeral 19 denotes a print control unit that performs control for printing the contents logically drawn on the bitmap memory 13.

Here, focusing on the functions of the main control section 11 and the line pattern drawing section 16, it has a configuration as shown in FIG. That is, in FIG. 3, reference numeral 21 denotes a line drawing control unit (determination unit, logical drawing unit, logical sum operation unit). The line drawing control unit 21 controls the logical drawing of a line pattern. It has a function as the control unit 11 and the line pattern drawing unit 16.

More specifically, the input drawing counter 18
The phase of the line pattern logically drawn in the bitmap memory 13 is determined based on the count value information from
Based on this determination result, the line pattern is logically drawn using the solid line bit pattern or the blank bit pattern stored in the bit pattern storage unit 17.

For example, when performing logical drawing of a line pattern in the line drawing control section 21, FIG.
When the solid line bit pattern shown in FIG. 5A is used, the logical drawing is directly performed on the bit map memory 13 as shown in FIG.
In the case where the blank bit pattern shown in (b) is used, a bit shift unit 22, an exclusive OR operation unit 23, and a line drawing control unit 2, which will be described later, according to the phase of the line pattern.
1 and the logical drawing is performed.

The bit shift unit (shift unit) 22 shifts the bit of the blank part bit in the blank part bit pattern from the bit pattern storage unit 17 based on the count value information as the phase determination result from the line drawing control unit 21. Things. The exclusive OR operation unit 23
Calculates the exclusive OR of the blank part bit pattern shifted by the bit shift unit 22 and the solid line bit pattern, and uses the calculation result as a bit pattern for logically drawing a line pattern including a blank part. This is output to the control unit 21.

For example, when the line pattern shown in FIG. 4 is logically drawn, the drawing counter 18 is used to logically draw the 68-dot solid line portion of the writing portion.
Is set to "0", the drawing counter 18 is counted up by "32" for the first 64 bits, and the process of logically drawing the solid line bit pattern shown in FIG. 5A is performed twice. The count value of the drawing counter 18 is "64", but when the next 32 bits are logically drawn, the drawing counter 18 is counted up to "96", and the blank portion bit pattern shown in FIG. , And a bit shift unit 22 (see FIG. 6 (a)) and a bit shift unit 30 (see FIG. 6 (b)). (See FIG. 7), and the exclusive OR of this operation result and the solid line bit pattern is calculated by the exclusive OR operation unit 23 (see FIG. 8). By outputting a non-line pattern in the line drawing control unit 21 as the bit pattern for the logic drawing, the line pattern is to logical drawing.

By the way, in the above case, the drawing counter 18 is counted up to "128" and bit-shifted based on the count value, as in the case of FIGS. 6 (a) and 6 (b). [Refer to FIG. 9 (a)], calculation result of exclusive OR operation [Refer to FIG. 9 (b)]
Are logically drawn in the bitmap memory 13.

If the count value exceeds "107", it means that one cycle of the line pattern has been drawn. Therefore, if the count value is counted up to "128", one cycle of the count value is subtracted from this count value. Is subtracted from “107” to obtain “21”. Thereafter, in each cycle after the first cycle, similarly to the case of the first cycle described above, when the drawing counter 18 counts up as shown in FIG. Logical drawing is performed on the memory 13.

Accordingly, the line drawing control unit 21, the bit shift unit 22, and the exclusive OR operation unit 23
It constitutes a line pattern logic drawing means. The operation of the first embodiment of the present invention having the above configuration will be described below with reference to the flowcharts shown in FIGS. When the line pattern is drawn from the beginning, the count value of the drawing counter 18 is set to “0” as an initial value.

First, when the line drawing control section 21 performs logical drawing of a line pattern on the bit map memory 13, the drawing counter 18 is counted up (step A1). In this case, since the logical drawing is performed every 32 bits, "32" is counted up and the count value becomes "32". Then, based on the bit pattern and the count value information stored in the bit pattern storage unit 17 and the drawing counter 18, the desired solid line is operated by the operations of the line drawing control unit 21, the bit shift unit 22, and the exclusive OR control unit 23. A bit pattern or a blank bit pattern is created (step A
2) The logical drawing is performed on the bit map memory 13 (step A3). For example, when the portion including the blank portion of the line pattern shown in FIG. 12 to 1 to be described later.
As shown in FIG.

Next, the line drawing control section 21 determines whether or not one cycle of drawing has been performed on the bitmap memory 13 based on the count value from the drawing counter 18 (step A4). Is completed, the count value for one cycle is subtracted from the count value of the drawing counter 18 (step A5). For example, as described above, when the line pattern shown in FIG. 4 is logically drawn, the count value “128” of the drawing counter 18
The count value “107” for one cycle is subtracted, and the count value is set to “21”.

In step A4, the bit map memory 13
If the drawing for one cycle has not been completed, or if the count value for one cycle has been subtracted in step A5, the line drawing control unit 21 specifies the point where the drawing was performed at the specified drawing end point. It is determined whether or not it is the drawing end point (step A6). If it is not the drawing end point, the process proceeds to step A1, and the logical drawing is performed until the drawing is completed.

Next, paying attention to the case where the line pattern shown in FIG. 4 includes a blank portion in the case of logical drawing, the procedure for creating this blank portion bit pattern will be described with reference to FIGS. The processing in FIGS.
This is supported regardless of the cycle of the logical drawing of the line pattern. That is, in the line pattern shown in FIG. 4, the writing start 68 dots are solid line bit patterns, but the count values are “69” to “9” in step B10 in the flowchart of FIG.
If it is determined that the value falls within the range of "4", the bit shift unit 22 creates a blank bit pattern bit-shifted to the right (step B11), and exclusive ORs the operation result with the solid line bit pattern. Is calculated by the exclusive OR operation unit 23 (step B12), and the operation result is used for logical drawing of the line pattern. Subsequent processing is performed at step A in the flowchart of FIG.
Move to 3.

Further, if the count value is not determined to be in the range of "6 9" - "94" in step B20 in the flowchart of FIG. 12, the count value is "9
If it is determined that the value is in the range of “5” to “100”, the bit shift unit 22 creates a first blank portion bit pattern bit-shifted to the right (step B2).
1) A second blank bit pattern shifted to the right is created (step B22). Then, the line drawing controller 21 calculates the logical sum of the first and second blank portion bit patterns (step B23), and calculates the exclusive logical sum of the calculation result and the solid line bit pattern.
An operation is performed in the exclusive OR operation unit 23 (step B2
4) The calculation result is used for logical drawing of a line pattern. Thereafter, the process proceeds to step A3 in the flowchart of FIG.

The count value is "95" to "100".
If it is determined that the count value is not within the range of “101” to “112” in step B30 in the flowchart of FIG. Create a shifted first blank bit pattern (step B
31) Then, a second blank portion bit pattern shifted to the right is created (step B32). Then, the line drawing control unit 21 calculates the logical sum of the first and second blank portion bit patterns (step B33).
The exclusive OR of this operation result and the solid line bit pattern is calculated in the exclusive OR operation unit 23 (step B34), and this operation result is used for drawing the logic of the line pattern. To step A3.

The count values are "101" to "11".
If it is determined that the count value is not in the range of “2”, the bit shift unit 22 determines that the count value is in the range of “113” to “126” in step B40 in the flowchart of FIG. (Step B4)
1) The exclusive OR of this operation result and the solid line bit pattern is calculated by the exclusive OR operation unit 23 (step B42), and the operation result is used for drawing the logic of the line pattern. Thereafter, the process proceeds to step A3 in the flowchart of FIG.

The count value is "113" to "12".
If it is determined that the count value is not in the range of “127” to “138” in step B40 in the flowchart of FIG. To create a blank bit pattern that is bit shifted (step B5).
1) The exclusive OR of this operation result and the solid line bit pattern is calculated in the exclusive OR operation unit 23 (step B52), and this operation result is used for drawing the logic of the line pattern. Thereafter, the process proceeds to step A3 in the flowchart of FIG.

As described above, when the bit pattern including the blank portion of the line pattern is created, the drawing counter 18 counts up as shown in FIG. 10 in each cycle of the logical drawing operation of the line pattern. ,
Logical drawing is performed on the bitmap memory 13 in a line pattern as shown in FIG. As described above, according to the first embodiment of the present invention, if the blank portion of the line pattern is set to a fixed length, the number of bit patterns held in advance can be suppressed to two types, and a line pattern having an arbitrary period can be saved. There is an advantage of enabling drawing.

Although the line drawing control unit 21 in this embodiment logically draws a line pattern in the bitmap memory 13 every 32 bits, the present invention is not limited to this. Alternatively, a line pattern may be logically drawn every 8 bits. (B) Description of Second Embodiment Next, a second embodiment of the present invention will be described.

The printer according to the second embodiment of the present invention can be applied to a printer as shown in FIG. 2, but the main controller 11, the interface 12, the bit map memory 13, the line Pattern drawing unit 16, bit pattern storage unit 17, and print control unit 1
9 has the same configuration as that of the first embodiment described above, except that the drawing counter 18 has a correction unit 24 as a means for correcting the count value.

FIG. 15 is a diagram showing a second embodiment of the present invention, in which attention is paid to the functions of the main control unit 11 and the line pattern drawing unit 16 in FIG. 2 shown in the first embodiment.
It corresponds to that shown in FIG. That is, as shown in FIG. 15, a line drawing control unit (judgment unit, logic drawing unit, logical sum operation unit) 21 and a bit shift unit (shift unit) 22 having the same functions as those shown in FIG. ,
An exclusive OR operation unit 23, a bit map memory 13, a bit pattern storage unit (bit pattern storage unit) 17, and a drawing counter 18 are provided.

The correction section (correction means) 24 corrects the count value of the drawing counter 18 at every arbitrary cycle of the line pattern, and counts the number of subtraction processing performed at each cycle. 24a, the count value is set to "0" as an initial value at the time of writing the line pattern.

More specifically, when the line pattern as shown in FIG. 4 is logically drawn as in the first embodiment, a line pattern of 321 dots can be drawn in three periods. As shown, 320 dots
When a line pattern having a cycle is realized, the correction unit 24 determines that the count value is 1 at the end of the third cycle.
By subtracting the count value “1” for one dot after subtracting the subtraction value “107” for the cycle, the number of dots is set to “106” in the third cycle.

That is, as shown in FIG. 17, the drawing dot pattern corresponding to the count value of the drawing counter 18 is one dot smaller at the end of three cycles than in the first embodiment (see FIG. 10). deviation is but at the end of the third period, the count value of one dot "1"
Since the correction is performed by the addition, the line pattern is logically drawn at the start of the fourth cycle, similarly to the first cycle.

Therefore, after that, the line pattern is logically drawn in the same manner as in the first to third cycles. The operation of the second embodiment of the present invention having the above configuration will be described below with reference to the flowcharts shown in FIGS. In FIG. 18, at step C1, similarly to step A1 in the flowchart of FIG. 11 described in the first embodiment, the drawing counter 18
Is counted up.

Then, in step C2 and step C3, respectively, as described in the first embodiment, FIG.
A2 and A3 in the flowchart of FIG.
Similarly, the bit pattern is created, and the line pattern is logically drawn in the bit map memory 13. When the line pattern is logically drawn in the bitmap memory 13 in step C3, it is determined whether or not one cycle of drawing has been performed in the bitmap memory 13 as in step A4 in the flowchart of FIG. 11 (step C3).
4) When one cycle is completed, the count value of one cycle is subtracted from the count value of the drawing counter 18 (step A5), and a correction process by the correction unit 24 as shown in FIG. 19 is performed.

That is, in the correction processing by the correction section 24, the count value of the subtraction processing number counter 24a is incremented by "1" to count up (step D1). When the count value of the subtraction processing number counter 24 becomes “3”, three cycles of logical drawing are performed, and the subtraction processing of the count value “107” for one cycle to the drawing counter 18 is performed. Assuming that the count has been performed three times, the count value of the drawing counter 18 on which the subtraction process has been performed is corrected by adding "1", and the count value of the subtraction process counter 24a is initialized (step D3).

In step D2, if the count value is less than "2", or if the drawing counter 1 in step D3
After the correction of the counter value of 8 is performed, the process proceeds to step C7 similar to step A6 described above, and the line drawing control unit 21 determines whether the point where the drawing is performed is the designated drawing end point. (Step C7) If it is the drawing end point, the drawing is terminated. If it is not the drawing end point, the process proceeds to Step C1, and the logical drawing is performed until the drawing is completed.

As described above, according to the second embodiment of the present invention, in addition to the effects obtained in the first embodiment, in addition to the effects obtained in the first embodiment, the line Logical drawing of patterns. In the present embodiment, the line drawing control unit 21 logically draws a line pattern in the bitmap memory 13 for every 32 bits. However, according to the present invention, the present invention is not limited to this.
The line pattern may be logically drawn in units of bits or 8 bits.

In the present embodiment, the correction value of the drawing counter 18 by the correction unit 24 is set to "1". However, according to the present invention, the correction value is not limited to this, and the dot value when a line pattern is drawn An arbitrary correction value can be selected according to the number.

[0053]

As described in detail above, according to the present invention,
There are the following effects and advantages. (1) If the blank portion of the line pattern has a fixed length, the number of bit patterns held in advance can be suppressed to two types, and a line pattern having an arbitrary period can be drawn.

(2) A line pattern can be logically drawn according to the number of dots when drawing the line pattern.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram illustrating a printer device applied to an embodiment of the present invention.

FIG. 3 is a block diagram focusing on functions of a main control unit and a line pattern drawing unit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a line pattern to be drawn in the first embodiment of the present invention.

FIGS. 5A and 5B are diagrams illustrating bit patterns stored in a bit pattern storage unit according to the first embodiment of the present invention.

FIGS. 6A and 6B are diagrams for explaining a procedure for creating a bit pattern including a blank portion according to the first embodiment of the present invention.

FIG. 7 is a diagram for explaining a method of creating a bit pattern including a blank portion according to the first embodiment of the present invention.

FIG. 8 is a diagram for explaining a method of creating a bit pattern including a blank portion according to the first embodiment of the present invention.

FIGS. 9 (a) and 9 (b) are diagrams for explaining a method of creating a bit pattern including a blank portion in the first embodiment of the present invention.

FIG. 10 is a diagram illustrating a count value of a drawing counter and a dot pattern according to the first embodiment of the present invention.

FIG. 11 is a flowchart illustrating the operation of the first embodiment of the present invention.

FIG. 12 is a flowchart illustrating a procedure for creating a bit pattern including a blank portion according to the first embodiment of the present invention.

FIG. 13 is a flowchart illustrating a procedure for creating a bit pattern including a blank portion according to the first embodiment of the present invention.

FIG. 14 is a flowchart illustrating a procedure for creating a bit pattern including a blank portion according to the first embodiment of the present invention.

FIG. 15 is a block diagram focusing on functions of a main control unit and a line pattern drawing unit according to a second embodiment of the present invention.

FIG. 16 is a diagram showing a line pattern to be drawn in a second embodiment of the present invention.

FIG. 17 is a diagram illustrating a count value of a drawing counter and a dot pattern according to a second embodiment of the present invention.

FIG. 18 is a flowchart for explaining the operation of the second embodiment of the present invention.

FIG. 19 is a flowchart illustrating a correction process performed by a correction unit according to the second embodiment of the present invention.

FIG. 20 is a block diagram illustrating a printer apparatus that employs a general line pattern drawing method.

FIG. 21 is a diagram showing an alternate long and short dash line as a line pattern.

FIGS. 22A and 22B are diagrams showing bit patterns stored in a bit pattern storage unit in a printer device employing a general line pattern drawing method.

FIG. 23 is a diagram showing a two-dot chain line as a line pattern.

FIGS. 24A to 24D are diagrams illustrating a general method of realizing a line pattern.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Bit pattern storage means 1A Solid line bit pattern 1B Blank part bit pattern 2 Line pattern logic drawing means 3 Judgment part 4 Logic drawing part 5 Shift part 6 OR operation part 7 Exclusive OR operation part 8 Counting means 9 Bit map memory 10 Correction unit 11 Main control unit 12 Interface unit 13 Bit map memory 16 Line pattern drawing unit 17 Bit pattern storage unit (bit pattern storage unit) 18 Drawing counter (counting unit) 19 Print control unit 21 Line drawing control unit 22 Bit shift unit 23 Exclusive OR operation unit 24 Correction unit 24a Subtraction processing number counter 101 Main control unit 102 Interface unit 103 Bitmap memory 104 Line pattern drawing unit 105 Bit pattern storage unit 106 Print control unit

Continuation of the front page (56) References JP-A-1-205285 (JP, A) JP-A-4-47383 (JP, A) JP-A-61-193197 (JP, A) JP-A-61-55691 (JP, A) JP-A-62-156778 (JP, A) JP-A-62-49569 (JP, A) JP-A-5-135182 (JP, A) JP-A-5-205001 (JP, A) 2-264378 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06T 11/20

Claims (4)

(57) [Claims] 1. A line pattern for each bit pattern to a unit of predetermined number of bits from the logic drawn to the bitmap memory, the line pattern drawing direction to print the logical drawn line patterns to the bitmap memory Act smell <br/> Te, when drawing a line pattern having a blank portion of the synchronously constant length, all the bits of the predetermined number of bits and the solid bit pattern as "1", the predetermined length The blank part bit is set to “1”,
Other parts with pre-stored and a blank portion bit pattern "0", provided with a counting means to count the number of bits of the bit pattern obtained by logically drawn on the bit map memory, the solid line portion of the line pattern is the said actual line bit pattern as logically drawn on the bit map memory, while the counting hand stage is incremented by the predetermined number of bits, the portion including the blank portion of the line pattern, the counting hand stage the air spaces unit bit of the white part bit patterns from the shift, the blank part bit pattern and the bit map NOTE bit pattern taking the exclusive OR between said actual line bit pattern after the shift in accordance with the count value by Re
Logic drawing to, characterized in that it counts up the count hand stage only the predetermined number of bits, the line pattern drawing how to. 2. The method according to claim 1, wherein the predetermined number of bits in the bit pattern is two.
The portion including the blank part of the above, according to the count value by <br/> to the count hand stage, corresponding to the blank portion by shifting a blank portion bits of the air white part bit patterns for each blank part after creating two or more blank part bit patterns, logic bit pattern taking the exclusive oR of the logical oR result and said actual line bit pattern of these two or more white space bit pattern to the bit map memory drawing to, characterized in that it counts up the count hand stage only the predetermined number of bits, the line pattern drawing how according to claim 1. 3. A count value by the counting hand stage, if it exceeds the number of cycles bits corresponding to the period of the line pattern, characterized by subtracting the said periodic bit number from the count value by the counting hand stage to the line pattern drawing how according to claim 1 or 2. Wherein each optional period of the line pattern, and correcting the count value by the counting hand stage, the line pattern drawing how according to any one of claims 1 to 3 .