JP3144807B2 - Access frequency calculation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bit map memory .
Access times to calculate access times when writing data
The present invention relates to a numerical operation circuit .

[0002]

2. Description of the Related Art In general, a bit map memory is used to hold display data on a bit map display. Is determined by

For this reason, the bit width of the storage area of the bit map memory is often different from the drawing width of the CPU. Here, the drawing width of the CPU is the width of the data bus, and is a unit of drawing in the bitmap memory. Further, in the bitmap memory, only one specific storage area addressed by the CPU can be written by one access.

Therefore, for example, when the drawing width of the CPU is larger than the bit width of the storage area of the bitmap memory, the drawing target extends over a plurality of storage areas. Data cannot be written to the bitmap memory, and access must be repeated several times. Therefore, there is a problem that the CPU must always be aware of the drawing width and the bit width of the bitmap memory in order to determine the number of accesses to the bitmap memory. This is a major factor in lowering the drawing speed.

[0005]

Conventionally, the CPU must always be aware of the bit width of the bit map memory, which has the disadvantage that the drawing speed is reduced.

[0006] The invention has been made in view of the above problems, the number of accesses that can be drawn data at high speed without to automatically determined the number of accesses, aware of the bit width of the bit map memory It is an object to provide an arithmetic circuit .

[0007]

According to the present invention , each of the circuits for calculating the number of accesses has a predetermined bit width.
Write to bitmap memory with multiple storage areas
Holds the value of the drawing start bit position when drawing only data
Means for writing, and the letter to be drawn in the bitmap memory.
Means for holding a value of a drawing width of the writing data;
Start bit position value and write data drawing width value
And the value of the last bit position of the write data
And a subtractor having first and second inputs.
An arithmetic circuit, wherein the write operation is performed on the first input terminal.
First drawing of only data to the bitmap memory
In the case of a picture, the output value of the addition circuit is input,
When drawing the descending, the value of the subtraction result is input and
The second input terminal is stored in the bitmap memory.
The value of the bit width of the storage area is input and the first
Input from the input terminal to the second input terminal;
A subtraction circuit for subtracting the subtracted value, and a subtraction result of the subtraction circuit.
Detecting that it has become zero or less and terminating the drawing operation
And a sequencer for outputting a control signal for
Features.

In this drawing method, a drawing start bit position specified by the CPU and a drawing width of data by the CPU are added to obtain a final bit position to be drawn. When drawing data in the bitmap memory, the value of the bit width of the storage area of the bitmap memory is subtracted from the value of the last bit position for each drawing, and drawing is repeated until the result of the subtraction becomes zero or less. . Therefore, the number of accesses is automatically obtained only by specifying the drawing start bit position, so that data can be drawn without being aware of the bit width of the bitmap memory.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of an access number calculation circuit for realizing a drawing method according to an embodiment of the present invention. This circuit is for automatically calculating the number of accesses to the bitmap memory and controlling the write operation, and forms a part of a memory controller that executes drawing of data to the bitmap memory.

The access number calculation circuit includes a dot address register 11, a drawing width register 12, and an addition circuit (ADD).
R) 13, a selector 14, a subtraction circuit (SUB) 15, a current register 16, a zero detection circuit 17, and a sequencer 18.

The dot address register 11 holds a drawing start address of a bit map memory specified by the CPU. This drawing start address specifies which bit position in the bitmap memory to start drawing. When the storage area of the bitmap memory is composed of 8 bits, it is composed of a 3-bit address signal. You.

The drawing width register 12 is for holding a drawing width (number of drawing dots) when the CPU draws data in the bit map memory, and the value of the drawing width is connected to the CPU. Is determined by the width of the data bus. For example, when the width of the data bus is 16 bits, the drawing width is 16 bits, and the drawing width is represented by 5-bit data.

An adder (ADDR) 13 adds the value of the drawing start address held in the dot address register 11 and the value of the drawing width held in the drawing width register 12. This addition result corresponds to a value indicating the last bit position of the drawing target. The selector 14 selects one of the addition result of the addition circuit (ADDR) 13 and the value held in the current register 16 and supplies the selected result to the first input of the subtraction circuit (SUB) 15. When drawing an image, an adder circuit (AD
DR) 13 is selected, and thereafter the value held in the current register 16 is selected.

A subtraction circuit (SUB) 15 subtracts the value supplied to the second input from the output of the selector 14 supplied to the first input. The value supplied to the second input is data indicating the bit width (8 bits) of each storage area of the bitmap memory. The subtraction result of the subtraction circuit (SUB) 15 is stored in the current register 16.

The zero detection circuit 17 detects that the subtraction result of the subtraction circuit (SUB) 15 has become zero, and notifies the sequencer 18. The sequencer 18 controls the data write operation to the bit map memory, and performs drawing when a zero detection signal is supplied from the zero detection circuit 17 or when a borrow output is generated from the subtraction circuit (SUB) 15. End the operation. Next, with reference to FIG. 2, an operation of the access number operation circuit of FIG. 1 and an operation of writing data to the bit map memory will be described. Here, CPU
Is 16 bits, and the bit width of each storage area of the bitmap memory is 8 bits.

Now, assuming that the CPU draws 16-bit data from the fifth bit (bit of address 4) of the first address (the storage area of address 1) of the bit map memory, the dot address register 11 stores the drawing start bit. Data “04” H (H; hexadecimal notation) is set as the position, and data “10” H is set in the drawing width register 12.

In this case, the addition result D of the addition circuit (ADD) 13 is "14" H. When the first access is executed, 4-bit data is written to the address 1 (the storage area of the address 1) of the bit map memory, as indicated by oblique lines. In this first access, the selector 14 selects the data "14" H, which is the addition result of the addition circuit (ADD) 13, and the data "14" H- "8" H "in the subtraction circuit (SUB) 15. Is subtracted. The value “0C” H of this subtraction result is stored in the current register 16. As described above, since the subtraction result is a positive value in the first access, the second access is started.

In the second access, 8-bit data is written to address 2 (the storage area of address 2) of the bit map memory. In the second access, the value “0C” held in the current register 16 is used.
H is selected by the selector 14, and the subtraction circuit (SUB) 15 subtracts “0C” H− “8” H ”. The value “04” H of this subtraction result is stored in the current register 16. As described above, since the subtraction result is a positive value even in the second access, the third access is started.

In the third access, 4-bit data is written to address 3 (the storage area of address 3) of the bit map memory. In the third access, the value “04” held in the current register 16 is used.
H is selected by the selector 14, and the subtraction circuit (SUB) 15 performs subtraction of "04" H- "8" H ". As a result of this subtraction, a borrow output (B) is generated from the subtraction circuit (SUB) 15 and supplied to the sequencer 18. As a result, 16
The bit drawing sequence ends. FIG. 3 shows the overall system configuration of an electronic computer for accessing the bitmap memory.

In this system, reference numeral 20 denotes a CPU for controlling the entire system, reference numeral 21 denotes a memory controller for controlling access to a bit map memory 25, reference numeral 22 denotes an access frequency calculation circuit shown in FIG. 1, and reference numeral 23 denotes a mask pattern generator (MP).
G) and 24 are barrel shifters (SHIFT).

The mask pattern generator (MPG) 23
Generates mask pattern data for extracting data of 8 bits or less from 16-bit data of PU20. The barrel shifter (SHIFT) 24 is used for aligning the 16-bit data of the CPU 20 with the 8-bit data width of the bit map memory 25 in cooperation with the mask pattern generator (MPG) 23. Execute

Data writing to the bit map memory 25 is executed by a mask pattern generator (MPG) 23 and a barrel shifter (SHIFT) 24, and the access sequence is terminated by an output control signal from the sequencer 18 of the access number operation circuit 22. Is done.

Next, referring to FIGS. 4 to 6, a mask pattern generator (MPG) 23 and a barrel shifter (SHIF)
The digit alignment operation of 16-bit data according to T) 24 will be described.

First, as shown in FIG. 4, in the first access, pattern data P1 of the mask pattern generator (MPG) 23 can write the latter 4 bits of the 8-bit storage area of the bit map memory 25. The shift data SD1 of the barrel shifter (SHIFT) 24 has a form in which 16-bit data is shifted to the right by 4 bits. As a result, the first four bits (bit 15 to bit 12) of the 16-bit data are written to the latter four bits in the storage area of the address 1 of the bit map memory 25.

In the second access, as shown in FIG. 5, the pattern data P2 of the mask pattern generator (MPG) 23 is a pattern which enables writing of all 8 bits of the 8-bit storage area of the bit map memory 25. Becomes
The shift data S of the barrel shifter (SHIFT) 24
D2 is a form in which 16-bit data is shifted right by 12 bits. As a result, the middle 8 bits (bits 11 to 4) of the 16-bit data are stored in the bit map memory 25.
Is written to the 8 bits of the storage area at address 2 of.

In the third access, as shown in FIG. 6, the pattern data P3 of the mask pattern generator (MPG) 23 can write the first four bits of the 8-bit storage area of the bit map memory 25. The shift data SD3 of the barrel shifter (SHIFT) 24 has a form in which 16-bit data is shifted to the right by 4 bits. As a result, the remaining 4 bits (bit 3 to bit 0) in the middle of the 16-bit data are written to the first 4 bits of the storage area of the address 3 of the bit map memory 25.

As described above, in this embodiment, C
The drawing start bit position specified by the PU and the drawing width of the data by the CPU are added by the adding circuit 13, and the final bit position to be drawn is obtained. When data is drawn in the bitmap memory, the value of the bit width of the storage area of the bitmap memory is subtracted from the value of the last bit position by the subtraction circuit 15 every time the data is drawn, until the result of the subtraction becomes zero or less. Drawing is repeated. Therefore, the number of accesses is automatically obtained only by specifying the drawing start bit position, so that data can be drawn without being aware of the bit width of the bitmap memory.

[0029]

As described in detail above, according to the present invention,
The number of accesses can be automatically obtained without considering the bit width of the bitmap memory, so that the drawing speed can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration for realizing a drawing method according to an embodiment of the present invention.

FIG. 2 is a view for explaining a drawing operation in the embodiment.

FIG. 3 is a block diagram showing a system configuration of the entire electronic computer using the circuit of FIG. 1;

FIG. 4 is an exemplary view for explaining a first example of a digit alignment operation of drawing data executed by the computer of FIG. 3;

FIG. 5 is an exemplary view for explaining a second example of a digit alignment operation of drawing data executed by the computer of FIG. 3;

FIG. 6 is an exemplary view for explaining a third example of a digit alignment operation of drawing data executed by the computer of FIG. 3;

[Explanation of symbols]

11 ... dot address register, 12 ... drawing width register, 13
... addition circuit, 14 ... selector, 15 ... subtraction circuit, 16 ... current register, 17 ... zero detection circuit, 18 ... sequencer.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/00-12/06 G06T 1/60

Claims (1)

(57) [Claims] A plurality of cases each having a predetermined bit width.
Write data to bitmap memory with storage area
Means for holding a value of a drawing start bit position when drawing, and the write data to be drawn in the bitmap memory
Means for holding the value of the drawing width, and the value of the drawing start bit position and the drawing of the write data.
And the final bit of the write data.
An addition circuit for obtaining a position value, and a subtraction circuit having first and second input terminals,
The bit of the write data for a first input
At the time of the first drawing to the map memory,
The output value of the road is input and subtracted for the second and subsequent drawing
The result value is input and the second input terminal
The bit of the storage area in the bitmap memory.
Is input to the first input terminal.
Subtracting the value input to the second input terminal from the
Path, and that the subtraction result of the subtraction circuit has become zero or less.
Output a control signal to end the drawing operation.
Access times characterized by having a
Arithmetic circuit.