JP2941677B2 - Digital signal transmission circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal transmission circuit for transmitting data using a ternary digital signal.

[0002]

2. Description of the Related Art For example, in various industrial machines and robots, many sensors and actuators are connected to a controller via signal lines, and operate according to commands from the controller. In such a case, data transmission is performed between the controller and the sensor or the like. As a transmission method, a serial transmission method using a ternary digital signal is conventionally known.

A ternary digital signal can be considered as a combination of a clock signal and a data signal as shown in FIG. The clock signal is output from the controller as a master unit at a constant cycle, and changes the potential between an intermediate level (12 V) and a high level (24 V). The data signal is output from a master unit or a terminal unit having a sensor or the like in synchronization with a clock signal, and changes the potential between an intermediate level (12 V) and a low level (0 V).

As shown in FIG. 6, a conventional master unit is provided with a communication controller 1 for controlling data transmission and a digital signal transmission circuit 2 for inputting and outputting digital signals. The digital signal transmission circuit 2 includes a clock output circuit 3 for outputting a clock signal, a data output circuit 4 for outputting a data signal, and a data input circuit 5. Also, the signal line 6
And a constant voltage / current circuit 7 having a constant current source function of outputting a constant current to the signal line 6 and a current flowing through the resistor R1. The two functions can be switched according to. If the current flowing through the resistor R1 is large, a VBE voltage required to turn on the transistor T1 is generated, the transistor T1 is turned on, the constant voltage / constant current circuit 7 functions as a constant current source, and the resistor R1 Is small, the transistor T1 is turned off and functions as a constant voltage source by the constant voltage diode D1.

When the clock output circuit 3 and the data output circuit 4 are turned off, the current flowing through the resistor R1 is small, so that the constant current voltage circuit 7 functions as a constant voltage source and the signal line 6 Held at an intermediate level. When the data output circuit 4 is turned on (the same data output circuit is also provided in the terminal unit, including when the data output circuit is turned on)
Since a large current flows through the resistor R1, the constant voltage / constant current circuit 7 functions as a constant current source to be in a high impedance state, and outputs a constant current to output the signal line 6.
To a low level.

[0006]

By the way, the clock output circuit is turned off and the signal line goes high (24).
When the voltage changes from V) to the intermediate level (12V), a back electromotive force occurs due to the influence of the inductance component of the signal line due to a change in current, and ringing occurs. At this time, if the influence of the inductance component is large, a large current flows through the constant voltage / constant current circuit. , The constant voltage / constant current circuit is brought into a high impedance state. As a result, the signal line has an intermediate level (12
V), the signal line swings further to the low level (0 V) side, and the signal line returns to the intermediate level (12 V). It swings greatly. Then, as shown in FIG. 7B, it gradually converges to the intermediate level (12 V) while vibrating. Such large ringing may cause a malfunction in the master unit or the terminal unit.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a digital signal transmission circuit capable of preventing a malfunction due to an influence of an inductance component of a signal line.

[0008]

In order to achieve the above object, a digital signal transmission circuit according to the present invention provides a signal line between a master unit and a terminal unit at a high-level, low-level, or intermediate-level voltage. A constant voltage source that performs signal transmission between both units and has a constant voltage source function of holding a signal line at an intermediate level and a constant current source function of entering a high impedance state and holding a signal line at a low level.
Timing detection to detect the change timing of the signal line from high level to intermediate level in a device that has a constant current circuit and switches between both functions according to the current flowing from the constant voltage / constant current circuit to the signal line And a constant voltage circuit for holding the signal line at a predetermined constant voltage for a predetermined time after detecting the change timing by the timing detection means (the invention of claim 1).

Further, the constant voltage circuit may be constituted by using a constant voltage source function in a constant voltage / constant current circuit (claim 2).

[0010]

According to the first aspect of the present invention, a digital signal having three values of a high level, an intermediate level, and a low level is transmitted to the signal line between the master unit and the terminal unit. Here, when the signal line changes from the high level to the intermediate level, the change timing is detected by the timing detecting means, and thereafter, the signal line is held at the predetermined voltage by the constant voltage circuit for a predetermined time. As a result, when the signal line changes from the high level to the intermediate level, the impedance is low because the signal line is held at a predetermined voltage by the constant voltage circuit even if a back electromotive force occurs in the signal line due to a change in current. In addition, the voltage of the signal line is prevented from dropping more than the intermediate level.

According to the second aspect of the present invention, when the signal line changes from the high level to the intermediate level, after the change timing is detected by the timing detection means, the constant voltage / voltage is changed.
The signal line is held at a predetermined constant voltage by the constant voltage source function of the constant current circuit.

[0012]

As described above, according to the present invention, when a signal line changes from a high level to an intermediate level, the signal line is held at a predetermined voltage. The occurrence of ringing is suppressed,
This prevents malfunctions of the master unit and the terminal unit.

Further, according to the second aspect of the present invention, when the signal line changes from the high level to the intermediate level, the constant voltage
Since the signal line is held at a predetermined constant voltage by the constant voltage source function of the constant current circuit, there is no need to provide a separate constant voltage circuit, which simplifies the circuit and reduces cost.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a data transmission device to which the digital signal transmission circuit of the present invention is applied will be described below with reference to FIGS. As shown in FIG. 4, the data transmission device according to the present embodiment includes a plurality of terminal units 1 connected to a signal line 12 derived from one master unit 11.
3 are connected. This master unit 1
Between the master unit 1 and the terminal unit 13
Each terminal unit 13 or the master unit 11 itself outputs a data signal in synchronization with a clock signal output from 1 at a constant period, and data transmission is performed. Here, the state in which the data signal is synchronized with the clock signal is a ternary digital signal as shown in FIG. 5A, and the portion where the potential changes between the intermediate level (12 V) and the high level (24 V). Is a clock signal, and the portion where the potential changes between the intermediate level (12 V) and the low level (0 V) is the data signal.

<Master Unit> As shown in FIGS. 1 and 2, the master unit 11 includes a communication controller 14 and a digital signal transmission circuit 15 corresponding to the present invention. Numeral 14 controls data transmission.

The digital signal transmission circuit 15 includes a clock output circuit 16 for outputting a clock signal, a data output circuit 17 for outputting a data signal, and a data input circuit 18 for receiving a data signal. Have been.

The clock output circuit 16 includes an inverting circuit A1 and two transistors T2 and T3. An output terminal O1 of the communication controller 14 is connected to the base of the transistor T2 via the inverting circuit A1. The collector side of the transistor T2 is connected to the base side of the transistor T3, and the transistor T3 is turned on when the transistor T2 is turned on. Further, the emitter side of the transistor T3 is V
The collector side is connected to the signal line 12 while being connected to CC (24V). When the output terminal O1 of the communication controller 14 is set to low level (0V), the clock output circuit 16 outputs the signal line 12 , A voltage of 24 V is output, and when the output terminal O1 is at a high level (5 V), the clock output circuit 16 is stopped.

The data output circuit 17 includes a transistor T4
The output terminal O2 of the communication controller 14 is connected to the base side, the emitter side is grounded to the ground via the resistor R2, and the collector side is connected to the signal line 12. Thus, when the output terminal O2 of the communication controller 14 is set to a high level (5 V), the transistor T4 is turned on, and the output terminal O2
Is set to the low level (0 V), the transistor T4 is turned off.

The data input circuit 18 comprises an inverting circuit A2 and a constant voltage diode D2 connected in series.
The cathode side of the constant voltage diode D2 is connected to the signal line 12, and the output side of the inverting circuit A2 is connected to the input terminal I1 of the communication controller 14. Thereby, if the signal line 12 is, for example, 6 V or more, the communication controller 14
Is set to low level (0 V), and is set to high level (5 V) if it is 6 V or less.

Further, the digital signal transmission circuit 15 has a constant voltage source function for maintaining the signal line 12 at an intermediate level (12 V) and a constant voltage source function for supplying a constant current to the signal line 12. A constant current circuit 19, a timing detection circuit 20 for detecting a change timing when the signal line 12 changes from a high level (24V) to an intermediate level (12V), and a predetermined time after the change timing is detected by the timing detection circuit 20 During the period, the constant voltage / constant current circuit 19 is switched to the constant voltage source function and held.
It has. The timing detecting circuit 20 and the constant voltage switching circuit 21 correspond to the change timing detecting means and the constant voltage circuit according to the present invention.

The constant voltage / constant current circuit 19 includes a constant voltage source 22 composed of a constant voltage diode D3 and a transistor T5. The constant voltage source 22 connects the cathode of the constant voltage diode D3 to the transistor T5. The transistor T5 functions as a constant voltage source by connecting the base side of the transistor T5 to the base side and grounding the anode side to the ground to make the voltage on the base side of the transistor T5 constant. In addition, constant voltage
The constant current circuit 19 includes a constant current source 23 including a transistor T6, and also functions as a constant current source. The constant current source function and the constant voltage source function depend on the current flowing through the resistor R3. It can be switched.

That is, if the current flowing through the resistor R3 is large, a voltage required to turn on the transistor T6 is generated at VBE of the transistor T6, and the transistor T6 is turned on to disable the constant voltage diode D3. The constant voltage / constant current circuit 19 functions as a constant current source. Also,
When the current flowing through the resistor R3 is small, the transistor T6 is turned off.
Functions as a constant voltage source by the constant voltage diode D3, and outputs a voltage obtained by subtracting the VBE voltage of the transistor T5, the voltage drop by the resistor R3, and the forward voltage of the diode D4 from the zener voltage of the constant voltage diode D3 to the signal line 12. You. The Zener voltage and the like are determined so that this voltage becomes an intermediate level (12 V).

The timing detecting circuit 20 comprises a differentiating circuit 30 comprising a resistor R4 and a capacitor C1, and an inverting circuit A3. The time constant of the differentiating circuit 30 is determined by the values of the capacitor C1 and the resistor R4. The input side of the differentiating circuit 30 is connected to the output side of the inverting circuit A1 in the clock output circuit 16, and when the output of the inverting circuit A1 changes from high level (5V) to low level (0V), its falling waveform is changed. The differentiated waveform is output. That is, a change timing pulse having a differential waveform is output from the inverting circuit A3 in accordance with the timing at which the clock output circuit 16 changes from the on state to the off state. The pulse width of the change timing pulse is determined by the time constant of the differentiating circuit 30. As a result, a change timing at which the signal line 12 changes from the high level (24 V) to the intermediate level (12 V) is detected.

The constant voltage switching circuit 21 includes a transistor T7
The base side is connected to the output side of the timing detection circuit 20, the collector side is connected to the base side of the transistor T7, and the emitter side is grounded to ground. As a result, while the change timing pulse is being output, the transistor T7 is turned on, and the base of the transistor T6 functioning as a constant current source in the constant voltage / constant current circuit 19 is set to 0V.
It is said. That is, after the signal line 12 changes from the high level (24V) to the intermediate level (12V) for a certain period of time,
The constant current source function of the constant voltage / constant current circuit 19 is invalidated,
The constant voltage / constant current circuit 19 is maintained as a constant voltage source.

<Terminal Unit> The terminal unit 13 includes a communication controller 24 and a digital signal transmission circuit 25, as shown in FIGS. The communication controller 24 controls data transmission similarly to the communication controller 14 of the master unit 11.

The digital signal transmission circuit 25 includes a data output circuit 26, a data input circuit 27, a clock input circuit 28
And a constant voltage / constant current circuit 29. The data output circuit 26 includes a transistor T8,
The base of the transistor T8 is the communication controller 2
4 is connected to the output terminal O3. The emitter side is grounded to the ground via a resistor R5, and the collector side is connected to the signal line 12. Thus, when the output terminal O3 of the communication controller 24 is at a high level (5 V), the transistor T8 is turned on, and the output terminal O3
Is set to the low level (0 V), the transistor T8 is turned off.

The data input circuit 27 is constituted by connecting a constant voltage diode D5 and an inverting circuit A4 in series. The cathode side of the constant voltage diode D5 is connected to the signal line 12, and the output side of the inverting circuit A4 is connected to the communication controller 24. Is connected to the input terminal I3. Thereby, the signal line 12
Is 6 V or more, for example, the input terminal I3 of the communication controller 24 is at a low level (0 V), and if it is 6 V or less, the input terminal I3 is at a high level (5 V).

The clock input circuit 28 is constituted by connecting a constant voltage diode D6 and an inverting circuit A5 in series. The cathode side of the constant voltage diode D6 is connected to the signal line 12, and the output side of the inverting circuit A5 is connected to the communication controller 24. Is connected to the input terminal I2. Thereby, the signal line 12
Is 18 V or more, for example, the input terminal I2 of the communication controller 24 is at a low level (0 V), and if it is 18 V or less, the input terminal I2 is at a high level (5 V).

The constant voltage / constant current circuit 29 has the same configuration as the constant voltage / constant current circuit 19 of the master unit 11, and includes a transistor T9 and a constant voltage diode D7, and a constant voltage source function and a transistor T10. The constant current source function can be switched according to the current flowing through the resistor R6.

Next, the operation of this embodiment will be described. <Data transmission from master unit 11 to each terminal unit 13> When the output terminal O1 of the communication controller 14 is set to a low level (0V) or a high level (5V), the transistors T2 and T3 are turned on at the low level (0V). The signal line 12 is set to a high level (24 V). At the high level (5 V), the transistors T2, T3
Is turned off and set to an intermediate level (12 V) by the constant voltage source function of the constant voltage / constant current circuit 19. Then, as shown in FIG. 5 (b), when the output terminal O1 is repeatedly switched to a low level (0V) and a high level (5V) at a constant cycle, the signal line 12 has an intermediate level (12V) and a high level. Clock pulses having a constant cycle of a level (24 V) are continuously output. Further, as shown in FIG. 5B, when the output terminal O1 of the communication controller 14 is at a low level (0 V), that is, when a high-level (24 V) voltage is not output to the signal line 12, the output of the communication controller 14 is output. When the terminal O2 is set to a high level (5 V), the transistor T4 is turned on, whereby the constant voltage / constant current circuits 19, 29 of the master unit 11 and the terminal unit 13 are supplied to the constant voltage / constant current circuits 19, 29. A current required to cause the constant voltage source to function as a constant current source flows, the constant voltage / constant current circuits 19 and 29 function as constant current sources, and the signal line 12 is set to a low level (0 V). Here, the number of clock pulses corresponds to the number of terminal units 13, and this clock pulse corresponds to the address of each terminal unit 13. For example, data synchronized with the first clock pulse is the first terminal pulse. The data for the unit 13, and the data synchronized with the second clock pulse becomes the data for the second terminal unit 13.

In each terminal unit 13, when the signal line 12 is set to the high level (24 V), the input terminal I 2 of the communication controller 24 is transmitted through the clock input circuit 28.
Is set to the low level (0 V), the communication controller 24 counts the number of clock pulses, and reads data synchronized with the clock pulse via the data input circuit 27 if the address matches the address value of the communication controller 24. At this time, if the signal line 12 is at the low level (0 V), data "0" is transmitted, and if it is at the intermediate level (12 V), data "1" is transmitted.

<Data Transmission from Terminal Unit 13 to Master Unit 11> A clock signal having a constant period is output from master unit 11 in the same manner as described above. In each terminal unit 13, the communication controller 24 counts the number of clock pulses via the clock input circuit 28. For example, data "0" is sent to the master unit 11.
Is transmitted, when the count value matches its own address value, the output terminal O3 of the communication controller 14 is set to a high level (5 V) to turn on the transistor T8. Then, the constant voltage / constant current circuits 19 and 29 of the master unit 11 and the terminal unit 13 have a constant voltage / constant voltage.
A current necessary for causing the constant current circuits 19, 29 to function as a constant current source flows, and the constant voltage / constant current circuits 19, 29
Function as a constant current source, and the signal line 12 goes low (0
V).

The master unit 11 reads data from the signal line 12 via the data input circuit 18 in synchronization with the clock pulse output from the master unit 11 and transmits the data from any terminal unit 13 in accordance with the count value of the clock pulse. It is determined whether the data is correct. For example, in synchronization with the second clock pulse, the input terminal I1 goes high (5
V), the second terminal unit 13
Means that the data "0" has been transmitted.

Here, the signal line 12 is at a high level (24
The operation of each circuit when changing from V) to the intermediate level (12V) will be described in detail. That is, the transistor T3 of the clock output circuit 16 of the master unit 11 switches from the ON state to the OFF state, and the signal line 12 is set to the intermediate level (12) by the constant voltage source function of the constant voltage / constant current circuits 19 and 29.
V). In this case, the timing detection circuit 20 outputs a change timing pulse in synchronization with the change timing as shown in FIG. 5B, and when the pulse is at the high level (5 V), the constant voltage switching circuit 21 Transistor T7 is turned on, and the base side of the transistor T6 of the constant voltage / constant current circuit 19 becomes 0
V. That is, the signal line 12 is at a high level (24 V).
After that, the base side of the transistor T6 is set to 0 V for a predetermined time, and the constant current source function is invalidated.

When the signal line 12 changes from the high level (24V) to the intermediate level (12V), the current on the signal line 12 changes, so that a back electromotive force is generated on the signal line 12 by the inductance component of the signal line 12. As a result, a large current flows through the resistor R3 of the constant voltage / constant current circuit 19.
However, at this time, conventionally, the transistor T6 is turned on, the constant voltage / constant current circuit 19 functions as a constant current source, and the voltage of the signal line 12 drops to a low level (0 V). However, in the present embodiment, since the base side of the transistor T6 is maintained at 0 V as described above, the constant voltage / constant current circuit 19 does not function as a constant current source, but retains the function as a constant voltage source. You. The voltage of the signal line 12 at this time is a value obtained by subtracting the VBE voltage of the transistor T5, the voltage drop of the resistor R3, and the forward voltage of the diode D4 from the Zener voltage of the constant voltage diode D3. Normally, the voltage is slightly lower than the voltage of the intermediate level (12 V) because the voltage is more than when the constant voltage / constant current circuit 19 functions as a constant voltage source.

As described above, in this embodiment, when the signal line 12 changes from the high level (24 V) to the intermediate level (12 V), the constant voltage / constant current circuit 19 holds the constant voltage source function for a predetermined time. Therefore, the constant voltage / constant current circuit 19 functions as a constant current source under the influence of the inductance component of the signal line 12 to prevent the voltage of the signal line 12 from dropping toward the low level (0 V). . This allows
Conventionally, the high level (24V) to the intermediate level (1
Since a large ringing does not occur at the time of the change to 2V), erroneous recognition of the signal by the master unit 11 and the terminal unit 13 is prevented, and thus a malfunction is eliminated.

When the clock output circuit 16 or the data output circuit 17 is turned on, that is, when the signal line 1
2 is high level (24V) or low level (0V)
In this case, the signal line 12 is connected to VCC (24 V) via the transistor T3 or to the ground via the transistor T4, so that the impedance is low and the ringing is large. Is unlikely to occur.

The present invention is not limited to the above embodiments, but can be modified as follows, for example, and these embodiments also belong to the technical scope of the present invention. (1) In the above embodiment, the constant voltage source 22 of the constant voltage / constant current circuit 19 is used as the constant voltage circuit of the present invention. A configuration may be provided in which a constant voltage circuit that holds the signal line at the intermediate level (12 V) for a predetermined time in synchronization with the timing of changing from the high level (24 V) to the intermediate level (12 V) is provided. In addition, the present invention can be implemented with various modifications without departing from the scope.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an entire embodiment.

FIG. 2 is a circuit diagram showing a master unit.

FIG. 3 is a circuit diagram showing a terminal unit.

FIG. 4 is a wiring diagram of the embodiment.

5A is a waveform diagram showing an ideal ternary digital signal, FIG. 5B is a timing chart showing a ternary digital signal in a state where a change timing pulse and damped oscillation are prevented, and FIG. It is a waveform diagram.

FIG. 6 is a circuit diagram showing a conventional master unit.

7A is a waveform diagram showing an ideal ternary digital signal, and FIG. 7B is a waveform diagram showing a ternary digital signal in an attenuated vibration state.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Master unit 12 ... Signal line 13 ... Terminal unit 15 ... Digital signal transmission circuit 19 ... Constant voltage / constant current circuit 20 ... Timing detection circuit (timing detection means) 22 ... Constant voltage source (constant voltage circuit)

Claims (2)

(57) [Claims] 1. A signal line between a master unit and a terminal unit is set to a high-level, low-level, or intermediate-level voltage to perform signal transmission between the two units.
A constant voltage / constant current circuit having a constant voltage source function of holding the signal line at the intermediate level and a constant current source function of entering a high impedance state and holding the signal line at a low level; A switching circuit that switches between the two functions in accordance with a current flowing from the current circuit to the signal line, wherein the timing detection unit detects a change timing of the signal line from a high level to an intermediate level; A constant voltage circuit for holding the signal line at a predetermined constant voltage for a predetermined time after detecting a change timing. 2. The digital signal transmission circuit according to claim 1, wherein said constant voltage circuit is configured using a constant voltage source function of said constant voltage / constant current circuit.