JP2941890B2 - Semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a semiconductor memory that can easily perform a screening test.

[Conventional technology]

Hitherto, as a method for realizing a high-integration and high-speed memory, a BiCMOS technology in which a bipolar transistor and a MOS transistor are formed on one chip has been proposed. As a memory to which the present technology is applied, for example, "1989 IE International Solid State Circuits Conference" (1989 IEEE Internat
ional Solid-State Circuits Conference pp28-29)
Described in the above.

[Problems to be solved by the invention]

However, in the related art, since the word lines and the bit lines need to be driven with a signal amplitude equal to the power supply voltage, there is a problem that the charging and discharging time of the word lines and the bit lines is long and the operation speed is slow.

In order to solve this problem, the present inventors have already proposed the semiconductor memory shown in FIG. 2 (Japanese Patent Application No. 1-292133).
issue). In the figure, MC1 and MC2 are memory cells, W is a word line, B10, B11, B20, and B21 are bit lines, S1 and S2 are sense circuits, WD is a word line selection driving circuit, and BD1 and BD2 are bit line selection driving. The circuit and OB are output buffers, and VAG and VBG are internal power supply voltage generation circuits. In the related art, the power supply of the memory cell is shared with the power supply of the memory chip. For example, ECL
(Emitter coupled logic) In the case of an input / output memory, VA = 0 V and VB = −5.2 V, and it was necessary to drive the word lines and bit lines with a signal amplitude of 5.2 V. In the semiconductor memory shown here, the power supply of the memory cells is generated by the internal power supply voltage generation circuits VAG and VBG provided inside the chip, and the voltage VA-VB applied to the memory cells is reduced to about 2 V, so that the word lines and The drive amplitude of the bit line is reduced to increase the speed. Further, by reducing the drive amplitudes of the word lines and the bit lines, the word line selection drive circuit WD and the bit line selection drive circuits BD1 and BD2 can be constituted by ECL circuits, thereby enabling a much higher speed.

However, the technique of FIG. 2 does not consider the screening test of the memory chip. That is,
During the screening test, it is necessary to apply a higher voltage to the memory cell than during normal operation. On the other hand, the internal power supply voltage generation circuits VAG and VBG need to be configured so that the potentials of VA and VB do not fluctuate even if the power supply voltage fluctuates, in order to prevent a reduction in the operation margin due to the power supply voltage fluctuation. Therefore, even if a high power supply voltage is applied to the memory chip, no high voltage is applied to the memory cells, and there is a problem that a screening test cannot be performed.

An object of the present invention is to provide a semiconductor memory that can easily perform a screening test.

[Means for solving the problem]

In order to achieve the above object, the present invention selectively drives a plurality of word lines, a plurality of bit lines, a plurality of memory cells arranged at intersections of the word lines and the bit lines, and the word lines. A word line selection drive circuit, and an internal power supply voltage generation circuit for supplying a power supply voltage to the memory cells,
In a semiconductor memory including an ECL circuit in the word line selection drive circuit, a first switch for separating the word line selection drive circuit from the word line; an internal power supply voltage generation circuit; and a low potential side power supply terminal of the memory cell. A second switch for disconnecting the memory cell, a third switch for short-circuiting the word line and the low-potential power supply terminal of the memory cell, and connecting the low-potential power supply terminal of the memory cell to an external power supply for screening test. A fourth switch is provided.

Also, the present invention provides a plurality of word lines, a plurality of bit lines, a plurality of memory cells arranged at intersections of the word lines and the bit lines, and a word line selection drive circuit for selectively driving the word lines. A semiconductor memory including an internal power supply voltage generation circuit for supplying a power supply voltage to the memory cell, wherein the word line selection drive circuit includes an ECL circuit, wherein the internal power supply voltage generation circuit and a high potential side power supply terminal of the memory cell are provided. And a fifth switch for disconnecting the switch.

Further, the present invention is characterized in that a sixth switch for connecting a high potential side power supply terminal of the memory cell to an external power supply for screening test is provided.

[Action]

In the semiconductor memory of the present invention, at the time of the screening test, the internal power supply voltage generating circuit is disconnected from the memory cell, and the power supply voltage of the memory cell is supplied from outside the memory chip. Thus, a high voltage can be applied to the memory cell regardless of the internal power supply voltage generation circuit, and a screening test can be easily performed.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1 FIG. 1 is a circuit diagram showing a first embodiment of the semiconductor memory of the present invention. In this embodiment, the circuit shown in FIG. 2 includes a first switch (MOS transistors MN101 and MP101) for separating the word line selection drive circuit WD and the word line W, an internal power supply voltage generation circuit VBG, and memory cells MC1 and MC2. A second switch (MOS transistor MN102,
MP102) and a third switch (MOS transistor MN103) for short-circuiting the word line W and the low potential side power supply terminals of the memory cells MC1 and MC2.

Hereinafter, the operation of this embodiment will be described with reference to FIG. In the figure, TE is a control signal, and a low potential is applied during a normal operation and a high potential is applied during a screening test. VEXT1 is an external power supply for screening test,
Apply a voltage lower than VB during the screening test First, consider normal operation. In this case, the control signal TE is at a low potential. Therefore, the MOS transistors MN101 and MP101
A first switch and a MOS transistor MN102,
The second switch composed of MP102 is conductive, and the third switch composed of MOS transistor MN103 is non-conductive. Therefore, the word line selection drive circuit WD is connected to the load line, and the internal power supply voltage generation circuit VBG is connected to the memory cells MC1 and MC2, so that normal operation is possible.

Next, consider the screening test. In this case, the control signal TE is at a high potential. Therefore, the MOS transistor MN1
01, first switch composed of MP101, MOS transistor MN
The second switch consisting of 102 and MP102 is non-conductive, and the third switch consisting of MOS transistor MN103 is conductive. Therefore, the word line selection drive circuit WD is disconnected from the word line W, the internal power supply voltage generation circuit VBG is disconnected from the memory cells MC1 and MC2, and the word line W and the low potential side power supply terminals of the memory cells MC1 and MC2 are short-circuited. Is done. Further, since the MOS transistor MN105 conducts, the word line W and the low-potential-side power supply terminals of the memory cells MC1 and MC2 are connected to the external power supply VEXT1 for screening test, and the potential of VEXT1 is made lower than VB. , MC2 can be applied with a high voltage.

In this embodiment, the reason why the word line W is cut off from the word line selection drive circuit WD and its potential is set to the same potential as VEXT1 is as follows. In the word line selection drive circuit WD constituted by the ECL circuit, the potential of the word line W cannot be lowered to VB or lower. Therefore, when the low-potential-side power supply potentials of the memory cells MC1 and MC2 are reduced by the external power supply VEXT1, the source potentials of the transfer MOS transistors MT0 and MT1 of the non-selected cells decrease, and MT0 and MT1 become conductive. As a result, a current flows through all the non-selected cells, the power supply current sharply increases, and the memory chip may be destroyed. In order to avoid this, in the present embodiment, the word line W is disconnected from the word line selection drive circuit WD, and the word line W is set to the same potential as the external power supply VEXT1, so that the current flows through the memory cells MC1 and MC2. Preventing.

Further, in this embodiment, when the external power supply VEXT1 is lower than VB and a high voltage is applied to the memory cells MC1 and MC2, the nMOS
The potential of the p-well needs to be reduced to the same level as that of the external power supply VEXT1 so that the source / drain diffusion layers and the p-wells of the memory cells MC1 and MC2 do not become forward biased. This is because, for example, the power supply line of the p-well and the memory cells MC1, MC2
It can be easily realized by short-circuiting the VB power supply line.

As described above, according to the present embodiment, the internal power supply voltage generation circuit VBG is connected to the memory cell MC during the screening test.
1. The power supply voltage of the memory cells MC1 and MC2 can be supplied from outside the memory chip by separating from the memory chip MC2. As a result, the memory cell M is independent of the internal power supply voltage generation circuit VBG.
A high voltage can be applied to C1 and MC2, and a screening test can be easily performed.

Embodiment 2 FIG. 3 is a circuit diagram showing a second embodiment of the semiconductor memory of the present invention. In the first embodiment shown in FIG. 1, the high voltage of the memory cell is applied by lowering the low potential power supply potential of the memory cell. However, in the present embodiment, the high potential power supply potential of the memory cell is raised. Indicates a case where a high voltage is applied to the memory cell. In this embodiment, the circuit shown in FIG. 2 includes a switch (MOS transistor MN1) that disconnects the internal power supply voltage generation circuit VAG and the high-potential power supply terminal of the memory cell.
11, MP111).

Hereinafter, the operation of this embodiment will be described with reference to FIG. In the figure, TE is a control signal, which is low potential during normal operation
During the screening test, a high potential is applied. Also,
VEXT2 is an external power supply for the screening test, and applies a voltage higher than VA during the screening test.

First, consider normal operation. In this case, the control signal TE is at a low potential. Therefore, MOS transistors MN111 and MP111
Is in a conductive state. For this reason, the internal power supply voltage generation circuit VAG is connected to the memory cells MC1 and MC2, and can operate normally.

Next, consider the screening test. In this case, the control signal TE is at a high potential. Therefore, the MOS transistor MN1
11. The switch composed of MP111 is off. For this reason, the internal power supply voltage generation circuit VAG is connected to the memory cells MC1, MC2
Disconnected from In addition, since the MOS transistor MP112 conducts, the high-potential-side power supply terminals of the memory cells MC1 and MC2 are connected to the screening test external power supply VEXT2, and the potential of the external power supply VEXT2 is raised above VA, so that the memory cells MC1 and MC2 are turned off. High voltage can be applied to MC2.

In this embodiment, the transfer MOS transistors MT0 and MT1 of the non-selected cells do not conduct even if the high-potential power supply potential of the memory cells MC1 and MC2 is raised by the external power supply VEXT2. There is no need to disconnect from the circuit WD.

In the present embodiment, when VEXT2 is raised above VA and a high voltage is applied to the memory cells MC1 and MC2, the source / drain diffusion layers of the pMOS and the n-wells of the memory cells MC1 and MC2 are not forward biased. , N-well also need to be raised to the same level as the external power supply VEXT2. This corresponds to, for example, the power supply line of the n-well and the VA of the memory cells MC1, MC2.
Can be easily realized by short-circuiting the power supply line.

Embodiment 3 FIGS. 4 (a) to 4 (c) are diagrams showing a third embodiment of the semiconductor memory of the present invention, and each show an example of a memory cell suitable for combination with the semiconductor memory of the present invention. It is a circuit diagram. (A) shows NMOS transistors MN0 and MN1 and resistors
This is a memory cell in which two inverters composed of R0 and R1 are connected to each other to form a flip-flop. Since this memory cell does not require well separation, there is an advantage that the memory cell area can be reduced.

(B) is a memory cell in which two inverters each including PMOS transistors MP0 and MP1 and resistors R0 and R1 are connected to each other to form a flip-flop. Since this memory cell also requires well separation, the memory cell area can be reduced.

(C) shows the case where the flip-flop and the bit line are connected by diodes D0 and D1. The portion of the flip-flop surrounded by a broken line may be configured by CMOS as shown here, or may be constituted by an NMOS transistor and a resistor or a PM.
It may be composed of an OS transistor and a resistor. This memory cell has the advantage that writing can be performed faster than the memory cells of (a) and (b).

Note that the memory cells that can be combined with the present invention are not limited to the examples given here, and the present invention can be applied to memory cells having similar characteristics.

As described above, the present invention has been specifically described based on the examples.
The present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the scope of the invention.

[Effects of the Invention] As described above, according to the present invention, the internal power supply voltage generation circuit can be disconnected from the memory cell during the screening test, and the power supply voltage of the memory cell can be supplied from outside the memory chip. A high voltage can be applied to the memory cell regardless of the power supply voltage generation circuit, and a screening test can be easily performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor memory of the present invention, FIG. 2 is a circuit diagram of a semiconductor memory showing a technique for solving the problems of the prior art, and FIG. 4A to 4C are circuit diagrams showing a second embodiment of the semiconductor memory of FIG.
(C) is a figure which showed the example of the memory cell suitable for combining with the semiconductor memory of this invention, respectively. MC1, MC2: Memory cell W: Word line B10, B11, B20, B21 ... Bit line WD ... Word line selection drive circuit BD1, BD2 ... Bit line selection drive circuit S1, S2 ... Sense circuit OB ... … Output buffer VAG, VBG …… Internal power supply potential generation circuit TE …… Control signal VEXT1 …… External power supply for screening test

──────────────────────────────────────────────────続 き Continuing on the front page (72) Kunihiko Yamaguchi 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Kazuo Kanaya 1-1280 Higashi Koigakubo, Kokubunji-shi, Tokyo Hitachi Central Research Laboratory (72) Inventor Hiroaki Nambu 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Inside the Hitachi, Ltd.Central Research Laboratories 72) Inventor Yoshiaki Sakurai 3681 Hayano Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (56) References JP-A-64-55857 (JP, A) JP-A-60-103587 (JP, A) JP-A Sho 62-252598 (JP, A) JP-A-63-181196 (JP, A) (58) Field (Int.Cl. ^6, DB name) G11C 29/00

Claims (3)

(57) [Claims] A plurality of word lines; a plurality of bit lines; a plurality of memory cells arranged at intersections of the word lines and the bit lines; a word line selection drive circuit for selectively driving the word lines; In a semiconductor memory having an internal power supply voltage generation circuit for supplying a power supply voltage to the memory cell, wherein the word line selection drive circuit includes an ECL circuit, a first switch for separating the word line selection drive circuit from the word line A second switch that disconnects the internal power supply voltage generation circuit from the low-potential power supply terminal of the memory cell; a third switch that short-circuits the word line and the low-potential power supply terminal of the memory cell; A semiconductor memory provided with a fourth switch for connecting a low potential side power supply terminal of the memory cell to an external power supply for screening test. 2. A plurality of word lines, a plurality of bit lines, a plurality of memory cells arranged at intersections of the word lines and the bit lines, a word line selection drive circuit for selectively driving the word lines, In a semiconductor memory having an internal power supply voltage generating circuit for supplying a power supply voltage to the memory cell, wherein the word line selection drive circuit includes an ECL circuit, the internal power supply voltage generating circuit, a high potential side power supply terminal of the memory cell, And a fifth switch for disconnecting the semiconductor memory. 3. The semiconductor memory according to claim 2, further comprising a sixth switch for connecting a high potential side power supply terminal of said memory cell to an external power supply for screening test.