JP2943244B2 - Video signal dubbing prevention device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal dubbing prevention apparatus for inhibiting illegal dubbing of a video signal in, for example, a VTR.

[Summary of the Invention]

The present invention relates to an apparatus for preventing dubbing of a video signal, which is obtained by inserting a signal sequentially generated through an arbitrary encryption circuit into a video signal and supplying the inserted signal to an arbitrary encryption circuit. By comparing the signal with the next inserted signal to determine whether dubbing is possible or not, illegal dubbing can be favorably prevented, and it is extremely difficult to form a release device of this prevention device. Is what you do.

[Conventional technology]

For example, dubbing a commercially available soft tape in a VTR is not only legally illegal, but also infringes the rights of authors and the like, and impedes the sound spread of VTRs and soft tapes.

Conventionally, for such illegal dubbing of a soft tape, for example, a plurality of pseudo horizontal sync pulses are inserted within a vertical blanking period, and a signal of a white peak level is provided at the trailing edge of the pseudo horizontal sync pulse. Therefore, the AGC of the VTR on the dubbing side is caused to malfunction. Alternatively, the width of the vertical synchronization signal is narrowed so that vertical synchronization of the dubbing-side VTR is not performed.

[Problems to be solved by the invention]

However, in any of these, the processing performed on the video signal is fixed, so that it is easy to change the signal, and a release device that changes a non-dubbable video signal into a dubbable one can be formed at low cost. Met.

The present application has been made in view of such a point, and it is intended to prevent dubbing satisfactorily and to make it extremely difficult to form a release device.

[Means for solving the problem]

A first means according to the present invention is to generate an arbitrary digital value in an encryption circuit (3) including at least an arbitrary operation means for an arbitrary initial value (A / D converter (2)), The digital value thus obtained is fed back to the initial value to sequentially generate the next digital value which sequentially changes every predetermined period (PLL (4)) of the video signal, and converts the generated digital value into an analog signal (D An A / A converter (5) is provided to prevent dubbing of a video signal and is inserted into a predetermined position of the video signal (switch (6)).

The second means digitizes a signal inserted at a predetermined position of the video signal at predetermined intervals (A / D converter (12))
The digitized value is supplied to an encryption circuit (13) including at least an arbitrary operation means, and the digital value generated by the encryption circuit is inserted into a predetermined position of the video signal in a next predetermined period. This is a video signal dubbing prevention apparatus which compares a digitized signal with a digitized value (coincidence detection circuit (15)) and disables dubbing when they do not match.

[Action]

According to this, since the signals sequentially generated by the encryption circuit are inserted into the predetermined position of the video signal, this signal can be supplied to the encryption circuit to easily determine whether dubbing is possible. At the same time, by including an arbitrary operation means in this encryption circuit, it is extremely difficult to form this circuit without permission, and it is possible to make the formation of a decryption device extremely difficult.

〔Example〕

FIG. 1 shows an example of an apparatus for generating a signal for permitting dubbing and inserting it into a predetermined position of a video signal.
In this figure, a video signal supplied to an input terminal (1) is digitized by an A / D converter (2) and supplied to an encryption circuit (3). At the same time, the video signal supplied to the input terminal (1) is supplied to the PLL (4) to form a horizontal / vertical synchronization signal and a clock signal, and these signals are also supplied to the encryption circuit (3).

As a result, an arbitrary digital value is sequentially generated from the encryption circuit (3) at a timing corresponding to a predetermined position of the video signal, and this digital value is converted into an analog signal by the D / A converter (5) and converted into an analog signal by the switch (6). Is supplied to one of the fixed contacts A. The video signal supplied to the input terminal (1) is supplied to the other fixed contact B. Further, the signal from the PLL (4) is supplied to the timing decoder (7) to form a signal corresponding to a predetermined position of the video signal. The switch (6) is switched by this signal to form a signal into which a signal sequentially formed by the encryption circuit (3) is inserted at a predetermined position of the video signal, and is taken out to the output terminal (8).

FIG. 2 shows a specific example of the encryption circuit (3). In this figure, the form of an analog signal inserted at a predetermined position in a video signal is, for example, a 16-sample signal of 4 values each (2 bits in digital value).

This signal is A / D converted, and the 2-bit signal (LSB / MSB) from the A / D converter (2) is supplied to a 16-bit shift register (31a) (31b) for serial-parallel conversion. The parallel outputs of the shift registers (31a) and (31b) are alternately arranged one bit at a time to form a 32-bit signal. The polarity of some of the bits is inverted by a group of inverters (32) provided so that this signal is, for example, 6 bits from the MSB in a 6-bit cycle and 3 bits are kept as they are, and the bit switching means (33) For example, from MSB to 5,
The bit order is inverted in units of 7, 9, and 11 bits, and a 32-bit shift register (3
4) supplied to.

And among the outputs of this shift register (34), for example,
2 ^0, 2 ^1, 2 ^2, the outputs of the 2 ²² exclusive OR circuit (3
5) is fed back to the serial input of the shift register (34) through, by the signal from 131071 counter (36) is supplied to the shift clock input of the shift register (34), on the Galois field GF (2 ³²⁾ ( ^{X 32 + X 22 + X 2} + X 1 +1)
Division by ¹³¹⁰⁷¹ is performed.

The parallel output of the shift register (34) is bit-reversed by the bit exchange means (37), for example, in the order of 5, 7, 9, and 11 bits from the MSB. The polarity of some bits is re-inverted by an inverter group (38) provided so that the three bits remain inverted. The re-inverted signal is alternately supplied one bit at a time to 16-bit shift registers (39a) and (39b) for parallel / serial conversion, and is extracted from the serial output of these shift registers (39a) and (39b). The bit signal (LSB / MSB) is supplied to the D / A converter (5).

Further, the horizontal / vertical synchronization signal and the clock signal from the PLL (4) are supplied to the timing decoder (40), and the signal formed by the decoder (40) is used as the shift register (31a) (31b) (39a). (39b) is supplied to the shift clock input of the shift register (34) (39a).
(39b) is supplied to the parallel load terminal.
It is supplied to one counter (36).

The digital value generated by the encryption circuit (3) in this way is supplied to the D / A converter (5), and the analog signal is inserted into a predetermined position of the video signal. Further, the digital values from the shift registers (39a) and (39b) are fed back to the shift registers (31a) and (31b), so that the next digital value that is sequentially changed every predetermined period of the video signal is sequentially generated. .

That is, FIG. 3 shows a procedure of signal generation. This example is applied to a so-called high-vision video signal.

In this figure, FIG. 7A shows the values of four-valued signals generated in the previous field, and these values are converted into 2-bit digital values as shown in FIG. Further, some of these bits are inverted in polarity to have a value as shown in FIG. C, and this bit value is inverted in a predetermined unit to have a value as shown in FIG. This value is set to a value as shown in FIG. The bit order of this value is re-inverted within a predetermined unit to obtain a value as shown in FIG. F, and some of these bits are inverted in polarity to obtain a value as shown in FIG. Then, a quaternary signal as shown in FIG. H is generated from each two bits of this value, and an analog signal as shown in FIG. I corresponding to this value is formed. Further, this signal is inserted at a predetermined position in a vertical blanking period of the video signal, for example, to form a video signal as shown in FIG.

For example, when dubbing is not allowed,
As shown in FIG. 4A, only the original video signal is recorded. On the other hand, when dubbing is permitted,
As shown in (1), a video signal having the above-described signal inserted therein is recorded at a predetermined position (for example, the ninth horizontal scanning line) in the vertical blanking period. Alternatively, a video signal having the above-described signal inserted may be recorded at a predetermined position in the effective screen as shown in FIG.

FIG. 5 shows an example of an apparatus for determining whether dubbing is possible or not using the above-mentioned signals. In this figure, a video signal supplied to an input terminal (11) is digitized by an A / D converter (12) and supplied to an encryption circuit (13) having the same configuration as the above-described encryption circuit (3). Is done. At the same time, the video signal supplied to the input terminal (11) is
The horizontal and vertical synchronizing signals and the clock signal are formed at 4), and these signals are also supplied to the encryption circuit (13).

As a result, the above-described arbitrary digital value is generated from the encryption circuit (13) based on the signal inserted into the predetermined position of the video signal. This digital value is supplied to the coincidence detection circuit (15), and the digital value from the A / D converter (12) is supplied to the coincidence detection circuit (15), and this detection output is supplied to the latch circuit (16). Is done. Further PLL (14)
Is supplied to the timing decoder (17) to form a signal corresponding to a predetermined position of the video signal. The latch circuit (16) is driven by this signal, and the coincidence detecting circuit (15) is sequentially turned on at a predetermined position of the video signal.
The signal detected at is latched and taken out to the output terminal (18).

Therefore, in this circuit, when the signal inserted at a predetermined position of the video signal coincides with the signal generated by the encryption circuit (13) from the signal of the immediately preceding field, the coincidence detection circuit (15) The detected signal is latched, and a control output enabling dubbing is taken out from the output terminal (18). On the other hand, when the signal inserted at a predetermined position of the video signal does not match the signal generated by the encryption circuit (13) from the signal of the immediately preceding field, the match detection circuit (15) No detection signal is obtained, and dubbing of the video signal at this time is prohibited.

Thus, according to the above-described device, the signals sequentially generated by the encryption circuit are inserted into the predetermined position of the video signal, so that the signals are supplied to the encryption circuit to easily determine whether dubbing is possible. In addition, by including an arbitrary operation means in this encryption circuit, it is extremely difficult to form this circuit without permission, and it is possible to make the formation of a release device extremely difficult.

That is, in the above device, the signal inserted into the video signal is changed for each field,
Therefore, it is extremely difficult to form this signal by means other than the above-described encryption circuit. On the other hand, this encryption circuit is composed of a complicated digital arithmetic processing circuit as described above.
Can be formed by an integrated LSI or the like together with a digital circuit for processing a video signal, and can be easily implemented, and it is extremely difficult to form an illegal release device due to misuse of the LSI or the like. be able to. In this case, the A / D converters (2) and (12) and the PLL (4)
(14) The circuits such as the D / A converter (5) can be omitted because they are shared with the video signal processing circuit.

In the above-described apparatus, when a signal to permit dubbing is recorded on a tape on which a signal to permit dubbing is already recorded, the last field of the recorded signal is reproduced. This signal is supplied to an encryption circuit to form the next signal. An arbitrary random signal can be used as an initial value when recording on a new tape.

In the above-mentioned encryption circuit, the inverter group (38)
By performing arbitrary error correction coding after the output of (1) and performing error correction before input of the inverter group (32), it is possible to prevent malfunction due to noise or the like during signal transmission.

Further, in implementing the above-described apparatus, it is necessary to provide a circuit for forming the above-mentioned dubbing-permitting signal in a video camera whose signal can always be dubbed. In a television tuner, a video enhancer, an AV selector, and the like, in which a signal is always allowed to be dubbed, it is necessary to have a characteristic in which a dubbing-enabled signal inserted in a signal transmitting side device such as a broadcasting station is transmitted. .

By the way, in the high-definition broadcasting described above, Muse
A method of transmitting only an effective screen of a video signal called VTR has been implemented, and a VTR based on this method has been proposed.

That is, FIG. 6 shows a recording pattern of a VTR in the Muse system. In this example, the 581st to 1120th horizontal scanning lines of the effective screen of the odd field are distributed to four tracks as shown in FIG. Is what you are doing. When this signal is reproduced, the signal in the vertical blanking period is restored as shown in FIG. B, and the original Hi-Vision signal is output.

In this case, for example, as shown in FIG. 7, if the 1120th horizontal scanning line in the effective screen is set to the area of the above-mentioned signal that allows dubbing, this signal is a signal in the video signal band. Because of this, this signal can be transmitted with the conventional configuration, and good dubbing prevention can be performed by providing the recording side VTR with a device for determining whether or not dubbing is possible.

On the other hand, if it is not recognized that the effective screen is damaged, an arbitrary identification signal of the postamble portion of the fourth track is provided as shown in FIG. As shown in the figure, the signal in the vertical blanking period is restored, and the discrimination signal is discriminated to form a signal enabling dubbing described above. Scan line). As a result, the recording side VTR can determine whether or not the above-described dubbing is possible.

Further, FIG. 9 shows an example of an apparatus for generating a signal for enabling dubbing in that case and inserting the signal into a predetermined position of the video signal. In this figure, a signal obtained by restoring the above-described vertical blanking period is supplied to an input terminal (1), and an AND gate (9) is provided in a signal path from the above-mentioned timing decoder (7). The gate (9) is supplied with the discrimination output of the identification signal from the terminal (11). Others are the same as the above-mentioned apparatus. According to this, a signal that allows dubbing is inserted into the reproduction signal only when the identification signal is determined, and the above-described determination of whether or not dubbing can be performed can be performed by the VTR on the recording side.

FIG. 10 shows an example in which the above-described apparatus is integrated with an apparatus for determining whether dubbing is possible or not. In this figure, the digital value from the encryption circuit (3) is supplied to the coincidence detection circuit (15), and the digital value from the A / D converter (2) is supplied to the coincidence detection circuit (15). The detection output is supplied to the latch circuit (16).
Further, the latch circuit (16) is driven by the signal from the timing decoder (7), and the signals detected by the coincidence detection circuit (15) are sequentially latched and taken out to the output terminal (18). According to this, the device can be realized with an extremely simple configuration by sharing a circuit.

In implementing these devices, the so-called Muse
It is necessary to provide a similar circuit in a broadcast decoder device or the like. In that case, the decoder device of Muse broadcasting and the VT of Muse system
In R, video signal processing is performed digitally, so A / D
Circuits such as the converter (2), the PLL (4), and the D / A converter (5) can be omitted because they are shared with the video signal processing circuit.

〔The invention's effect〕

According to the present invention, since the signals sequentially generated by the encryption circuit are inserted at predetermined positions of the video signal,
By supplying this signal to the encryption circuit, it is possible to easily determine whether dubbing is possible or not, and it becomes extremely difficult to form this circuit without permission by including any arithmetic means in the encryption circuit. The formation of the release device can be made extremely difficult.

[Brief description of the drawings]

FIG. 1 is a block diagram of an example of a device for generating a signal for enabling dubbing and inserting the signal into a predetermined position of a video signal in a video signal dubbing prevention device according to the present invention, and FIG. 2 is an encryption circuit. FIG. 3 is a diagram showing a signal generation procedure, FIG. 4 is a waveform diagram showing an example of a video signal, and FIG. 5 is a diagram for determining whether dubbing is possible or not. 6 to 8 are diagrams each showing an example of a VTR recording pattern and a reproduction signal in the Muse system,
FIG. 9 and FIG. 10 are block diagrams each showing an example of an apparatus for generating a signal for enabling dubbing of the video signal dubbing prevention apparatus in the Muse system and inserting the signal into a predetermined position of the video signal. (1) (11) is an input terminal, (2) and (12) are A / D converters,
(3) (13) is an encryption circuit, (4) (14) is a PLL,
(5) is a D / A converter, (6) is a switch, (7) (17)
Is a timing decoder, (8) and (18) are output terminals, (1
5) is a coincidence detection circuit, and (16) is a latch circuit.

Claims (2)

(57) [Claims] An encryption circuit including at least an arbitrary operation means generates an arbitrary digital value with respect to an arbitrary initial value, and returns the generated digital value to the initial value to thereby provide a predetermined period of a video signal. A dubbing prevention apparatus for a video signal, which sequentially generates the next digital value that sequentially changes every time, converts the generated digital value into an analog signal, and inserts the analog value into a predetermined position of the video signal. 2. A signal inserted into a predetermined position of a video signal at predetermined intervals is digitized, and the digitized value is supplied to an encryption circuit including at least an arbitrary operation means, and is generated by the encryption circuit. The digital value thus obtained is compared with a digitized value of a signal inserted at a predetermined position of the video signal in the next predetermined period, and when the values do not match, dubbing is disabled to prevent dubbing of the video signal. apparatus.