JP2946848B2 - Container for semiconductor device - Google Patents
Container for semiconductor deviceInfo
- Publication number
- JP2946848B2 JP2946848B2 JP17737491A JP17737491A JP2946848B2 JP 2946848 B2 JP2946848 B2 JP 2946848B2 JP 17737491 A JP17737491 A JP 17737491A JP 17737491 A JP17737491 A JP 17737491A JP 2946848 B2 JP2946848 B2 JP 2946848B2
- Authority
- JP
- Japan
- Prior art keywords
- side wall
- metal
- ceramic
- metal side
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 239000002184 metal Substances 0.000 claims description 41
- 239000000919 ceramic Substances 0.000 claims description 34
- 230000035882 stress Effects 0.000 description 9
- 238000005219 brazing Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 230000008646 thermal stress Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910017309 Mo—Mn Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【0001】[0001]
【産業上の利用分野】本発明は半導体装置用容器に関
し、特に気密封止用の金属で構成された半導体装置用容
器に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device container, and more particularly to a semiconductor device container made of a metal for hermetic sealing.
【0002】[0002]
【従来の技術】従来の半導体素子を気密封止する半導体
装置用の容器は、図3(a)及び(b)に夫々平面図及
び正面図を示すように、金属材を加工した金属側壁1で
囲まれるキャビティ2を構成し、このキャビティ内に半
導体素子を搭載するようにしている。この金属側壁1の
外側には放熱板3が一体に設けられる。又、金属側壁1
の一部は切り欠かれて切欠部4が設けられ、この切欠部
4にセラミックス側壁5が配置され、このセラミックス
側壁5の周囲の全面においてAgロー材7により金属側
壁1に一体化されている。このセラミックス側壁5には
外部導出リード6がキャビティ2の内外にわたって貫通
支持されており、キャビティ2内に搭載される半導体素
子に電気接続される。2. Description of the Related Art Conventionally, a container for a semiconductor device for hermetically sealing a semiconductor element has a metal side wall 1 formed by processing a metal material as shown in plan and front views in FIGS. 3 (a) and 3 (b), respectively. A cavity 2 surrounded by is formed, and a semiconductor element is mounted in this cavity. A heat radiating plate 3 is integrally provided outside the metal side wall 1. Also, metal side wall 1
Is cut out to form a cutout portion 4, a ceramic side wall 5 is arranged in the cutout portion 4, and the entire surface around the ceramic side wall 5 is integrated with the metal side wall 1 by an Ag brazing material 7. . An external lead 6 is supported by the ceramic side wall 5 so as to extend through the inside and outside of the cavity 2, and is electrically connected to a semiconductor element mounted in the cavity 2.
【0003】[0003]
【発明が解決しようとする課題】このような従来の半導
体装置用容器では、セラミックス側壁5の周囲全面にお
いて金属側壁1にロー接されているため、熱履歴に対す
る金属側壁1とセラミックス側壁5の熱膨張率が相違す
ることから、半導体素子の搭載時における金属側壁1の
熱収縮によりセラミックス側壁5に熱応力が加わり、セ
ラミックス側壁5にクラックが生じるという問題があ
る。又、電気特性検査時等において金属側壁1及び放熱
板3を検査用治具で固定した場合に、これらを構成する
金属部材に加わる圧力によりセラミックス側壁5に応力
が加わって同様にクラックが生じるという問題がある。
本発明の目的はセラミックス側壁のクラックを防止した
半導体装置用容器を提供することにある。In such a conventional semiconductor device container, since the entire peripheral surface of the ceramic side wall 5 is in low contact with the metal side wall 1, the heat of the metal side wall 1 and the ceramic side wall 5 with respect to the heat history is reduced. Since the expansion coefficients are different, thermal stress is applied to the ceramic side wall 5 due to thermal shrinkage of the metal side wall 1 at the time of mounting the semiconductor element, and there is a problem that cracks occur in the ceramic side wall 5. Further, when the metal side wall 1 and the heat sink 3 are fixed by an inspection jig at the time of an electrical characteristic test or the like, stress is applied to the ceramic side wall 5 due to the pressure applied to the metal members constituting the metal side wall 1 and the heat radiating plate 3, and cracks are similarly generated. There's a problem.
An object of the present invention is to provide a container for a semiconductor device in which cracks on a ceramic side wall are prevented.
【0004】[0004]
【課題を解決するための手段】本発明の半導体装置用容
器は、金属側壁に設けた切欠部の側面に複数個の凹凸部
を設け、セラミックス側壁をこの凹凸部の凸面のみに接
触した状態で固着した構成とする。又、切欠部に沿う金
属側壁の外側面に複数個の凹凸部を設けている。According to the present invention, there is provided a semiconductor device container, wherein a plurality of concave and convex portions are provided on a side surface of a notch provided on a metal side wall, and a ceramic side wall is connected only to the convex surface of the concave and convex portion.
It is configured to be fixed in the state of touch . Further, a plurality of uneven portions are provided on the outer surface of the metal side wall along the cutout portion.
【0005】[0005]
【作用】本発明によれば、切欠部に設けた凸面でのみ金
属側壁とセラミックス側壁が接触されるため、金属側壁
に生じた応力がセラミックス側壁にそのまま伝えられる
ことはなく、セラミックス側壁のクラックが防止され
る。又、金属側壁の外側面に設けた凹凸部により金属側
壁の応力が緩和され、セラミックス側壁に影響する応力
が低減される。According to the present invention, since the metal side wall and the ceramic side wall contact only at the convex surface provided in the notch, the stress generated on the metal side wall is not transmitted to the ceramic side wall as it is, and cracks on the ceramic side wall are generated. Is prevented. Further, the stress on the metal side wall is reduced by the uneven portion provided on the outer surface of the metal side wall, and the stress affecting the ceramic side wall is reduced.
【0006】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の半導体装置用容器の一実施例を示
し、同図(a)は平面図、同図(b)は正面図である。
これまでと同様に金属を加工した側壁1を形成し、内部
に半導体素子を搭載するためのキャビティ2を形成す
る。金属側壁1の外側には放熱板3が一体に形成され
る。又、金属側壁1の内面、内底面等はMo−Mn等で
のメタライズが施されている。更に、金属側壁1の一部
は切り欠かれて切欠部4が設けられ、ここにセラミック
ス側壁5が配設され、外部導出リード6を支持してい
る。このセラミックス側壁5は金属側壁1にAgロー材
7で接続されているが、このセラミックス側壁5に対向
する金属側壁1の切欠部4の側面には、切削加工等によ
って金属側壁の厚さ方向に沿った複数個の凹凸部8を形
成している。そして、この凹凸部8の凸面でのみ金属側
壁1とセラミックス側壁5が接触され、この接触部にお
いてのみ前記Agロー材7での接続が行われている。Next, the present invention will be described with reference to the drawings. 1A and 1B show an embodiment of a semiconductor device container according to the present invention, wherein FIG. 1A is a plan view and FIG. 1B is a front view.
As in the past, a metal-processed side wall 1 is formed, and a cavity 2 for mounting a semiconductor element therein is formed therein. A heat sink 3 is integrally formed outside the metal side wall 1. The inner surface, inner bottom surface, and the like of the metal side wall 1 are metallized with Mo-Mn or the like. Further, a part of the metal side wall 1 is cut out to form a cutout portion 4, in which a ceramic side wall 5 is provided to support an external lead 6. The ceramic side wall 5 is connected to the metal side wall 1 by an Ag brazing material 7, and the side surface of the notch 4 of the metal side wall 1 facing the ceramic side wall 5 is formed by cutting or the like in the thickness direction of the metal side wall. A plurality of uneven portions 8 are formed along the same. The metal side wall 1 and the ceramic side wall 5 are in contact only at the convex surface of the uneven portion 8, and the connection with the Ag brazing material 7 is performed only at this contact portion.
【0007】この構成によれば、金属側壁1とセラミッ
クス側壁5は凹凸部8の凸面のみで接触されてAgロー
材7でロー付けされているため、両者は微小な面積で接
触されることになる。このため、半導体素子搭載時の熱
応力或いは電気特性検査時の治具固定時の機械的応力が
金属側壁1に生じても、この応力がセラミックス側壁5
に影響することを緩和することが可能となり、セラミッ
クス側壁5におけるクラック発生を抑制することができ
る。因に、本実施例の半導体装置用容器によれば、ある
条件下での半導体素子搭載時のセラミック側壁のクラッ
クは従来容器の3個/20個の発生に対し、0個/20個と
良好な結果を得ている。According to this configuration, the metal side wall 1 and the ceramic side wall 5 are contacted only by the convex surface of the uneven portion 8 and brazed by the Ag brazing material 7, so that both are brought into contact with a very small area. Become. For this reason, even if thermal stress at the time of mounting a semiconductor element or mechanical stress at the time of fixing a jig at the time of electrical characteristic inspection occurs on the metal side wall 1, this stress is applied to the ceramic side wall 5.
Can be alleviated, and the occurrence of cracks in the ceramic side wall 5 can be suppressed. According to the semiconductor device container of the present embodiment, the number of cracks on the ceramic side wall when the semiconductor element is mounted under a certain condition is as good as 0/20 cracks compared with 3/20 in the conventional container. Results have been obtained.
【0008】図2は本発明の第2実施例を示しており、
(a)は平面図、(b)は正面図である。尚、図1と同
一部分には同一符号を付してある。この実施例では、金
属側壁1の外部導出リード6側の二つの外側面を切削等
により加工して凹凸部9を形成する。又、金属側壁1に
設けた切欠部4に配設したセラミックス側壁5はAgロ
ー材7で金属側壁1にロー付けするが、この場合にはセ
ラミックス側壁5の外部角部はロー付けしないように構
成している。FIG. 2 shows a second embodiment of the present invention.
(A) is a plan view and (b) is a front view. The same parts as those in FIG. 1 are denoted by the same reference numerals. In this embodiment, the two outer surfaces of the metal side wall 1 on the side of the external lead 6 are machined by cutting or the like to form the uneven portion 9. Also, the ceramic side wall 5 provided in the cutout 4 provided in the metal side wall 1 is brazed to the metal side wall 1 with an Ag brazing material 7, but in this case, the outer corners of the ceramic side wall 5 are not brazed. Make up.
【0009】この構成では、金属側壁1の外側面に凹凸
部9を設けることで、金属側壁1に生じる熱応力及び機
械応力を金属側壁1自身の変形で緩和させ、セラミック
ス側壁5に応力が伝達されることを防止する。これによ
り、セラミックス側壁5におけるクラックを有効に防止
することが可能となる。In this configuration, the unevenness 9 is provided on the outer surface of the metal side wall 1 so that the thermal stress and the mechanical stress generated on the metal side wall 1 are alleviated by the deformation of the metal side wall 1 itself, and the stress is transmitted to the ceramic side wall 5. To prevent it from being done. Thus, cracks in the ceramic side wall 5 can be effectively prevented.
【0010】[0010]
【発明の効果】以上説明したように本発明は、半導体装
置用容器の金属側壁に設けたセラミックス側壁を配置す
る切欠部に複数個の凹凸部を設け、その凹凸部の凸面の
みに接触した状態でセラミックス側壁を固着しているの
で、又金属側壁の外側面に複数個の凹凸部を設けている
ので、半導体素子搭載時の熱応力或いは電気特性検査時
の治具固定時の機械的応力がセラミックス側壁に及ぼす
影響を低減し、セラミックス側壁のクラック発生を低減
させるという効果を有する。As described above, according to the present invention, a plurality of concave and convex portions are provided in a notch portion where a ceramic side wall provided on a metal side wall of a semiconductor device container is arranged , and the convex surface of the concave and convex portion is provided.
Since the ceramic side wall is fixed in contact with only the outer surface of the metal side wall, a plurality of irregularities are provided. This has the effect of reducing the effect of the mechanical stress on the ceramic side wall and reducing the occurrence of cracks on the ceramic side wall.
【図1】本発明の第1実施例を示し、(a)は平面図、
(b)は正面図である。FIG. 1 shows a first embodiment of the present invention, wherein (a) is a plan view,
(B) is a front view.
【図2】本発明の第2実施例を示し、(a)は平面図、
(b)は正面図である。FIG. 2 shows a second embodiment of the present invention, wherein (a) is a plan view,
(B) is a front view.
【図3】従来の半導体装置用容器を示し、(a)は平面
図、(b)は正面図である。3A and 3B show a conventional semiconductor device container, wherein FIG. 3A is a plan view and FIG. 3B is a front view.
1 金属側壁 2 キャビティ 3 放熱板 4 切欠部 5 セラミックス側壁 6 外部導出リード 7 Agロー材 8,9 凹凸部 DESCRIPTION OF SYMBOLS 1 Metal side wall 2 Cavity 3 Heat sink 4 Notch 5 Ceramics side wall 6 Outer lead 7 Ag brazing material 8, 9 Concavo-convex part
Claims (2)
収納するキャビティを有し、この金属側壁の一部に設け
た切欠部をセラミックス側壁で構成してなる半導体装置
用容器において、前記金属側壁の切欠部の側面に複数個
の凹凸部を設け、前記セラミックス側壁を前記金属側壁
の前記凹凸部の凸面のみに接触した状態で固着したこと
を特徴とする半導体装置用容器。1. A semiconductor device container having a cavity surrounded by a metal side wall and accommodating a semiconductor element therein, wherein a cutout provided in a part of the metal side wall is constituted by a ceramic side wall. Multiple on the side of the notch on the side wall
Of the uneven portion is provided, the ceramic sidewall of the metal sidewall the uneven portion of the convex surface only container and wherein a firmly fixed in contact with the.
収納するキャビティを有し、この金属側壁の一部に設け
た切欠部をセラミックス側壁で構成してなる半導体装置
用容器において、前記切欠部に沿う前記金属側壁の外側
面に複数個の凹凸部を設けたことを特徴とする半導体装
置用容器。2. A semiconductor device container comprising a cavity surrounded by a metal side wall and accommodating a semiconductor element therein, and a notch provided in a part of the metal side wall is constituted by a ceramic side wall. the plurality of uneven portions semiconductor device for containers, characterized in that a on the outer surface of the metal side wall along the section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17737491A JP2946848B2 (en) | 1991-06-22 | 1991-06-22 | Container for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17737491A JP2946848B2 (en) | 1991-06-22 | 1991-06-22 | Container for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04373152A JPH04373152A (en) | 1992-12-25 |
| JP2946848B2 true JP2946848B2 (en) | 1999-09-06 |
Family
ID=16029837
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17737491A Expired - Fee Related JP2946848B2 (en) | 1991-06-22 | 1991-06-22 | Container for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2946848B2 (en) |
-
1991
- 1991-06-22 JP JP17737491A patent/JP2946848B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04373152A (en) | 1992-12-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |