JP2960835B2 - Low noise converter circuit - Google Patents
Low noise converter circuitInfo
- Publication number
- JP2960835B2 JP2960835B2 JP16678593A JP16678593A JP2960835B2 JP 2960835 B2 JP2960835 B2 JP 2960835B2 JP 16678593 A JP16678593 A JP 16678593A JP 16678593 A JP16678593 A JP 16678593A JP 2960835 B2 JP2960835 B2 JP 2960835B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- local oscillator
- semiconductor integrated
- converter circuit
- intermediate frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Description
【0001】[0001]
【産業上の利用分野】本発明は、受信アンテナで受信し
た放送衛星からの信号を増幅および周波数変換してチュ
ーナ回路に出力する低雑音コンバータ回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low noise converter circuit for amplifying and frequency converting a signal from a broadcasting satellite received by a receiving antenna and outputting the signal to a tuner circuit.
【0002】[0002]
【従来の技術】ローノイズ・ブロック・ダウン・コンバ
ータ(以下、LNB、という)は受信アンテナで受信し
た周波数10数GHzの水平偏波信号および垂直偏波信
号を低雑音増幅し、さらに周波数1GHz前後の中間周
波信号に変換して後段のチューナ回路に出力するもので
ある。2. Description of the Related Art A low-noise block down converter (hereinafter referred to as LNB) amplifies low-noise signals of a horizontal polarization signal and a vertical polarization signal having a frequency of several tens of GHz, which are received by a receiving antenna. The signal is converted into an intermediate frequency signal and output to a tuner circuit at the subsequent stage.
【0003】図4に示す従来のLNB回路は、水平およ
び垂直偏波信号を同時に受信して出力する2出力型の回
路で、各偏波信号毎に構成した2系統の回路によって各
偏波信号を増幅および周波数変換するもので、各系の混
合回路には1つの局部発振器から局部発振信号が2分割
して供給されている。The conventional LNB circuit shown in FIG. 4 is a two-output type circuit that receives and outputs horizontal and vertical polarization signals at the same time. Is amplified and frequency-converted, and a local oscillation signal is divided into two and supplied from one local oscillator to a mixing circuit of each system.
【0004】すなわち、この回路は入力端子21に入力
した水平偏波信号HPを3段構成のHEMT(高電子移
動度トランジスタ)素子からなる低雑音増幅回路(以
下、LNA、という)22で増幅し、混合回路23で局
部発振器24からの局部発振信号Lo と混合して中間周
波信号IHに変換し、スイッチ回路25を経て2段構成
の中間周波増幅回路(以下、IFA、という)26(ま
たは27)で適切なレベルの信号に増幅して出力端子2
8(または29)から出力する。That is, this circuit amplifies a horizontally polarized signal HP input to an input terminal 21 by a low noise amplifier (hereinafter referred to as LNA) 22 composed of a three-stage HEMT (high electron mobility transistor) element. In a mixing circuit 23, the signal is mixed with a local oscillation signal Lo from a local oscillator 24, converted into an intermediate frequency signal IH, and passed through a switch circuit 25 to a two-stage intermediate frequency amplifier circuit (hereinafter referred to as IFA) 26 (or 27). ) To amplify the signal to an appropriate level and output to terminal 2
8 (or 29).
【0005】また、入力端子30に入力した垂直偏波信
号VPを、LNA22と同一構成のLNA31で低雑音
増幅し、混合回路32で局部発振器24からの局部発振
信号Lo と混合して中間周波信号IV に変換し、スイ
ッチ回路25を経て2段構成のIFA27(または2
6)で適切なレベルの信号に増幅して出力端子29(ま
たは28)から出力する。Further, the vertically polarized signal VP input to the input terminal 30 is amplified with low noise by an LNA 31 having the same configuration as the LNA 22, and mixed with a local oscillation signal Lo from a local oscillator 24 by a mixing circuit 32 to produce an intermediate frequency signal. IV, and through a switch circuit 25, a two-stage IFA 27 (or 2
In 6), the signal is amplified to an appropriate level and output from the output terminal 29 (or 28).
【0006】図5は、局部発振器24から2つの混合回
路23,32にY形電力分配器33を通して局部発振信
号Lo を供給する構成を示した図である。また、図6
は、ミキサ素子としてガリウム砒素ショットキダイオー
ドを用いた混合回路23,32を、局部発振器24に対
して互いに対称となるように配置することで高アイソレ
ーション(水平偏波信号と垂直偏波信号との分離度)を
得ることができた構成である。FIG. 5 is a diagram showing a configuration in which a local oscillation signal Lo is supplied from a local oscillator 24 to two mixing circuits 23 and 32 through a Y-type power divider 33. FIG.
Is disclosed in Japanese Patent Application Laid-Open No. H11-27138. By disposing mixing circuits 23 and 32 each using a gallium arsenide Schottky diode as a mixer element so as to be symmetrical with respect to a local oscillator 24, high isolation (a difference between a horizontally polarized signal and a vertically polarized signal) can be achieved. (Degree of separation).
【0007】[0007]
【発明が解決しようとする課題】ところで、混合回路と
してダイオードミキサを使用した場合、混合回路には増
幅作用がないためLNAの増幅素子を多段構成としなけ
ればならず、回路基板の小型化が困難となる。However, when a diode mixer is used as a mixing circuit, the mixing circuit has no amplifying action, so that the LNA amplifying element must have a multistage configuration, making it difficult to reduce the size of the circuit board. Becomes
【0008】そこで、増幅素子とミキサ素子とを含むM
MIC(マイクロ波モノリシック集積回路)を使用して
低コスト化および小型化を実現するようにしたコンバー
タ回路が提案されている。しかし、ミキサ素子としてF
ET(電界効果トランジスタ)やHEMT素子またはこ
れらのアクティブ素子を含むMMICを使用する場合、
局部発振器と2つのMMICとをY形電力分配器で接続
すると、MMIC間での影響がダイオードミキサに比べ
て大きくなり、アイソレーションが悪化するという不都
合がある。[0008] Therefore, M including an amplifying element and a mixer element
2. Description of the Related Art A converter circuit has been proposed which realizes cost reduction and miniaturization using an MIC (microwave monolithic integrated circuit). However, as a mixer element, F
When using an ET (field effect transistor), HEMT element or MMIC including these active elements,
When a local oscillator and two MMICs are connected by a Y-type power divider, the influence between the MMICs is greater than that of a diode mixer, and there is a disadvantage that isolation is deteriorated.
【0009】また、MMICの構造上、ピン配置が1通
りであるため、図7に示すように、Y形電力分配器33
と2つのMMIC41,42とを接続する場合、MMI
C41,42の局発入力ピンがこの図においては共にパ
ッケージの下側に位置しているため、MMIC42の配
線は破線で示すように迂回しなければならず、局部発振
器24に対して2つのMMIC41,42を対称に配置
できないことになる。このため、局部発振信号Lo をM
MIC41,42に均等に分配できないといった不都合
が生じる。Further, since the MMIC has a single pin arrangement due to the structure of the MMIC, as shown in FIG.
When connecting the two MMICs 41 and 42, the MMI
Since the local input pins of C41 and C42 are both located on the lower side of the package in this figure, the wiring of the MMIC 42 must be bypassed as shown by a broken line, and two MMICs 41 are connected to the local oscillator 24. , 42 cannot be arranged symmetrically. Therefore, the local oscillation signal Lo is set to M
There is a disadvantage that the MICs 41 and 42 cannot be equally distributed.
【0010】そこで、本発明は局部発振信号の電力を2
つの混合回路に均等に2分割して供給し、かつ回路基板
の小型を図ることを目的とする。Therefore, the present invention reduces the power of the local oscillation signal by two.
An object of the present invention is to evenly divide and supply two mixed circuits to one mixed circuit and to reduce the size of the circuit board.
【0011】[0011]
【課題を解決するための手段】本発明は、受信アンテナ
で受信した水平および垂直偏波信号を中間周波信号に変
換して出力する2出力型の低雑音コンバータ回路におい
て、水平および垂直偏波信号を中間周波信号に変換する
ミキサ素子を含む第1および第2のマイクロ波半導体集
積回路と、第1および第2のマイクロ波半導体集積回路
に局部発振信号を供給する局部発振器と、局部発振器と
第1および第2のマイクロ波半導体集積回路とを接続す
るY形電力分配器とを設け、第1および第2の半導体集
積回路は、局部発振器に対しY形電力分配器を介して互
いに対称となる位置に配置されるように互いに異なるピ
ン配置を有するように構成する。SUMMARY OF THE INVENTION The present invention provides a two-output low noise converter circuit for converting a horizontal and vertical polarization signal received by a receiving antenna into an intermediate frequency signal and outputting the intermediate frequency signal. First and second microwave semiconductor integrated circuits including a mixer element for converting a signal into an intermediate frequency signal, a local oscillator for supplying a local oscillation signal to the first and second microwave semiconductor integrated circuits, a local oscillator and a second oscillator. A Y-type power divider for connecting the first and second microwave semiconductor integrated circuits, wherein the first and second semiconductor integrated circuits are symmetric with respect to the local oscillator via the Y-type power divider. It is configured to have different pin arrangements so as to be arranged at positions.
【0012】この場合、第1および第2の半導体集積回
路は、共にY形電力分配器側に局部発振信号入力ピンを
有し、それぞれコンデンサを介してY形電力分配器に接
続されている。In this case, each of the first and second semiconductor integrated circuits has a local oscillation signal input pin on the Y-type power splitter side, and is connected to the Y-type power splitter via a capacitor.
【0013】[0013]
【作用】本発明の構成において、第1および第2のマイ
クロ波半導体集積回路は、局部発振器に対して互いに対
称の位置に配置されるように互いに異なるピン配置、例
えば共にY形電力分配器側に局部発振信号入力ピンを有
している。このため、局部発振器からの局部発振信号は
Y形電力分配器を介して均等に2分配されて供給され
る。In the structure of the present invention, the first and second microwave semiconductor integrated circuits are arranged in mutually different pins so as to be arranged symmetrically with respect to the local oscillator. Has a local oscillation signal input pin. For this reason, the local oscillation signal from the local oscillator is equally divided into two and supplied via the Y-type power divider.
【0014】[0014]
【実施例】図1は、本発明によるコンバータ回路の一実
施例を示すブロック図である。本実施例は、水平偏波信
号HPが入力される入力端子1と垂直偏波信号VPが入
力される入力端子2とを備え、入力端子1は2段構成の
HEMT素子からなるLNA3に接続され、入力端子2
は同じく2段構成のHEMT素子からなるLNA4に接
続されている。FIG. 1 is a block diagram showing an embodiment of a converter circuit according to the present invention. This embodiment includes an input terminal 1 to which a horizontal polarization signal HP is input and an input terminal 2 to which a vertical polarization signal VP is input. The input terminal 1 is connected to an LNA 3 composed of a two-stage HEMT element. , Input terminal 2
Are also connected to an LNA 4 composed of two-stage HEMT elements.
【0015】LNA3の出力はアクティブミキサを含む
MMIC5に接続され、LNA4の出力は同じくアクテ
ィブミキサを含むMMIC6に接続されている。MMI
C5には、図4に示すスイッチ回路25も含まれている
ので、MMIC6の出力はMMIC5に接続されてい
る。MMIC5および6には、後述するように、局部発
振器7からの局部発振信号Lo が均等に分配されるよう
に接続されている。The output of LNA 3 is connected to MMIC 5 containing an active mixer, and the output of LNA 4 is connected to MMIC 6 also containing an active mixer. MMI
Since the switch circuit 25 shown in FIG. 4 is also included in C5, the output of the MMIC 6 is connected to the MMIC 5. As will be described later, the MMICs 5 and 6 are connected so that the local oscillation signal Lo from the local oscillator 7 is evenly distributed.
【0016】MMIC5の出力は、1段構成のIFA8
および9に接続されており、増幅回路8,9の出力は、
それぞれ出力端子10および11に接続されている。The output of the MMIC 5 is a one-stage IFA 8
And 9, the outputs of the amplifier circuits 8, 9 are
They are connected to output terminals 10 and 11, respectively.
【0017】図2は、2つのMMIC5,6と局部発振
器7との接続関係を示す配置図である。この場合、MM
IC5は、図3(a) に示すように、図においてパッケー
ジの左側に信号入力ピン5aが、右側に信号出力ピン5
bが、上側に直流電源DCの供給される直流電源ピン5
cが、下側に局部発振信号Lo が入力される局発入力ピ
ン5dがそれぞれ配置された構成となっている。FIG. 2 is a layout diagram showing a connection relationship between the two MMICs 5 and 6 and the local oscillator 7. In this case, MM
As shown in FIG. 3 (a), the IC 5 has a signal input pin 5a on the left side of the package and a signal output pin 5 on the right side.
b is the DC power supply pin 5 on the upper side to which the DC power supply DC is supplied.
c has a configuration in which local oscillation input pins 5d to which the local oscillation signal Lo is input are arranged on the lower side.
【0018】これに対し、MMIC6は、図3(b) に示
すように、図においてパッケージの左側に信号入力ピン
6aが、右側に信号出力ピン6bが、上側に局発入力ピ
ン6cが、下側に直流電源ピン6dがそれぞれ配置され
た構成となっており、MMIC5とは直流電源ピンと局
発入力ピンとが入れ替わった構造となっている。On the other hand, as shown in FIG. 3B, the MMIC 6 has a signal input pin 6a on the left side of the package, a signal output pin 6b on the right side, a local oscillation input pin 6c on the upper side, and a lower side of the package. The DC power supply pins 6d are arranged on the sides, and the MMIC 5 has a structure in which the DC power supply pins and the local oscillation input pins are interchanged.
【0019】このため、図2に示すように、局部発振器
7に対するMMIC5,6の位置が鏡像となり、Y形電
力分配器12を通って局発電力を均等に2分配する構成
を実現できる。また、この実施例では、局発伝送線路上
にコンデンサC1,C2を挿入することによって高アイ
ソレーション設計が可能となり、さらに、ピン配置のみ
ならず電力分配器で2系統回路に存在するMMICが結
合されるところで互いのMMICの影響を少なくし、高
アイソレーションの実現が可能な構成となっている。For this reason, as shown in FIG. 2, the position of the MMICs 5 and 6 with respect to the local oscillator 7 becomes a mirror image, and a configuration can be realized in which the local oscillator power is equally distributed into two through the Y-type power divider 12. Further, in this embodiment, a high isolation design becomes possible by inserting the capacitors C1 and C2 on the local transmission line. Further, not only the pin arrangement but also the MMIC existing in the two-system circuit is coupled by the power distributor. In this case, the effects of the MMICs are reduced so that high isolation can be realized.
【0020】この構成において、入力端子1に入力した
水平偏波信号HPはLNA3によって低雑音増幅され、
MMIC5で局部発振信号Lo と混合されて中間周波数
信号IHに周波数変換される。例えば、LNA3で増幅
された周波数10.95〜11.7GHzの水平偏波信号H
Pが、MMIC5内の混合回路で周波数10GHzの局
部発振信号Lo と混合されて周波数950〜1700M
Hzの中間周波信号IHに変換される。入力端子2に入
力した垂直偏波信号VPも同様にして中間周波信号IV
に変換される。In this configuration, the horizontally polarized signal HP input to the input terminal 1 is amplified by the LNA 3 with low noise,
The MMIC 5 mixes the frequency with the local oscillation signal Lo and frequency-converts it into an intermediate frequency signal IH. For example, a horizontally polarized signal H having a frequency of 10.95 to 11.7 GHz amplified by the LNA 3
P is mixed with a local oscillation signal Lo having a frequency of 10 GHz by a mixing circuit in the MMIC 5 to produce a frequency of 950 to 1700 M
Hz intermediate frequency signal IH. Similarly, the vertical polarization signal VP input to the input terminal 2 is the intermediate frequency signal IV.
Is converted to
【0021】中間周波信号IHおよびIVは、MMIC
5内のスイッチ回路によって切り換えられ、中間周波信
号IHはIFA8(または9)で増幅された後に出力端
子10(または11)から出力され、中間周波信号IV
はIFA9(または8)で増幅された後に出力端子11
(または10)から出力される。The intermediate frequency signals IH and IV are
5, and the intermediate frequency signal IH is output from the output terminal 10 (or 11) after being amplified by the IFA 8 (or 9).
Is output terminal 11 after being amplified by IFA 9 (or 8).
(Or 10).
【0022】[0022]
【発明の効果】本発明によれば、ピン配置の異なる2種
類のMMICを使用することによって2つのMMICを
Y形電力分配器に対して対象に配置することができるの
で、局部発振信号の電力を均等に分割して供給すること
ができる。According to the present invention, by using two types of MMICs having different pin arrangements, two MMICs can be arranged symmetrically with respect to the Y-type power divider, so that the power of the local oscillation signal can be reduced. Can be supplied evenly divided.
【0023】また、アクティブミキサを含むMMICを
使用することによって、基板の小型化を図ることがで
き、加えて前後の増幅回路、すなわちLNAおよびIF
Aの段数を減らすことができるので、部品点数の削減お
よび伝送線路の簡素化によってさらなる小型化を図るこ
とができ、LNBの低コスト化および小型化が可能とな
る。Further, by using the MMIC including the active mixer, the size of the substrate can be reduced, and in addition, the front and rear amplifier circuits, that is, the LNA and the IF
Since the number of stages A can be reduced, the number of parts can be reduced and the transmission line can be simplified, so that the size can be further reduced, and the cost and size of the LNB can be reduced.
【図1】本発明による低雑音コンバータ回路の一実施例
を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of a low noise converter circuit according to the present invention.
【図2】局部発振器とMMICとの接続状態を示す配置
図である。FIG. 2 is a layout diagram showing a connection state between a local oscillator and an MMIC.
【図3】異なる2種類のピン配置を有するMMICの構
成図である。FIG. 3 is a configuration diagram of an MMIC having two different types of pin arrangements.
【図4】従来の低雑音コンバータ回路の一例を示すブロ
ック図である。FIG. 4 is a block diagram showing an example of a conventional low noise converter circuit.
【図5】Y形電力分配器による局部発振器と混合回路と
の結合関係を示す図である。FIG. 5 is a diagram showing a coupling relationship between a local oscillator and a mixing circuit by a Y-type power divider.
【図6】混合回路としてショットキダイオードを使用し
た構成図である。FIG. 6 is a configuration diagram using a Schottky diode as a mixing circuit.
【図7】混合回路としてMMICを使用できないことを
説明する図である。FIG. 7 is a diagram illustrating that an MMIC cannot be used as a mixing circuit.
1,2 入力端子 3,4 低雑音増幅回路(LNA) 5,6 MMIC 7 局部発振器 8,9 中間周波増幅回路(IFA) 10,11 出力端子 12 Y形電力分配器 5a,6a 信号入力ピン 5b,6b 信号出力ピン 5c,6d 直流電源ピン 5d,6c 局発入力ピン 1, 2 input terminal 3, 4 low noise amplifier (LNA) 5, 6 MMIC 7 local oscillator 8, 9 intermediate frequency amplifier (IFA) 10, 11 output terminal 12 Y-type power divider 5a, 6a signal input pin 5b , 6b Signal output pins 5c, 6d DC power supply pins 5d, 6c Local oscillation input pins
Claims (2)
偏波信号を中間周波信号に変換して出力する2出力型の
低雑音コンバータ回路において、 前記水平および垂直偏波信号を中間周波信号に変換する
ミキサ素子を含む第1および第2のマイクロ波半導体集
積回路と、 前記第1および第2のマイクロ波半導体集積回路に局部
発振信号を供給する局部発振器と、 前記局部発振器と前記第1および第2のマイクロ波半導
体集積回路とを接続するY形電力分配器とを備え、 前記第1および第2の半導体集積回路は、前記局部発振
器に対し前記Y形電力分配器を介して互いに対称の位置
に配置されるように互いに異なるピン配置を有すること
を特徴とする低雑音コンバータ回路。1. A two-output low-noise converter circuit for converting a horizontal and vertical polarization signal received by a receiving antenna into an intermediate frequency signal and outputting the intermediate frequency signal, wherein the horizontal and vertical polarization signals are converted to an intermediate frequency signal. First and second microwave semiconductor integrated circuits including a mixer element, a local oscillator for supplying a local oscillation signal to the first and second microwave semiconductor integrated circuits, a local oscillator, and the first and second microwave oscillators. And a Y-shape power divider for connecting the microwave semiconductor integrated circuit to the local oscillator. The first and second semiconductor integrated circuits are symmetrically positioned with respect to the local oscillator via the Y-shape power splitter. A low-noise converter circuit having different pin arrangements so as to be arranged.
は、共に前記Y形電力分配器側に局部発振信号入力ピン
を有し、それぞれコンデンサを介して前記Y形電力分配
器に接続されていることを特徴とする請求項1記載の低
雑音コンバータ回路。2. The first and second semiconductor integrated circuits both have a local oscillation signal input pin on the Y-shape power divider side, and are respectively connected to the Y-shape power splitter via capacitors. The low noise converter circuit according to claim 1, wherein
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16678593A JP2960835B2 (en) | 1993-07-06 | 1993-07-06 | Low noise converter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16678593A JP2960835B2 (en) | 1993-07-06 | 1993-07-06 | Low noise converter circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0730333A JPH0730333A (en) | 1995-01-31 |
| JP2960835B2 true JP2960835B2 (en) | 1999-10-12 |
Family
ID=15837635
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16678593A Expired - Lifetime JP2960835B2 (en) | 1993-07-06 | 1993-07-06 | Low noise converter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2960835B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102201789B (en) * | 2010-07-14 | 2014-04-23 | 锐迪科科技有限公司 | LNB down-conversion chip circuit and chip, LNB down-conversion circuit and method |
-
1993
- 1993-07-06 JP JP16678593A patent/JP2960835B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0730333A (en) | 1995-01-31 |
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